Re: [PATCH] arm64: dts: rockchip: Add cache information to the SoC dtsi for RK356x

[Dragan Simic <dsimic@manjaro.org>]

Hello Anand,

On 2024-03-04 10:21, Anand Moon wrote:
> On Mon, 4 Mar 2024 at 00:35, Dragan Simic <dsimic@manjaro.org> wrote:
>> 
>> Add missing cache information to the Rockchip RK356x SoC dtsi, to 
>> allow
>> the userspace, which includes /proc/cpuinfo and lscpu(1), to present 
>> proper
>> RK3566 and RK3568 cache information.  Also, it gets rid of the 
>> following
>> error in the kernel log:
>> 
>>   cacheinfo: Unable to detect cache hierarchy for CPU 0
>> 
>> The cache parameters for the RK356x dtsi were obtained and partially 
>> derived
>> by hand from the cache size and layout specifications found in the 
>> following
>> datasheets and technical reference manuals:
>> 
>>   - Rockchip RK3566 datasheet, version 1.1
>>   - Rockchip RK3568 datasheet, version 1.3
>>   - ARM Cortex-A55 revision r1p0 TRM, version 0100-00
>>   - ARM DynamIQ Shared Unit revision r4p0 TRM, version 0400-02
>> 
>> For future reference, here's a rather detailed summary of the 
>> documentation,
>> which applies to both Rockchip RK3566 and RK3568 SoCs:
>> 
>>   - All caches employ the 64-byte cache line length
>>   - Each Cortex-A55 core has 32 KB of L1 4-way, set-associative 
>> instruction
>>     cache and 32 KB of L1 4-way, set-associative data cache
>>   - There are no L2 caches, which are per-core and private in 
>> Cortex-A55,
>>     because it belongs to the ARM DynamIQ IP core lineup
>>   - The entire SoC has 512 KB of unified L3 16-way, set-associative 
>> cache,
>>     which is shared among all four Cortex-A55 CPU cores
>>   - Cortex-A55 cores can be configured without private per-core L2 
>> caches,
>>     in which case the shared L3 cache appears to them as an L2 cache;  
>> this
>>     is the case for the RK356x SoCs, so let's use "cache-level = <2>" 
>> to
>>     prevent the "huh, no L2 caches, but an L3 cache?" confusion among 
>> the
>>     users viewing the data presented to the userspace;  another option 
>> could
>>     be to have additional 0 KB L2 caches defined, which may be 
>> technically
>>     correct, but would probably be even more confusing
>> 
>> Helped-by: Anand Moon <linux.amoon@gmail.com>
>> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
>> ---
> 
> Thanks, Please add my
> Reviewed-by: Anand Moon <linux.amoon@gmail.com>

Thank you for your review.

>> Notes:
>>     As already agreed upon with Anand Moon, this patch replaces the 
>> submission
>>     of a similar, albeit a bit incorrect patch [1] that appeared a bit 
>> earlier
>>     on the linux-rockchip mailing list.
>> 
>>     [1] 
>> https://lore.kernel.org/linux-rockchip/20240226182310.4032-1-linux.amoon@gmail.com/T/#u
>> 
>>  arch/arm64/boot/dts/rockchip/rk356x.dtsi | 41 
>> ++++++++++++++++++++++++
>>  1 file changed, 41 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi 
>> b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
>> index c19c0f1b3778..6dfb2d47d3d0 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
>> @@ -57,36 +57,77 @@ cpu0: cpu@0 {
>>                         #cooling-cells = <2>;
>>                         enable-method = "psci";
>>                         operating-points-v2 = <&cpu0_opp_table>;
>> +                       i-cache-size = <0x8000>;
>> +                       i-cache-line-size = <64>;
>> +                       i-cache-sets = <128>;
>> +                       d-cache-size = <0x8000>;
>> +                       d-cache-line-size = <64>;
>> +                       d-cache-sets = <128>;
>> +                       next-level-cache = <&l3_cache>;
>>                 };
>> 
>>                 cpu1: cpu@100 {
>>                         device_type = "cpu";
>>                         compatible = "arm,cortex-a55";
>>                         reg = <0x0 0x100>;
>>                         #cooling-cells = <2>;
>>                         enable-method = "psci";
>>                         operating-points-v2 = <&cpu0_opp_table>;
>> +                       i-cache-size = <0x8000>;
>> +                       i-cache-line-size = <64>;
>> +                       i-cache-sets = <128>;
>> +                       d-cache-size = <0x8000>;
>> +                       d-cache-line-size = <64>;
>> +                       d-cache-sets = <128>;
>> +                       next-level-cache = <&l3_cache>;
>>                 };
>> 
>>                 cpu2: cpu@200 {
>>                         device_type = "cpu";
>>                         compatible = "arm,cortex-a55";
>>                         reg = <0x0 0x200>;
>>                         #cooling-cells = <2>;
>>                         enable-method = "psci";
>>                         operating-points-v2 = <&cpu0_opp_table>;
>> +                       i-cache-size = <0x8000>;
>> +                       i-cache-line-size = <64>;
>> +                       i-cache-sets = <128>;
>> +                       d-cache-size = <0x8000>;
>> +                       d-cache-line-size = <64>;
>> +                       d-cache-sets = <128>;
>> +                       next-level-cache = <&l3_cache>;
>>                 };
>> 
>>                 cpu3: cpu@300 {
>>                         device_type = "cpu";
>>                         compatible = "arm,cortex-a55";
>>                         reg = <0x0 0x300>;
>>                         #cooling-cells = <2>;
>>                         enable-method = "psci";
>>                         operating-points-v2 = <&cpu0_opp_table>;
>> +                       i-cache-size = <0x8000>;
>> +                       i-cache-line-size = <64>;
>> +                       i-cache-sets = <128>;
>> +                       d-cache-size = <0x8000>;
>> +                       d-cache-line-size = <64>;
>> +                       d-cache-sets = <128>;
>> +                       next-level-cache = <&l3_cache>;
>>                 };
>>         };
>> 
>> +       /*
>> +        * There are no private per-core L2 caches, but only the
>> +        * L3 cache that appears to the CPU cores as L2 caches
>> +        */
>> +       l3_cache: l3-cache {
>> +               compatible = "cache";
>> +               cache-level = <2>;
>> +               cache-unified;
>> +               cache-size = <0x80000>;
>> +               cache-line-size = <64>;
>> +               cache-sets = <512>;
>> +       };
>> +
>>         cpu0_opp_table: opp-table-0 {
>>                 compatible = "operating-points-v2";
>>                 opp-shared;
> 
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