Re: [PATCH V4 03/13] perf tools: Support new branch sample type for LBR TOS

["Liang, Kan" <kan.liang@linux.intel.com>]

On 11/19/2019 4:31 PM, Peter Zijlstra wrote:
> On Tue, Nov 19, 2019 at 11:00:00AM -0800, Stephane Eranian wrote:
>> On Tue, Nov 19, 2019 at 6:35 AM <kan.liang@linux.intel.com> wrote:
> 
>>> diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h
>>> index bb7b271397a6..c2da61c9ace7 100644
>>> --- a/tools/include/uapi/linux/perf_event.h
>>> +++ b/tools/include/uapi/linux/perf_event.h
>>> @@ -180,7 +180,10 @@ enum perf_branch_sample_type_shift {
>>>
>>>          PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT      = 16, /* save branch type */
>>>
>>> -       PERF_SAMPLE_BRANCH_MAX_SHIFT            /* non-ABI */
>>> +       PERF_SAMPLE_BRANCH_MAX_SHIFT            = 17, /* non-ABI */
>>> +
>>> +       /* PMU specific */
>>
>> No! You must abstract this.
>>
>>> +       PERF_SAMPLE_BRANCH_LBR_TOS_SHIFT        = 63, /* save LBR TOS */
>>>   };
>>>
>> I don't like this because this is too Intel specific.
>> What is the meaning of this field? You need a clear definition so it can be used
>> with other PERF_SAMPLE_BRANCH_* implementations.
> 
> I also detest the MSB usage. Normal pattern is that any bit >= MAX
> will be rejected by the kernel.
>

OK. I will still use bit 17 for the new branch sample type.

I can change the Intel specific name, and use a generic name. How about 
PERF_SAMPLE_BRANCH_PMU_SPECIFIC?

If we make it generic, there will be another question. How much space 
should we reserve for this new branch sample type?
For LBR TOS, we only need a u64.
I'm not sure if it's good enough for other platforms.

Or maybe we want a flexible space as below?
@@ -849,7 +854,12 @@ enum perf_event_type {
          *        char                  data[size];}&& PERF_SAMPLE_RAW
          *
          *      { u64                   nr;
-        *        { u64 from, to, flags } lbr[nr];} && 
PERF_SAMPLE_BRANCH_STACK
+        *        { u64 from, to, flags } lbr[nr];
+        *
+        *        # only available if PERF_SAMPLE_BRANCH_PMU_SPECIFIC is set
+        *        u64                   nr;
+        *        u64                   data[nr];
+        *      } && PERF_SAMPLE_BRANCH_STACK
          *
          *      { u64                   abi; # enum perf_sample_regs_abi
          *        u64                   regs[weight(mask)]; } && 
PERF_SAMPLE_REGS_USER


Thanks,
Kan