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From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 6/7] drm/i915/gen11: Program the Y and UV plane for planar mode correctly.
Date: Sat, 22 Sep 2018 11:37:09 +0200	[thread overview]
Message-ID: <936dd554-c8ed-4ab9-52fd-2acc510593b7@linux.intel.com> (raw)
In-Reply-To: <20180921190137.GK5565@intel.com>

Op 21-09-18 om 21:01 schreef Ville Syrjälä:
> On Fri, Sep 21, 2018 at 07:39:44PM +0200, Maarten Lankhorst wrote:
>> The UV plane is the master plane that does all color correction etc.
>> It needs to be programmed with the dimensions for color plane 1 (UV).
>>
>> The Y plane just feeds the Y pixels to it. Program the scaler from the
>> master only, and set PLANE_CTL_YUV420_Y_PLANE on the slave plane.
>>
>> Changes since v1:
>> - Make a common skl_program_plane, and use it for both plane updates.
>>
>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h     |  1 +
>>  drivers/gpu/drm/i915/intel_sprite.c | 50 +++++++++++++++++++++--------
>>  2 files changed, 38 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index b614a06b66c4..a3129a4c15cc 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6511,6 +6511,7 @@ enum {
>>  #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)
>>  #define   PLANE_CTL_ORDER_BGRX			(0 << 20)
>>  #define   PLANE_CTL_ORDER_RGBX			(1 << 20)
>> +#define   PLANE_CTL_YUV420_Y_PLANE		(1 << 19)
>>  #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18)
>>  #define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
>>  #define   PLANE_CTL_YUV422_YUYV			(0 << 16)
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> index c4e05b0b60bf..708d2dfd59d7 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -339,23 +339,23 @@ skl_program_scaler(struct drm_i915_private *dev_priv,
>>  		      ((crtc_w + 1) << 16)|(crtc_h + 1));
>>  }
>>  
>> -void
>> -skl_update_plane(struct intel_plane *plane,
>> -		 const struct intel_crtc_state *crtc_state,
>> -		 const struct intel_plane_state *plane_state)
>> +static void
>> +skl_program_plane(struct intel_plane *plane,
>> +		  const struct intel_crtc_state *crtc_state,
>> +		  const struct intel_plane_state *plane_state,
>> +		  int color_plane, bool slave, u32 plane_ctl)
>>  {
>>  	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>>  	enum plane_id plane_id = plane->id;
>>  	enum pipe pipe = plane->pipe;
>> -	u32 plane_ctl = plane_state->ctl;
>>  	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
>> -	u32 surf_addr = plane_state->color_plane[0].offset;
>> -	u32 stride = skl_plane_stride(plane_state, 0);
>> +	u32 surf_addr = plane_state->color_plane[color_plane].offset;
>> +	u32 stride = skl_plane_stride(plane_state, color_plane);
>>  	u32 aux_stride = skl_plane_stride(plane_state, 1);
>>  	int crtc_x = plane_state->base.dst.x1;
>>  	int crtc_y = plane_state->base.dst.y1;
>> -	uint32_t x = plane_state->color_plane[0].x;
>> -	uint32_t y = plane_state->color_plane[0].y;
>> +	uint32_t x = plane_state->color_plane[color_plane].x;
>> +	uint32_t y = plane_state->color_plane[color_plane].y;
>>  	uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
>>  	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
>>  	struct intel_plane *linked = plane_state->linked_plane;
>> @@ -409,7 +409,9 @@ skl_update_plane(struct intel_plane *plane,
>>  
>>  	/* program plane scaler */
>>  	if (plane_state->scaler_id >= 0) {
>> -		skl_program_scaler(dev_priv, plane, crtc_state, plane_state);
>> +		if (!slave)
>> +			skl_program_scaler(dev_priv, plane,
>> +					   crtc_state, plane_state);
>>  
>>  		I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
>>  	} else {
>> @@ -424,6 +426,25 @@ skl_update_plane(struct intel_plane *plane,
>>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>>  }
>>  
>> +void
>> +skl_update_plane(struct intel_plane *plane,
>> +		 const struct intel_crtc_state *crtc_state,
>> +		 const struct intel_plane_state *plane_state)
>> +{
>> +	skl_program_plane(plane, crtc_state, plane_state,
>> +			  !!plane_state->linked_plane, false,
> The !!linked thing is a bit magicy. I'd probably forget what it means
> every single time. So IMO deserves to be written out in a bit more
> verbose way and/or accompanied by a comment.
I'll just make a variable int color_plane = plane_state->linked_plane ? 1 : 0?
>> +			  plane_state->ctl);
>> +}
>> +
>> +static void
>> +icl_update_slave(struct intel_plane *plane,
>> +		 const struct intel_crtc_state *crtc_state,
>> +		 const struct intel_plane_state *plane_state)
>> +{
>> +	skl_program_plane(plane, crtc_state, plane_state, 0, true,
>> +			  plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE);
> So that one bit is the only difference (apart from the obvious
> PLANE_SURF/STRIDE/OFFSET? No need to deal with the chroma vs. luma 
> size difference etc?
Yes, and all color management is ignored on the Y plane. Still there doesn't seem
to be any harm in programming it, so *shrug*.

Only not so nice thing is I found a CRC mismatch when using chroma upsampling + scaling
vs just using the chroma upsampling. Seems to be a small ~1 or 2 pixel difference in 10 bit.
Need to investigate it a bit more, but with 8 bits you don't notice it. Just an annoying crc mismatch. :)

~Maarten
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  reply	other threads:[~2018-09-22  9:37 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-21 17:39 [PATCH 0/7] drm/i915/gen11: Enable planar format support on gen11 Maarten Lankhorst
2018-09-21 17:39 ` [PATCH 1/7] drm/i915/gen11: Enable 6 sprites " Maarten Lankhorst
2018-09-21 23:24   ` Matt Roper
2018-09-21 17:39 ` [PATCH 2/7] drm/i915/gen11: Link nv12 Y and UV planes in the atomic state, v3 Maarten Lankhorst
2018-09-21 18:35   ` Ville Syrjälä
2018-09-21 19:31     ` Ville Syrjälä
2018-09-24 12:35       ` Maarten Lankhorst
2018-09-24 13:18         ` Ville Syrjälä
2018-09-25 10:03           ` Maarten Lankhorst
2018-09-25 12:44             ` Ville Syrjälä
2018-09-25 18:01           ` Matt Roper
2018-09-25 18:34             ` Ville Syrjälä
2018-09-25 20:18               ` Matt Roper
2018-09-27 13:10                 ` Ville Syrjälä
2018-09-21 23:25   ` Matt Roper
2018-09-21 17:39 ` [PATCH 3/7] drm/i915/gen11: Handle watermarks correctly for separate Y/UV planes Maarten Lankhorst
2018-09-26 22:02   ` Matt Roper
2018-09-21 17:39 ` [PATCH 4/7] drm/i915/gen11: Program the scalers correctly for planar formats Maarten Lankhorst
2018-09-21 18:45   ` Ville Syrjälä
2018-09-24  8:39     ` Maarten Lankhorst
2018-09-24 13:10       ` Ville Syrjälä
2018-09-27  0:16   ` Matt Roper
2018-09-27 13:08     ` Ville Syrjälä
2018-09-21 17:39 ` [PATCH 5/7] drm/i915/gen11: Program the chroma upsampler for HDR planes Maarten Lankhorst
2018-09-21 18:53   ` Ville Syrjälä
2018-09-24  8:38     ` Maarten Lankhorst
2018-09-24 13:09       ` Ville Syrjälä
2018-09-21 17:39 ` [PATCH 6/7] drm/i915/gen11: Program the Y and UV plane for planar mode correctly Maarten Lankhorst
2018-09-21 19:01   ` Ville Syrjälä
2018-09-22  9:37     ` Maarten Lankhorst [this message]
2018-09-21 17:39 ` [PATCH 7/7] drm/i915/gen11: Expose planar format support on gen11 Maarten Lankhorst
2018-09-21 18:17 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gen11: Enable " Patchwork
2018-09-21 18:40 ` ✓ Fi.CI.BAT: success " Patchwork
2018-09-21 20:29 ` ✓ Fi.CI.IGT: " Patchwork

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