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From: Paul Walmsley <pjw@kernel.org>
To: Xixin Liu <liuxixin@kylinos.cn>
Cc: linux-riscv@lists.infradead.org, atish.patra@linux.dev,
	 anup@brainfault.org, will@kernel.org, mark.rutland@arm.com,
	pjw@kernel.org,  palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr,  linux-arm-kernel@lists.infradead.org,
	linux-perf-users@vger.kernel.org,  linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 2/2] perf: RISC-V: store available counter mask as bitmap
Date: Fri, 7 Aug 2026 18:32:33 -0600 (MDT)	[thread overview]
Message-ID: <93cab992-f808-8f3e-03a6-19d84baf38f3@kernel.org> (raw)
In-Reply-To: <prpmask02cmap.1786092600.git.liuxixin@kylinos.cn>

Hi,

On Fri, 7 Aug 2026, Xixin Liu wrote:

> The available-counter mask was a single unsigned long, but iteration
> uses RISCV_MAX_COUNTERS (64). On RV32 that reads past the object. Filling
> with BIT(i) is also wrong for i >= 32.
> 
> Use DECLARE_BITMAP, set_bit/bitmap helpers, and stop counters one word
> at a time.
> 
> Signed-off-by: Xixin Liu <liuxixin@kylinos.cn>

This patch contains several array indexes to element 0 of the cmask 
bitmap, but that element is going to be XLEN bits wide.   Does that 
actually work on RV32 systems?


- Paul


WARNING: multiple messages have this Message-ID (diff)
From: Paul Walmsley <pjw@kernel.org>
To: Xixin Liu <liuxixin@kylinos.cn>
Cc: linux-riscv@lists.infradead.org, atish.patra@linux.dev,
	 anup@brainfault.org, will@kernel.org, mark.rutland@arm.com,
	pjw@kernel.org,  palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr,  linux-arm-kernel@lists.infradead.org,
	linux-perf-users@vger.kernel.org,  linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 2/2] perf: RISC-V: store available counter mask as bitmap
Date: Fri, 7 Aug 2026 18:32:33 -0600 (MDT)	[thread overview]
Message-ID: <93cab992-f808-8f3e-03a6-19d84baf38f3@kernel.org> (raw)
In-Reply-To: <prpmask02cmap.1786092600.git.liuxixin@kylinos.cn>

Hi,

On Fri, 7 Aug 2026, Xixin Liu wrote:

> The available-counter mask was a single unsigned long, but iteration
> uses RISCV_MAX_COUNTERS (64). On RV32 that reads past the object. Filling
> with BIT(i) is also wrong for i >= 32.
> 
> Use DECLARE_BITMAP, set_bit/bitmap helpers, and stop counters one word
> at a time.
> 
> Signed-off-by: Xixin Liu <liuxixin@kylinos.cn>

This patch contains several array indexes to element 0 of the cmask 
bitmap, but that element is going to be XLEN bits wide.   Does that 
actually work on RV32 systems?


- Paul

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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2026-08-08  0:32 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-07  8:50 [PATCH v1 0/2] perf: RISC-V: fix SBI PMU masks for RV32 Xixin Liu
2026-08-07  8:50 ` Xixin Liu
2026-08-07  8:50 ` [PATCH v1 1/2] perf: RISC-V: use BIT_ULL for u64 overflow masks Xixin Liu
2026-08-07  8:50   ` Xixin Liu
2026-08-07  9:17   ` sashiko-bot
2026-08-08  0:46   ` Paul Walmsley
2026-08-08  0:46     ` Paul Walmsley
2026-08-07  8:50 ` [PATCH v1 2/2] perf: RISC-V: store available counter mask as bitmap Xixin Liu
2026-08-07  8:50   ` Xixin Liu
2026-08-07  9:11   ` sashiko-bot
2026-08-08  0:32   ` Paul Walmsley [this message]
2026-08-08  0:32     ` Paul Walmsley

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