From: Florian Fainelli <f.fainelli@gmail.com>
To: arinc.unal@arinc9.com, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Cc: mithat.guner@xeront.com, erkin.bozoglu@xeront.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH 1/2] arm64: dts: mediatek: mt7622: set PHY address of MT7531 switch to 0x1f
Date: Fri, 15 Mar 2024 10:26:41 -0700 [thread overview]
Message-ID: <94e3d09a-e6a4-4808-bc29-3f494b65e170@gmail.com> (raw)
In-Reply-To: <20240314-for-mediatek-mt7531-phy-address-v1-1-52f58db01acd@arinc9.com>
On 3/14/24 05:20, Arınç ÜNAL via B4 Relay wrote:
> From: Arınç ÜNAL <arinc.unal@arinc9.com>
>
> The MT7531 switch listens on PHY address 0x1f on an MDIO bus. I've got two
> findings that support this. There's no bootstrapping option to change the
> PHY address of the switch. The Linux driver hardcodes 0x1f as the PHY
> address of the switch. So the reg property on the device tree is currently
> ignored by the Linux driver.
>
> Therefore, describe the correct PHY address on boards that have this
> switch.
Can we call it a pseudo PHY to use a similar terminology as what is done
through drivers/net/dsa/{bcm_sf2,b53}*?
This is not a real PHY as in it has no actual transceiver/digital signal
processing logic, this is a piece of logic that snoops for MDIO
transactions at that specific address and lets you access the switch's
internal register as if it was a MDIO device.
LGTM otherwise!
--
Florian
WARNING: multiple messages have this Message-ID (diff)
From: Florian Fainelli <f.fainelli@gmail.com>
To: arinc.unal@arinc9.com, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Cc: mithat.guner@xeront.com, erkin.bozoglu@xeront.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH 1/2] arm64: dts: mediatek: mt7622: set PHY address of MT7531 switch to 0x1f
Date: Fri, 15 Mar 2024 10:26:41 -0700 [thread overview]
Message-ID: <94e3d09a-e6a4-4808-bc29-3f494b65e170@gmail.com> (raw)
In-Reply-To: <20240314-for-mediatek-mt7531-phy-address-v1-1-52f58db01acd@arinc9.com>
On 3/14/24 05:20, Arınç ÜNAL via B4 Relay wrote:
> From: Arınç ÜNAL <arinc.unal@arinc9.com>
>
> The MT7531 switch listens on PHY address 0x1f on an MDIO bus. I've got two
> findings that support this. There's no bootstrapping option to change the
> PHY address of the switch. The Linux driver hardcodes 0x1f as the PHY
> address of the switch. So the reg property on the device tree is currently
> ignored by the Linux driver.
>
> Therefore, describe the correct PHY address on boards that have this
> switch.
Can we call it a pseudo PHY to use a similar terminology as what is done
through drivers/net/dsa/{bcm_sf2,b53}*?
This is not a real PHY as in it has no actual transceiver/digital signal
processing logic, this is a piece of logic that snoops for MDIO
transactions at that specific address and lets you access the switch's
internal register as if it was a MDIO device.
LGTM otherwise!
--
Florian
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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-03-15 17:26 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-14 12:20 [PATCH 0/2] Set PHY address of MT7531 switch to 0x1f on MediaTek arm64 boards Arınç ÜNAL
2024-03-14 12:20 ` Arınç ÜNAL via B4 Relay
2024-03-14 12:20 ` Arınç ÜNAL via B4 Relay
2024-03-14 12:20 ` [PATCH 1/2] arm64: dts: mediatek: mt7622: set PHY address of MT7531 switch to 0x1f Arınç ÜNAL
2024-03-14 12:20 ` Arınç ÜNAL via B4 Relay
2024-03-14 12:20 ` Arınç ÜNAL via B4 Relay
2024-03-15 17:26 ` Florian Fainelli [this message]
2024-03-15 17:26 ` Florian Fainelli
2024-03-16 7:43 ` Arınç ÜNAL
2024-03-18 13:02 ` Florian Fainelli
2024-03-18 13:02 ` Florian Fainelli
2024-03-18 15:26 ` Arınç ÜNAL
2024-03-18 15:38 ` Florian Fainelli
2024-03-18 15:38 ` Florian Fainelli
2024-03-18 15:50 ` Arınç ÜNAL
2024-03-14 12:20 ` [PATCH 2/2] arm64: dts: mediatek: mt7986: " Arınç ÜNAL
2024-03-14 12:20 ` Arınç ÜNAL via B4 Relay
2024-03-14 12:20 ` Arınç ÜNAL via B4 Relay
2024-04-27 1:28 ` Daniel Golle
2024-04-27 1:28 ` Daniel Golle
2024-03-15 15:50 ` [PATCH 0/2] Set PHY address of MT7531 switch to 0x1f on MediaTek arm64 boards Rob Herring
2024-03-15 15:50 ` Rob Herring
2024-03-31 9:28 ` arinc.unal
2024-03-31 9:28 ` arinc.unal
2024-04-08 7:22 ` Arınç ÜNAL
2024-04-08 7:22 ` Arınç ÜNAL
2024-04-23 9:16 ` Arınç ÜNAL
2024-04-23 9:16 ` Arınç ÜNAL
2024-04-26 12:15 ` Arınç ÜNAL
2024-04-26 12:15 ` Arınç ÜNAL
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