Re: [PATCH 04/19] drm/dp: Add DPCD for configuring AS SDP for PR + VRR

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 3/13/2026 5:22 PM, Ville Syrjälä wrote:
> On Wed, Mar 11, 2026 at 05:05:56PM +0530, Ankit Nautiyal wrote:
>> Add additional DPCDs required to be configured to support VRR with Panel
>> Replay. These DPCDs are specifically required for configuring Adaptive Sync
>> SDP and are introduced in DP v2.1.
>>
>> v2:
>>   - Correct the shift for the bits. (Ville)
>>   - Add DP_PR_ prefix for the PR-related fields.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   include/drm/display/drm_dp.h | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
>> index 8d172863eba3..e6752a92d5dc 100644
>> --- a/include/drm/display/drm_dp.h
>> +++ b/include/drm/display/drm_dp.h
>> @@ -775,6 +775,15 @@
>>   # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK  (0xf << 3)
>>   # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE		 (1 << 7)
>>   
>> +#define PANEL_REPLAY_CONFIG3				0x11a /* DP 2.1 */
>> +# define DP_PR_AS_SDP_SETUP_TIME_SHIFT			6
>> +# define DP_PR_AS_SDP_SETUP_TIME_MASK			(3 << DP_PR_AS_SDP_SETUP_TIME_SHIFT)
>> +# define DP_PR_AS_SDP_SETUP_TIME_T1			0
>> +# define DP_PR_AS_SDP_SETUP_TIME_DYNAMIC		1 /* DP 2.1 Table 2-227 */
>> +# define DP_PR_AS_SDP_SETUP_TIME_T2			2
> The usual rule in drm_dp.h seems to be to define the values
> as already shifted.


Hmm.. I think I wanted to represent the 3 setup time config with 0, 1 ,2 
which I am using later in switch case.

But to be consistent with the file, I will define the values as already 
shifted, we can still use them in switch case I suppose.


Regards,

Ankit


>
>> +# define DP_PR_AS_SDP_SETUP_TIME(t)			(((t) << DP_PR_AS_SDP_SETUP_TIME_SHIFT) & \
>> +							 DP_PR_AS_SDP_SETUP_TIME_MASK)
>> +
>>   #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
>>   #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>>   #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
>> -- 
>> 2.45.2