* [PATCH v3 1/5] target/riscv: Add svukte extension capability variable
2024-11-12 9:14 [PATCH v3 0/5] Introduce svukte ISA extension Fea.Wang
@ 2024-11-12 9:14 ` Fea.Wang
2024-11-19 3:22 ` Alistair Francis
2024-11-12 9:14 ` [PATCH v3 2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Fea.Wang
` (3 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Fea.Wang @ 2024-11-12 9:14 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Fea.Wang, Frank Chang,
Jim Shu
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's address-space layout.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 59d6fc445d..d8771ca641 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -84,6 +84,7 @@ struct RISCVCPUConfig {
bool ext_svnapot;
bool ext_svpbmt;
bool ext_svvptc;
+ bool ext_svukte;
bool ext_zdinx;
bool ext_zaamo;
bool ext_zacas;
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 1/5] target/riscv: Add svukte extension capability variable
2024-11-12 9:14 ` [PATCH v3 1/5] target/riscv: Add svukte extension capability variable Fea.Wang
@ 2024-11-19 3:22 ` Alistair Francis
0 siblings, 0 replies; 15+ messages in thread
From: Alistair Francis @ 2024-11-19 3:22 UTC (permalink / raw)
To: Fea.Wang
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Frank Chang, Jim Shu
On Tue, Nov 12, 2024 at 7:13 PM Fea.Wang <fea.wang@sifive.com> wrote:
>
> Refer to the draft of svukte extension from:
> https://github.com/riscv/riscv-isa-manual/pull/1564
>
> Svukte provides a means to make user-mode accesses to supervisor memory
> raise page faults in constant time, mitigating attacks that attempt to
> discover the supervisor software's address-space layout.
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_cfg.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 59d6fc445d..d8771ca641 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -84,6 +84,7 @@ struct RISCVCPUConfig {
> bool ext_svnapot;
> bool ext_svpbmt;
> bool ext_svvptc;
> + bool ext_svukte;
> bool ext_zdinx;
> bool ext_zaamo;
> bool ext_zacas;
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled
2024-11-12 9:14 [PATCH v3 0/5] Introduce svukte ISA extension Fea.Wang
2024-11-12 9:14 ` [PATCH v3 1/5] target/riscv: Add svukte extension capability variable Fea.Wang
@ 2024-11-12 9:14 ` Fea.Wang
2024-11-19 3:23 ` Alistair Francis
2024-11-12 9:14 ` [PATCH v3 3/5] target/riscv: Support hstatus[HUKTE] " Fea.Wang
` (2 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Fea.Wang @ 2024-11-12 9:14 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Fea.Wang, Frank Chang,
Jim Shu
Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be
supported when the svukte extension is enabled.
When senvcfg[UKTE] bit is set, the memory access from U-mode should do
the svukte check only except HLV/HLVX/HSV H-mode instructions which
depend on hstatus[HUKTE].
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 385a2c67c2..4b9f899217 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -785,6 +785,7 @@ typedef enum RISCVException {
#define SENVCFG_CBIE MENVCFG_CBIE
#define SENVCFG_CBCFE MENVCFG_CBCFE
#define SENVCFG_CBZE MENVCFG_CBZE
+#define SENVCFG_UKTE BIT(8)
#define HENVCFG_FIOM MENVCFG_FIOM
#define HENVCFG_LPE MENVCFG_LPE
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9846770820..1936a6f32a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2453,6 +2453,10 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
mask |= SENVCFG_SSE;
}
+ if (env_archcpu(env)->cfg.ext_svukte) {
+ mask |= SENVCFG_UKTE;
+ }
+
env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
return RISCV_EXCP_NONE;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled
2024-11-12 9:14 ` [PATCH v3 2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Fea.Wang
@ 2024-11-19 3:23 ` Alistair Francis
0 siblings, 0 replies; 15+ messages in thread
From: Alistair Francis @ 2024-11-19 3:23 UTC (permalink / raw)
To: Fea.Wang
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Frank Chang, Jim Shu
On Tue, Nov 12, 2024 at 7:13 PM Fea.Wang <fea.wang@sifive.com> wrote:
>
> Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be
> supported when the svukte extension is enabled.
>
> When senvcfg[UKTE] bit is set, the memory access from U-mode should do
> the svukte check only except HLV/HLVX/HSV H-mode instructions which
> depend on hstatus[HUKTE].
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_bits.h | 1 +
> target/riscv/csr.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 385a2c67c2..4b9f899217 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -785,6 +785,7 @@ typedef enum RISCVException {
> #define SENVCFG_CBIE MENVCFG_CBIE
> #define SENVCFG_CBCFE MENVCFG_CBCFE
> #define SENVCFG_CBZE MENVCFG_CBZE
> +#define SENVCFG_UKTE BIT(8)
>
> #define HENVCFG_FIOM MENVCFG_FIOM
> #define HENVCFG_LPE MENVCFG_LPE
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9846770820..1936a6f32a 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2453,6 +2453,10 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
> mask |= SENVCFG_SSE;
> }
>
> + if (env_archcpu(env)->cfg.ext_svukte) {
> + mask |= SENVCFG_UKTE;
> + }
> +
> env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
> return RISCV_EXCP_NONE;
> }
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 3/5] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled
2024-11-12 9:14 [PATCH v3 0/5] Introduce svukte ISA extension Fea.Wang
2024-11-12 9:14 ` [PATCH v3 1/5] target/riscv: Add svukte extension capability variable Fea.Wang
2024-11-12 9:14 ` [PATCH v3 2/5] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Fea.Wang
@ 2024-11-12 9:14 ` Fea.Wang
2024-11-19 3:24 ` Alistair Francis
2024-11-12 9:14 ` [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule Fea.Wang
2024-11-12 9:14 ` [PATCH v3 5/5] target/riscv: Expose svukte ISA extension Fea.Wang
4 siblings, 1 reply; 15+ messages in thread
From: Fea.Wang @ 2024-11-12 9:14 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Fea.Wang, Frank Chang,
Jim Shu
Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written
value will be masked when the svukte extension is not enabled.
When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should
do svukte check.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 4b9f899217..fe4e34c64a 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -604,6 +604,7 @@ typedef enum {
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTW 0x00200000
#define HSTATUS_VTSR 0x00400000
+#define HSTATUS_HUKTE 0x01000000
#define HSTATUS_VSXL 0x300000000
#define HSTATUS32_WPRI 0xFF8FF87E
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1936a6f32a..b6fa8ae53f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3540,6 +3540,9 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno,
static RISCVException write_hstatus(CPURISCVState *env, int csrno,
target_ulong val)
{
+ if (!env_archcpu(env)->cfg.ext_svukte) {
+ val = val & (~HSTATUS_HUKTE);
+ }
env->hstatus = val;
if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
qemu_log_mask(LOG_UNIMP,
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 3/5] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled
2024-11-12 9:14 ` [PATCH v3 3/5] target/riscv: Support hstatus[HUKTE] " Fea.Wang
@ 2024-11-19 3:24 ` Alistair Francis
0 siblings, 0 replies; 15+ messages in thread
From: Alistair Francis @ 2024-11-19 3:24 UTC (permalink / raw)
To: Fea.Wang
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Frank Chang, Jim Shu
On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang <fea.wang@sifive.com> wrote:
>
> Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written
> value will be masked when the svukte extension is not enabled.
>
> When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should
> do svukte check.
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_bits.h | 1 +
> target/riscv/csr.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 4b9f899217..fe4e34c64a 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -604,6 +604,7 @@ typedef enum {
> #define HSTATUS_VTVM 0x00100000
> #define HSTATUS_VTW 0x00200000
> #define HSTATUS_VTSR 0x00400000
> +#define HSTATUS_HUKTE 0x01000000
> #define HSTATUS_VSXL 0x300000000
>
> #define HSTATUS32_WPRI 0xFF8FF87E
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 1936a6f32a..b6fa8ae53f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3540,6 +3540,9 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno,
> static RISCVException write_hstatus(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> + if (!env_archcpu(env)->cfg.ext_svukte) {
> + val = val & (~HSTATUS_HUKTE);
> + }
> env->hstatus = val;
> if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
> qemu_log_mask(LOG_UNIMP,
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule
2024-11-12 9:14 [PATCH v3 0/5] Introduce svukte ISA extension Fea.Wang
` (2 preceding siblings ...)
2024-11-12 9:14 ` [PATCH v3 3/5] target/riscv: Support hstatus[HUKTE] " Fea.Wang
@ 2024-11-12 9:14 ` Fea.Wang
2024-11-12 12:52 ` Daniel Henrique Barboza
2024-11-19 3:33 ` Alistair Francis
2024-11-12 9:14 ` [PATCH v3 5/5] target/riscv: Expose svukte ISA extension Fea.Wang
4 siblings, 2 replies; 15+ messages in thread
From: Fea.Wang @ 2024-11-12 9:14 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Fea.Wang, Frank Chang,
Jim Shu
Follow the Svukte spec, do the memory access address checking
1. Include instruction fetches or explicit memory accesses
2. System run in effective privilege U or VU
3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
instruction is HLV, HLVX, HSV and execute from U mode to VU mode
4. Depend on Sv39 and check virtual addresses bit[SXLEN-1]
5. Raises a page-fault exception corresponding to the original access
type.
Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
---
target/riscv/cpu_helper.c | 61 +++++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0a3ead69ea..5b29344c4f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -857,6 +857,61 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr,
return TRANSLATE_SUCCESS;
}
+/* Returns 'true' if a svukte address check is needed */
+static bool do_svukte_check(CPURISCVState *env, bool first_stage,
+ int mode, bool virt)
+{
+ bool ukte;
+
+ /* Svukte extension depends on Sv39. */
+ if (!(env_archcpu(env)->cfg.ext_svukte ||
+ !first_stage ||
+ VM_1_10_SV39 != get_field(env->satp, SATP64_MODE))) {
+ return false;
+ }
+
+ /*
+ * Check hstatus.HUKTE if the effective mode is switched to VU-mode by
+ * executing HLV/HLVX/HSV in U-mode.
+ * For other cases, check senvcfg.UKTE.
+ */
+ if (env->priv == PRV_U && !env->virt_enabled && virt) {
+ ukte = !!(env->hstatus & HSTATUS_HUKTE);
+ } else {
+ ukte = !!(env->senvcfg & SENVCFG_UKTE);
+ }
+
+ if (!ukte) {
+ return false;
+ }
+
+ /*
+ * Svukte extension is qualified only in U or VU-mode.
+ *
+ * Effective mode can be switched to U or VU-mode by:
+ * - M-mode + mstatus.MPRV=1 + mstatus.MPP=U-mode.
+ * - Execute HLV/HLVX/HSV from HS-mode + hstatus.SPVP=0.
+ * - U-mode.
+ * - VU-mode.
+ * - Execute HLV/HLVX/HSV from U-mode + hstatus.HU=1.
+ */
+ if (mode != PRV_U) {
+ return false;
+ }
+
+ return true;
+}
+
+static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
+{
+ uint32_t sxl = riscv_cpu_sxl(env);
+ sxl = (sxl == 0) ? MXL_RV32 : sxl;
+ uint32_t sxlen = 32 * sxl;
+ uint64_t high_bit = addr & (1UL << (sxlen - 1));
+
+ return !high_bit;
+}
+
/*
* get_physical_address - get the physical address for this virtual address
*
@@ -894,6 +949,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int mode = mmuidx_priv(mmu_idx);
+ bool virt = mmuidx_2stage(mmu_idx);
bool use_background = false;
hwaddr ppn;
int napot_bits = 0;
@@ -901,6 +957,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
bool is_sstack_idx = ((mmu_idx & MMU_IDX_SS_WRITE) == MMU_IDX_SS_WRITE);
bool sstack_page = false;
+ if (do_svukte_check(env, first_stage, mode, virt) &&
+ !check_svukte_addr(env, addr)) {
+ return TRANSLATE_FAIL;
+ }
+
/*
* Check if we should use the background registers for the two
* stage translation. We don't need to check if we actually need
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule
2024-11-12 9:14 ` [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule Fea.Wang
@ 2024-11-12 12:52 ` Daniel Henrique Barboza
2024-11-19 3:33 ` Alistair Francis
1 sibling, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2024-11-12 12:52 UTC (permalink / raw)
To: Fea.Wang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
Frank Chang, Jim Shu
On 11/12/24 6:14 AM, Fea.Wang wrote:
> Follow the Svukte spec, do the memory access address checking
>
> 1. Include instruction fetches or explicit memory accesses
> 2. System run in effective privilege U or VU
> 3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
> instruction is HLV, HLVX, HSV and execute from U mode to VU mode
> 4. Depend on Sv39 and check virtual addresses bit[SXLEN-1]
> 5. Raises a page-fault exception corresponding to the original access
> type.
>
> Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu_helper.c | 61 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 0a3ead69ea..5b29344c4f 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -857,6 +857,61 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr,
> return TRANSLATE_SUCCESS;
> }
>
> +/* Returns 'true' if a svukte address check is needed */
> +static bool do_svukte_check(CPURISCVState *env, bool first_stage,
> + int mode, bool virt)
> +{
> + bool ukte;
> +
> + /* Svukte extension depends on Sv39. */
> + if (!(env_archcpu(env)->cfg.ext_svukte ||
> + !first_stage ||
> + VM_1_10_SV39 != get_field(env->satp, SATP64_MODE))) {
> + return false;
> + }
> +
> + /*
> + * Check hstatus.HUKTE if the effective mode is switched to VU-mode by
> + * executing HLV/HLVX/HSV in U-mode.
> + * For other cases, check senvcfg.UKTE.
> + */
> + if (env->priv == PRV_U && !env->virt_enabled && virt) {
> + ukte = !!(env->hstatus & HSTATUS_HUKTE);
> + } else {
> + ukte = !!(env->senvcfg & SENVCFG_UKTE);
> + }
> +
> + if (!ukte) {
> + return false;
> + }
> +
> + /*
> + * Svukte extension is qualified only in U or VU-mode.
> + *
> + * Effective mode can be switched to U or VU-mode by:
> + * - M-mode + mstatus.MPRV=1 + mstatus.MPP=U-mode.
> + * - Execute HLV/HLVX/HSV from HS-mode + hstatus.SPVP=0.
> + * - U-mode.
> + * - VU-mode.
> + * - Execute HLV/HLVX/HSV from U-mode + hstatus.HU=1.
> + */
> + if (mode != PRV_U) {
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
> +{
> + uint32_t sxl = riscv_cpu_sxl(env);
> + sxl = (sxl == 0) ? MXL_RV32 : sxl;
> + uint32_t sxlen = 32 * sxl;
> + uint64_t high_bit = addr & (1UL << (sxlen - 1));
> +
> + return !high_bit;
> +}
> +
> /*
> * get_physical_address - get the physical address for this virtual address
> *
> @@ -894,6 +949,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> MemTxResult res;
> MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
> int mode = mmuidx_priv(mmu_idx);
> + bool virt = mmuidx_2stage(mmu_idx);
> bool use_background = false;
> hwaddr ppn;
> int napot_bits = 0;
> @@ -901,6 +957,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> bool is_sstack_idx = ((mmu_idx & MMU_IDX_SS_WRITE) == MMU_IDX_SS_WRITE);
> bool sstack_page = false;
>
> + if (do_svukte_check(env, first_stage, mode, virt) &&
> + !check_svukte_addr(env, addr)) {
> + return TRANSLATE_FAIL;
> + }
> +
> /*
> * Check if we should use the background registers for the two
> * stage translation. We don't need to check if we actually need
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule
2024-11-12 9:14 ` [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule Fea.Wang
2024-11-12 12:52 ` Daniel Henrique Barboza
@ 2024-11-19 3:33 ` Alistair Francis
2024-11-20 7:42 ` Fea Wang
1 sibling, 1 reply; 15+ messages in thread
From: Alistair Francis @ 2024-11-19 3:33 UTC (permalink / raw)
To: Fea.Wang
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Frank Chang, Jim Shu
On Tue, Nov 12, 2024 at 7:13 PM Fea.Wang <fea.wang@sifive.com> wrote:
>
> Follow the Svukte spec, do the memory access address checking
>
> 1. Include instruction fetches or explicit memory accesses
> 2. System run in effective privilege U or VU
> 3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
> instruction is HLV, HLVX, HSV and execute from U mode to VU mode
> 4. Depend on Sv39 and check virtual addresses bit[SXLEN-1]
> 5. Raises a page-fault exception corresponding to the original access
> type.
>
> Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> ---
> target/riscv/cpu_helper.c | 61 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 0a3ead69ea..5b29344c4f 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -857,6 +857,61 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr,
> return TRANSLATE_SUCCESS;
> }
>
> +/* Returns 'true' if a svukte address check is needed */
> +static bool do_svukte_check(CPURISCVState *env, bool first_stage,
> + int mode, bool virt)
> +{
> + bool ukte;
> +
> + /* Svukte extension depends on Sv39. */
> + if (!(env_archcpu(env)->cfg.ext_svukte ||
> + !first_stage ||
> + VM_1_10_SV39 != get_field(env->satp, SATP64_MODE))) {
> + return false;
> + }
> +
> + /*
> + * Check hstatus.HUKTE if the effective mode is switched to VU-mode by
> + * executing HLV/HLVX/HSV in U-mode.
> + * For other cases, check senvcfg.UKTE.
> + */
> + if (env->priv == PRV_U && !env->virt_enabled && virt) {
> + ukte = !!(env->hstatus & HSTATUS_HUKTE);
You should just be able to use get_field() here
> + } else {
> + ukte = !!(env->senvcfg & SENVCFG_UKTE);
> + }
> +
> + if (!ukte) {
> + return false;
and it's probably simpler to remove the ukte variable and just return
based on the result of get_field()
> + }
> +
> + /*
> + * Svukte extension is qualified only in U or VU-mode.
> + *
> + * Effective mode can be switched to U or VU-mode by:
> + * - M-mode + mstatus.MPRV=1 + mstatus.MPP=U-mode.
> + * - Execute HLV/HLVX/HSV from HS-mode + hstatus.SPVP=0.
> + * - U-mode.
> + * - VU-mode.
> + * - Execute HLV/HLVX/HSV from U-mode + hstatus.HU=1.
> + */
> + if (mode != PRV_U) {
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
> +{
> + uint32_t sxl = riscv_cpu_sxl(env);
> + sxl = (sxl == 0) ? MXL_RV32 : sxl;
I don't think riscv_cpu_sxl() can return 0, do we actually need this check?
Also this extension isn't defined for RV32
Alistair
> + uint32_t sxlen = 32 * sxl;
> + uint64_t high_bit = addr & (1UL << (sxlen - 1));
> +
> + return !high_bit;
> +}
> +
> /*
> * get_physical_address - get the physical address for this virtual address
> *
> @@ -894,6 +949,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> MemTxResult res;
> MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
> int mode = mmuidx_priv(mmu_idx);
> + bool virt = mmuidx_2stage(mmu_idx);
> bool use_background = false;
> hwaddr ppn;
> int napot_bits = 0;
> @@ -901,6 +957,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> bool is_sstack_idx = ((mmu_idx & MMU_IDX_SS_WRITE) == MMU_IDX_SS_WRITE);
> bool sstack_page = false;
>
> + if (do_svukte_check(env, first_stage, mode, virt) &&
> + !check_svukte_addr(env, addr)) {
> + return TRANSLATE_FAIL;
> + }
> +
> /*
> * Check if we should use the background registers for the two
> * stage translation. We don't need to check if we actually need
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule
2024-11-19 3:33 ` Alistair Francis
@ 2024-11-20 7:42 ` Fea Wang
0 siblings, 0 replies; 15+ messages in thread
From: Fea Wang @ 2024-11-20 7:42 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Frank Chang, Jim Shu
[-- Attachment #1: Type: text/plain, Size: 4692 bytes --]
Thanks for the advice.
I will fix them in the next patch version.
Sincerely,
Fea
On Tue, Nov 19, 2024 at 11:33 AM Alistair Francis <alistair23@gmail.com>
wrote:
> On Tue, Nov 12, 2024 at 7:13 PM Fea.Wang <fea.wang@sifive.com> wrote:
> >
> > Follow the Svukte spec, do the memory access address checking
> >
> > 1. Include instruction fetches or explicit memory accesses
> > 2. System run in effective privilege U or VU
> > 3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
> > instruction is HLV, HLVX, HSV and execute from U mode to VU mode
> > 4. Depend on Sv39 and check virtual addresses bit[SXLEN-1]
> > 5. Raises a page-fault exception corresponding to the original access
> > type.
> >
> > Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> > Reviewed-by: Jim Shu <jim.shu@sifive.com>
> > ---
> > target/riscv/cpu_helper.c | 61 +++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 61 insertions(+)
> >
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index 0a3ead69ea..5b29344c4f 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -857,6 +857,61 @@ static int get_physical_address_pmp(CPURISCVState
> *env, int *prot, hwaddr addr,
> > return TRANSLATE_SUCCESS;
> > }
> >
> > +/* Returns 'true' if a svukte address check is needed */
> > +static bool do_svukte_check(CPURISCVState *env, bool first_stage,
> > + int mode, bool virt)
> > +{
> > + bool ukte;
> > +
> > + /* Svukte extension depends on Sv39. */
> > + if (!(env_archcpu(env)->cfg.ext_svukte ||
> > + !first_stage ||
> > + VM_1_10_SV39 != get_field(env->satp, SATP64_MODE))) {
> > + return false;
> > + }
> > +
> > + /*
> > + * Check hstatus.HUKTE if the effective mode is switched to VU-mode
> by
> > + * executing HLV/HLVX/HSV in U-mode.
> > + * For other cases, check senvcfg.UKTE.
> > + */
> > + if (env->priv == PRV_U && !env->virt_enabled && virt) {
> > + ukte = !!(env->hstatus & HSTATUS_HUKTE);
>
> You should just be able to use get_field() here
>
> > + } else {
> > + ukte = !!(env->senvcfg & SENVCFG_UKTE);
> > + }
> > +
> > + if (!ukte) {
> > + return false;
>
> and it's probably simpler to remove the ukte variable and just return
> based on the result of get_field()
>
> > + }
> > +
> > + /*
> > + * Svukte extension is qualified only in U or VU-mode.
> > + *
> > + * Effective mode can be switched to U or VU-mode by:
> > + * - M-mode + mstatus.MPRV=1 + mstatus.MPP=U-mode.
> > + * - Execute HLV/HLVX/HSV from HS-mode + hstatus.SPVP=0.
> > + * - U-mode.
> > + * - VU-mode.
> > + * - Execute HLV/HLVX/HSV from U-mode + hstatus.HU=1.
> > + */
> > + if (mode != PRV_U) {
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > +static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
> > +{
> > + uint32_t sxl = riscv_cpu_sxl(env);
> > + sxl = (sxl == 0) ? MXL_RV32 : sxl;
>
> I don't think riscv_cpu_sxl() can return 0, do we actually need this check?
>
> Also this extension isn't defined for RV32
>
> Alistair
>
> > + uint32_t sxlen = 32 * sxl;
> > + uint64_t high_bit = addr & (1UL << (sxlen - 1));
> > +
> > + return !high_bit;
> > +}
> > +
> > /*
> > * get_physical_address - get the physical address for this virtual
> address
> > *
> > @@ -894,6 +949,7 @@ static int get_physical_address(CPURISCVState *env,
> hwaddr *physical,
> > MemTxResult res;
> > MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
> > int mode = mmuidx_priv(mmu_idx);
> > + bool virt = mmuidx_2stage(mmu_idx);
> > bool use_background = false;
> > hwaddr ppn;
> > int napot_bits = 0;
> > @@ -901,6 +957,11 @@ static int get_physical_address(CPURISCVState *env,
> hwaddr *physical,
> > bool is_sstack_idx = ((mmu_idx & MMU_IDX_SS_WRITE) ==
> MMU_IDX_SS_WRITE);
> > bool sstack_page = false;
> >
> > + if (do_svukte_check(env, first_stage, mode, virt) &&
> > + !check_svukte_addr(env, addr)) {
> > + return TRANSLATE_FAIL;
> > + }
> > +
> > /*
> > * Check if we should use the background registers for the two
> > * stage translation. We don't need to check if we actually need
> > --
> > 2.34.1
> >
> >
>
[-- Attachment #2: Type: text/html, Size: 6285 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 5/5] target/riscv: Expose svukte ISA extension
2024-11-12 9:14 [PATCH v3 0/5] Introduce svukte ISA extension Fea.Wang
` (3 preceding siblings ...)
2024-11-12 9:14 ` [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule Fea.Wang
@ 2024-11-12 9:14 ` Fea.Wang
2024-11-19 3:25 ` Alistair Francis
2024-11-19 3:33 ` Alistair Francis
4 siblings, 2 replies; 15+ messages in thread
From: Fea.Wang @ 2024-11-12 9:14 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Fea.Wang, Frank Chang,
Jim Shu
Add "svukte" in the ISA string when svukte extension is enabled.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f219f0c3b5..6d3e9d563d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -199,6 +199,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
@@ -1595,6 +1596,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
/* These are experimental so mark with 'x-' */
const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+ MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v3 5/5] target/riscv: Expose svukte ISA extension
2024-11-12 9:14 ` [PATCH v3 5/5] target/riscv: Expose svukte ISA extension Fea.Wang
@ 2024-11-19 3:25 ` Alistair Francis
2024-11-19 3:33 ` Alistair Francis
1 sibling, 0 replies; 15+ messages in thread
From: Alistair Francis @ 2024-11-19 3:25 UTC (permalink / raw)
To: Fea.Wang
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Frank Chang, Jim Shu
On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang <fea.wang@sifive.com> wrote:
>
> Add "svukte" in the ISA string when svukte extension is enabled.
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f219f0c3b5..6d3e9d563d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -199,6 +199,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> + ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
> ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
> @@ -1595,6 +1596,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
>
> /* These are experimental so mark with 'x-' */
> const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> + MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v3 5/5] target/riscv: Expose svukte ISA extension
2024-11-12 9:14 ` [PATCH v3 5/5] target/riscv: Expose svukte ISA extension Fea.Wang
2024-11-19 3:25 ` Alistair Francis
@ 2024-11-19 3:33 ` Alistair Francis
2024-11-20 7:42 ` Fea Wang
1 sibling, 1 reply; 15+ messages in thread
From: Alistair Francis @ 2024-11-19 3:33 UTC (permalink / raw)
To: Fea.Wang
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Frank Chang, Jim Shu
On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang <fea.wang@sifive.com> wrote:
>
> Add "svukte" in the ISA string when svukte extension is enabled.
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> ---
> target/riscv/cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f219f0c3b5..6d3e9d563d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -199,6 +199,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> + ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
> ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
> @@ -1595,6 +1596,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
>
> /* These are experimental so mark with 'x-' */
> const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> + MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
There should be a check to make sure this isn't enabled for RV32
Alistair
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v3 5/5] target/riscv: Expose svukte ISA extension
2024-11-19 3:33 ` Alistair Francis
@ 2024-11-20 7:42 ` Fea Wang
0 siblings, 0 replies; 15+ messages in thread
From: Fea Wang @ 2024-11-20 7:42 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Frank Chang, Jim Shu
[-- Attachment #1: Type: text/plain, Size: 1675 bytes --]
OK, I will add a new commit for checking the extension in RV32.
Thank you.
Sincerely,
Fea
On Tue, Nov 19, 2024 at 11:34 AM Alistair Francis <alistair23@gmail.com>
wrote:
> On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang <fea.wang@sifive.com> wrote:
> >
> > Add "svukte" in the ISA string when svukte extension is enabled.
> >
> > Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> > Reviewed-by: Frank Chang <frank.chang@sifive.com>
> > Reviewed-by: Jim Shu <jim.shu@sifive.com>
> > ---
> > target/riscv/cpu.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index f219f0c3b5..6d3e9d563d 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -199,6 +199,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> > + ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
> > ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
> > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
> > @@ -1595,6 +1596,7 @@ const RISCVCPUMultiExtConfig
> riscv_cpu_vendor_exts[] = {
> >
> > /* These are experimental so mark with 'x-' */
> > const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> > + MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
>
> There should be a check to make sure this isn't enabled for RV32
>
> Alistair
>
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