* [PATCH v8 1/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
2023-01-16 12:29 [PATCH v8 0/3] hw/riscv: clear kernel_entry high bits with 32bit CPUs Daniel Henrique Barboza
@ 2023-01-16 12:29 ` Daniel Henrique Barboza
2023-01-18 22:43 ` Alistair Francis
2023-01-16 12:29 ` [PATCH v8 2/3] hw/riscv/boot.c: make riscv_load_initrd() static Daniel Henrique Barboza
2023-01-16 12:29 ` [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() Daniel Henrique Barboza
2 siblings, 1 reply; 11+ messages in thread
From: Daniel Henrique Barboza @ 2023-01-16 12:29 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza,
Palmer Dabbelt, Bin Meng
The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
the same steps when '-kernel' is used:
- execute load_kernel()
- load init_rd()
- write kernel_cmdline
Let's fold everything inside riscv_load_kernel() to avoid code
repetition. To not change the behavior of boards that aren't calling
riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and
allow these boards to opt out from initrd loading.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
hw/riscv/boot.c | 22 +++++++++++++++++++---
hw/riscv/microchip_pfsoc.c | 12 ++----------
hw/riscv/opentitan.c | 2 +-
hw/riscv/sifive_e.c | 3 ++-
hw/riscv/sifive_u.c | 12 ++----------
hw/riscv/spike.c | 11 +----------
hw/riscv/virt.c | 12 ++----------
include/hw/riscv/boot.h | 1 +
8 files changed, 30 insertions(+), 45 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 2594276223..4888d5c1e0 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
target_ulong riscv_load_kernel(MachineState *machine,
target_ulong kernel_start_addr,
+ bool load_initrd,
symbol_fn_t sym_cb)
{
const char *kernel_filename = machine->kernel_filename;
uint64_t kernel_load_base, kernel_entry;
+ void *fdt = machine->fdt;
g_assert(kernel_filename != NULL);
@@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine,
if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
NULL, &kernel_load_base, NULL, NULL, 0,
EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
- return kernel_load_base;
+ kernel_entry = kernel_load_base;
+ goto out;
}
if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
NULL, NULL, NULL) > 0) {
- return kernel_entry;
+ goto out;
}
if (load_image_targphys_as(kernel_filename, kernel_start_addr,
current_machine->ram_size, NULL) > 0) {
- return kernel_start_addr;
+ kernel_entry = kernel_start_addr;
+ goto out;
}
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
+
+out:
+ if (load_initrd && machine->initrd_filename) {
+ riscv_load_initrd(machine, kernel_entry);
+ }
+
+ if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
+ machine->kernel_cmdline);
+ }
+
+ return kernel_entry;
}
void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 82ae5e7023..c45023a2b1 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -629,16 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
firmware_end_addr);
- kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
-
- if (machine->initrd_filename) {
- riscv_load_initrd(machine, kernel_entry);
- }
-
- if (machine->kernel_cmdline && *machine->kernel_cmdline) {
- qemu_fdt_setprop_string(machine->fdt, "/chosen",
- "bootargs", machine->kernel_cmdline);
- }
+ kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
+ true, NULL);
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 64d5d435b9..f6fd9725a5 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -101,7 +101,7 @@ static void opentitan_board_init(MachineState *machine)
}
if (machine->kernel_filename) {
- riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL);
+ riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL);
}
}
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 3e3f4b0088..6835d1c807 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine)
memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
if (machine->kernel_filename) {
- riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL);
+ riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base,
+ false, NULL);
}
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2fb6ee231f..ccad386920 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -598,16 +598,8 @@ static void sifive_u_machine_init(MachineState *machine)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
firmware_end_addr);
- kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
-
- if (machine->initrd_filename) {
- riscv_load_initrd(machine, kernel_entry);
- }
-
- if (machine->kernel_cmdline && *machine->kernel_cmdline) {
- qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
- machine->kernel_cmdline);
- }
+ kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
+ true, NULL);
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index badc11ec43..91bf194ec1 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -306,16 +306,7 @@ static void spike_board_init(MachineState *machine)
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
- htif_symbol_callback);
-
- if (machine->initrd_filename) {
- riscv_load_initrd(machine, kernel_entry);
- }
-
- if (machine->kernel_cmdline && *machine->kernel_cmdline) {
- qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
- machine->kernel_cmdline);
- }
+ true, htif_symbol_callback);
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index e6d4f06e8d..e374b58f89 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1281,16 +1281,8 @@ static void virt_machine_done(Notifier *notifier, void *data)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
- kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
-
- if (machine->initrd_filename) {
- riscv_load_initrd(machine, kernel_entry);
- }
-
- if (machine->kernel_cmdline && *machine->kernel_cmdline) {
- qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
- machine->kernel_cmdline);
- }
+ kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
+ true, NULL);
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index f94653a09b..c3de897371 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -45,6 +45,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
symbol_fn_t sym_cb);
target_ulong riscv_load_kernel(MachineState *machine,
target_ulong firmware_end_addr,
+ bool load_initrd,
symbol_fn_t sym_cb);
void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
--
2.39.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v8 1/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
2023-01-16 12:29 ` [PATCH v8 1/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Daniel Henrique Barboza
@ 2023-01-18 22:43 ` Alistair Francis
0 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2023-01-18 22:43 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, Palmer Dabbelt,
Bin Meng
On Mon, Jan 16, 2023 at 10:31 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
> the same steps when '-kernel' is used:
>
> - execute load_kernel()
> - load init_rd()
> - write kernel_cmdline
>
> Let's fold everything inside riscv_load_kernel() to avoid code
> repetition. To not change the behavior of boards that aren't calling
> riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and
> allow these boards to opt out from initrd loading.
>
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Reviewed-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> hw/riscv/boot.c | 22 +++++++++++++++++++---
> hw/riscv/microchip_pfsoc.c | 12 ++----------
> hw/riscv/opentitan.c | 2 +-
> hw/riscv/sifive_e.c | 3 ++-
> hw/riscv/sifive_u.c | 12 ++----------
> hw/riscv/spike.c | 11 +----------
> hw/riscv/virt.c | 12 ++----------
> include/hw/riscv/boot.h | 1 +
> 8 files changed, 30 insertions(+), 45 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 2594276223..4888d5c1e0 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
>
> target_ulong riscv_load_kernel(MachineState *machine,
> target_ulong kernel_start_addr,
> + bool load_initrd,
> symbol_fn_t sym_cb)
> {
> const char *kernel_filename = machine->kernel_filename;
> uint64_t kernel_load_base, kernel_entry;
> + void *fdt = machine->fdt;
>
> g_assert(kernel_filename != NULL);
>
> @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine,
> if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
> NULL, &kernel_load_base, NULL, NULL, 0,
> EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
> - return kernel_load_base;
> + kernel_entry = kernel_load_base;
> + goto out;
> }
>
> if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
> NULL, NULL, NULL) > 0) {
> - return kernel_entry;
> + goto out;
> }
>
> if (load_image_targphys_as(kernel_filename, kernel_start_addr,
> current_machine->ram_size, NULL) > 0) {
> - return kernel_start_addr;
> + kernel_entry = kernel_start_addr;
> + goto out;
> }
>
> error_report("could not load kernel '%s'", kernel_filename);
> exit(1);
> +
> +out:
> + if (load_initrd && machine->initrd_filename) {
> + riscv_load_initrd(machine, kernel_entry);
This breaks 32-bit loading as kernel_entry might be sign extended with 1s
Alistair
> + }
> +
> + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
> + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
> + machine->kernel_cmdline);
> + }
> +
> + return kernel_entry;
> }
>
> void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 82ae5e7023..c45023a2b1 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -629,16 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
> kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
> firmware_end_addr);
>
> - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
> -
> - if (machine->initrd_filename) {
> - riscv_load_initrd(machine, kernel_entry);
> - }
> -
> - if (machine->kernel_cmdline && *machine->kernel_cmdline) {
> - qemu_fdt_setprop_string(machine->fdt, "/chosen",
> - "bootargs", machine->kernel_cmdline);
> - }
> + kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
> + true, NULL);
>
> /* Compute the fdt load address in dram */
> fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 64d5d435b9..f6fd9725a5 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -101,7 +101,7 @@ static void opentitan_board_init(MachineState *machine)
> }
>
> if (machine->kernel_filename) {
> - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL);
> + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL);
> }
> }
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 3e3f4b0088..6835d1c807 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine)
> memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
>
> if (machine->kernel_filename) {
> - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL);
> + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base,
> + false, NULL);
> }
> }
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 2fb6ee231f..ccad386920 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -598,16 +598,8 @@ static void sifive_u_machine_init(MachineState *machine)
> kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
> firmware_end_addr);
>
> - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
> -
> - if (machine->initrd_filename) {
> - riscv_load_initrd(machine, kernel_entry);
> - }
> -
> - if (machine->kernel_cmdline && *machine->kernel_cmdline) {
> - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
> - machine->kernel_cmdline);
> - }
> + kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
> + true, NULL);
> } else {
> /*
> * If dynamic firmware is used, it doesn't know where is the next mode
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index badc11ec43..91bf194ec1 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -306,16 +306,7 @@ static void spike_board_init(MachineState *machine)
> firmware_end_addr);
>
> kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
> - htif_symbol_callback);
> -
> - if (machine->initrd_filename) {
> - riscv_load_initrd(machine, kernel_entry);
> - }
> -
> - if (machine->kernel_cmdline && *machine->kernel_cmdline) {
> - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
> - machine->kernel_cmdline);
> - }
> + true, htif_symbol_callback);
> } else {
> /*
> * If dynamic firmware is used, it doesn't know where is the next mode
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index e6d4f06e8d..e374b58f89 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -1281,16 +1281,8 @@ static void virt_machine_done(Notifier *notifier, void *data)
> kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
> firmware_end_addr);
>
> - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
> -
> - if (machine->initrd_filename) {
> - riscv_load_initrd(machine, kernel_entry);
> - }
> -
> - if (machine->kernel_cmdline && *machine->kernel_cmdline) {
> - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
> - machine->kernel_cmdline);
> - }
> + kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
> + true, NULL);
> } else {
> /*
> * If dynamic firmware is used, it doesn't know where is the next mode
> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
> index f94653a09b..c3de897371 100644
> --- a/include/hw/riscv/boot.h
> +++ b/include/hw/riscv/boot.h
> @@ -45,6 +45,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
> symbol_fn_t sym_cb);
> target_ulong riscv_load_kernel(MachineState *machine,
> target_ulong firmware_end_addr,
> + bool load_initrd,
> symbol_fn_t sym_cb);
> void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
> uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
> --
> 2.39.0
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v8 2/3] hw/riscv/boot.c: make riscv_load_initrd() static
2023-01-16 12:29 [PATCH v8 0/3] hw/riscv: clear kernel_entry high bits with 32bit CPUs Daniel Henrique Barboza
2023-01-16 12:29 ` [PATCH v8 1/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Daniel Henrique Barboza
@ 2023-01-16 12:29 ` Daniel Henrique Barboza
2023-01-16 12:29 ` [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() Daniel Henrique Barboza
2 siblings, 0 replies; 11+ messages in thread
From: Daniel Henrique Barboza @ 2023-01-16 12:29 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, Bin Meng
The only remaining caller is riscv_load_kernel_and_initrd() which
belongs to the same file.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/boot.c | 80 ++++++++++++++++++++---------------------
include/hw/riscv/boot.h | 1 -
2 files changed, 40 insertions(+), 41 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 4888d5c1e0..e868fb6ade 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -173,6 +173,46 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
exit(1);
}
+static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
+{
+ const char *filename = machine->initrd_filename;
+ uint64_t mem_size = machine->ram_size;
+ void *fdt = machine->fdt;
+ hwaddr start, end;
+ ssize_t size;
+
+ g_assert(filename != NULL);
+
+ /*
+ * We want to put the initrd far enough into RAM that when the
+ * kernel is uncompressed it will not clobber the initrd. However
+ * on boards without much RAM we must ensure that we still leave
+ * enough room for a decent sized initrd, and on boards with large
+ * amounts of RAM we must avoid the initrd being so far up in RAM
+ * that it is outside lowmem and inaccessible to the kernel.
+ * So for boards with less than 256MB of RAM we put the initrd
+ * halfway into RAM, and for boards with 256MB of RAM or more we put
+ * the initrd at 128MB.
+ */
+ start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
+
+ size = load_ramdisk(filename, start, mem_size - start);
+ if (size == -1) {
+ size = load_image_targphys(filename, start, mem_size - start);
+ if (size == -1) {
+ error_report("could not load ramdisk '%s'", filename);
+ exit(1);
+ }
+ }
+
+ /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
+ if (fdt) {
+ end = start + size;
+ qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+ }
+}
+
target_ulong riscv_load_kernel(MachineState *machine,
target_ulong kernel_start_addr,
bool load_initrd,
@@ -225,46 +265,6 @@ out:
return kernel_entry;
}
-void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
-{
- const char *filename = machine->initrd_filename;
- uint64_t mem_size = machine->ram_size;
- void *fdt = machine->fdt;
- hwaddr start, end;
- ssize_t size;
-
- g_assert(filename != NULL);
-
- /*
- * We want to put the initrd far enough into RAM that when the
- * kernel is uncompressed it will not clobber the initrd. However
- * on boards without much RAM we must ensure that we still leave
- * enough room for a decent sized initrd, and on boards with large
- * amounts of RAM we must avoid the initrd being so far up in RAM
- * that it is outside lowmem and inaccessible to the kernel.
- * So for boards with less than 256MB of RAM we put the initrd
- * halfway into RAM, and for boards with 256MB of RAM or more we put
- * the initrd at 128MB.
- */
- start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
-
- size = load_ramdisk(filename, start, mem_size - start);
- if (size == -1) {
- size = load_image_targphys(filename, start, mem_size - start);
- if (size == -1) {
- error_report("could not load ramdisk '%s'", filename);
- exit(1);
- }
- }
-
- /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
- if (fdt) {
- end = start + size;
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
- }
-}
-
uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
{
uint64_t temp, fdt_addr;
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index c3de897371..cbd131bad7 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -47,7 +47,6 @@ target_ulong riscv_load_kernel(MachineState *machine,
target_ulong firmware_end_addr,
bool load_initrd,
symbol_fn_t sym_cb);
-void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
hwaddr saddr,
--
2.39.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym()
2023-01-16 12:29 [PATCH v8 0/3] hw/riscv: clear kernel_entry high bits with 32bit CPUs Daniel Henrique Barboza
2023-01-16 12:29 ` [PATCH v8 1/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Daniel Henrique Barboza
2023-01-16 12:29 ` [PATCH v8 2/3] hw/riscv/boot.c: make riscv_load_initrd() static Daniel Henrique Barboza
@ 2023-01-16 12:29 ` Daniel Henrique Barboza
2023-01-16 12:37 ` Philippe Mathieu-Daudé
2023-01-19 0:20 ` Bin Meng
2 siblings, 2 replies; 11+ messages in thread
From: Daniel Henrique Barboza @ 2023-01-16 12:29 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, Bin Meng
Recent hw/risc/boot.c changes caused a regression in an use case with
the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel'
stopped working. The reason seems to be that Xvisor is using 64 bit to
encode the 32 bit addresses from the guest, and load_elf_ram_sym() is
sign-extending the result with '1's [1].
Use a translate_fn() callback to be called by load_elf_ram_sym() and
return only the 32 bits address if we're running a 32 bit CPU.
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
hw/riscv/boot.c | 20 +++++++++++++++++++-
hw/riscv/microchip_pfsoc.c | 4 ++--
hw/riscv/opentitan.c | 3 ++-
hw/riscv/sifive_e.c | 3 ++-
hw/riscv/sifive_u.c | 4 ++--
hw/riscv/spike.c | 2 +-
hw/riscv/virt.c | 4 ++--
include/hw/riscv/boot.h | 1 +
target/riscv/cpu_bits.h | 1 +
9 files changed, 32 insertions(+), 10 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index e868fb6ade..0fd39df7f3 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
}
}
+static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
+{
+ RISCVHartArrayState *harts = opaque;
+
+ /*
+ * For 32 bit CPUs, kernel_load_base is sign-extended (i.e.
+ * it can be padded with '1's) if the hypervisor is using
+ * 64 bit addresses with 32 bit guests.
+ */
+ if (riscv_is_32bit(harts)) {
+ return extract64(addr, 0, RV32_KERNEL_ADDR_LEN);
+ }
+
+ return addr;
+}
+
target_ulong riscv_load_kernel(MachineState *machine,
+ RISCVHartArrayState *harts,
target_ulong kernel_start_addr,
bool load_initrd,
symbol_fn_t sym_cb)
@@ -231,7 +248,8 @@ target_ulong riscv_load_kernel(MachineState *machine,
* the (expected) load address load address. This allows kernels to have
* separate SBI and ELF entry points (used by FreeBSD, for example).
*/
- if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
+ if (load_elf_ram_sym(kernel_filename, NULL,
+ translate_kernel_address, NULL,
NULL, &kernel_load_base, NULL, NULL, 0,
EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
kernel_entry = kernel_load_base;
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index c45023a2b1..b7e171b605 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -629,8 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
firmware_end_addr);
- kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
- true, NULL);
+ kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
+ kernel_start_addr, true, NULL);
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index f6fd9725a5..1404a52da0 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machine)
}
if (machine->kernel_filename) {
- riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL);
+ riscv_load_kernel(machine, &s->soc.cpus,
+ memmap[IBEX_DEV_RAM].base, false, NULL);
}
}
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 6835d1c807..04939b60c3 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine)
memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
if (machine->kernel_filename) {
- riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base,
+ riscv_load_kernel(machine, &s->soc.cpus,
+ memmap[SIFIVE_E_DEV_DTIM].base,
false, NULL);
}
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ccad386920..b0b3e6f03a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -598,8 +598,8 @@ static void sifive_u_machine_init(MachineState *machine)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
firmware_end_addr);
- kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
- true, NULL);
+ kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
+ kernel_start_addr, true, NULL);
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 91bf194ec1..3c0ac916c0 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -305,7 +305,7 @@ static void spike_board_init(MachineState *machine)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
- kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
+ kernel_entry = riscv_load_kernel(machine, &s->soc[0], kernel_start_addr,
true, htif_symbol_callback);
} else {
/*
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index e374b58f89..cf64da65bf 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1281,8 +1281,8 @@ static void virt_machine_done(Notifier *notifier, void *data)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
- kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
- true, NULL);
+ kernel_entry = riscv_load_kernel(machine, &s->soc[0],
+ kernel_start_addr, true, NULL);
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index cbd131bad7..bc9faed397 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
hwaddr firmware_load_addr,
symbol_fn_t sym_cb);
target_ulong riscv_load_kernel(MachineState *machine,
+ RISCVHartArrayState *harts,
target_ulong firmware_end_addr,
bool load_initrd,
symbol_fn_t sym_cb);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8b0d7e20ea..8fcaeae342 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -751,6 +751,7 @@ typedef enum RISCVException {
#define MENVCFG_STCE (1ULL << 63)
/* For RV32 */
+#define RV32_KERNEL_ADDR_LEN 32
#define MENVCFGH_PBMTE BIT(30)
#define MENVCFGH_STCE BIT(31)
--
2.39.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym()
2023-01-16 12:29 ` [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() Daniel Henrique Barboza
@ 2023-01-16 12:37 ` Philippe Mathieu-Daudé
2023-01-16 12:45 ` Daniel Henrique Barboza
2023-01-19 0:17 ` Bin Meng
2023-01-19 0:20 ` Bin Meng
1 sibling, 2 replies; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-01-16 12:37 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, Bin Meng
On 16/1/23 13:29, Daniel Henrique Barboza wrote:
> Recent hw/risc/boot.c changes caused a regression in an use case with
> the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel'
> stopped working. The reason seems to be that Xvisor is using 64 bit to
> encode the 32 bit addresses from the guest, and load_elf_ram_sym() is
> sign-extending the result with '1's [1].
>
> Use a translate_fn() callback to be called by load_elf_ram_sym() and
> return only the 32 bits address if we're running a 32 bit CPU.
>
> [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html
>
> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Suggested-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> hw/riscv/boot.c | 20 +++++++++++++++++++-
> hw/riscv/microchip_pfsoc.c | 4 ++--
> hw/riscv/opentitan.c | 3 ++-
> hw/riscv/sifive_e.c | 3 ++-
> hw/riscv/sifive_u.c | 4 ++--
> hw/riscv/spike.c | 2 +-
> hw/riscv/virt.c | 4 ++--
> include/hw/riscv/boot.h | 1 +
> target/riscv/cpu_bits.h | 1 +
> 9 files changed, 32 insertions(+), 10 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index e868fb6ade..0fd39df7f3 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
> }
> }
>
> +static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
> +{
> + RISCVHartArrayState *harts = opaque;
> +
> + /*
> + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e.
> + * it can be padded with '1's) if the hypervisor is using
> + * 64 bit addresses with 32 bit guests.
> + */
> + if (riscv_is_32bit(harts)) {
Maybe move the comment within the if() and add " so remove the sign
extension by truncating to 32-bit".
> + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN);
For 32-bit maybe a definition is not necessary, I asked before
you used 24-bit in the previous version. As the maintainer prefer :)
> + }
> +
> + return addr;
> +}
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 8b0d7e20ea..8fcaeae342 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -751,6 +751,7 @@ typedef enum RISCVException {
> #define MENVCFG_STCE (1ULL << 63)
>
> /* For RV32 */
> +#define RV32_KERNEL_ADDR_LEN 32
> #define MENVCFGH_PBMTE BIT(30)
> #define MENVCFGH_STCE BIT(31)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym()
2023-01-16 12:37 ` Philippe Mathieu-Daudé
@ 2023-01-16 12:45 ` Daniel Henrique Barboza
2023-01-18 22:45 ` Alistair Francis
2023-01-19 0:17 ` Bin Meng
1 sibling, 1 reply; 11+ messages in thread
From: Daniel Henrique Barboza @ 2023-01-16 12:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-riscv, alistair.francis, Bin Meng
On 1/16/23 09:37, Philippe Mathieu-Daudé wrote:
> On 16/1/23 13:29, Daniel Henrique Barboza wrote:
>> Recent hw/risc/boot.c changes caused a regression in an use case with
>> the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel'
>> stopped working. The reason seems to be that Xvisor is using 64 bit to
>> encode the 32 bit addresses from the guest, and load_elf_ram_sym() is
>> sign-extending the result with '1's [1].
>>
>> Use a translate_fn() callback to be called by load_elf_ram_sym() and
>> return only the 32 bits address if we're running a 32 bit CPU.
>>
>> [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html
>>
>> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> Suggested-by: Bin Meng <bmeng.cn@gmail.com>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>> hw/riscv/boot.c | 20 +++++++++++++++++++-
>> hw/riscv/microchip_pfsoc.c | 4 ++--
>> hw/riscv/opentitan.c | 3 ++-
>> hw/riscv/sifive_e.c | 3 ++-
>> hw/riscv/sifive_u.c | 4 ++--
>> hw/riscv/spike.c | 2 +-
>> hw/riscv/virt.c | 4 ++--
>> include/hw/riscv/boot.h | 1 +
>> target/riscv/cpu_bits.h | 1 +
>> 9 files changed, 32 insertions(+), 10 deletions(-)
>>
>> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
>> index e868fb6ade..0fd39df7f3 100644
>> --- a/hw/riscv/boot.c
>> +++ b/hw/riscv/boot.c
>> @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
>> }
>> }
>> +static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
>> +{
>> + RISCVHartArrayState *harts = opaque;
>> +
>> + /*
>> + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e.
>> + * it can be padded with '1's) if the hypervisor is using
>> + * 64 bit addresses with 32 bit guests.
>> + */
>> + if (riscv_is_32bit(harts)) {
>
> Maybe move the comment within the if() and add " so remove the sign
> extension by truncating to 32-bit".
>
>> + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN);
>
> For 32-bit maybe a definition is not necessary, I asked before
> you used 24-bit in the previous version. As the maintainer prefer :)
That was unintentional. I missed a 'f' in that 0x0fffffff, which I noticed only
now when doing this version. It's curious because Alistair mentioned that
the patch apparently solved the bug ....
I don't mind creating a macro for the 32 bit value. If we decide it's unneeded
I can remove it and just put a '32' there. I'll also make the comment change
you mentioned above.
Thanks,
Daniel
>
>> + }
>> +
>> + return addr;
>> +}
>
>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>> index 8b0d7e20ea..8fcaeae342 100644
>> --- a/target/riscv/cpu_bits.h
>> +++ b/target/riscv/cpu_bits.h
>> @@ -751,6 +751,7 @@ typedef enum RISCVException {
>> #define MENVCFG_STCE (1ULL << 63)
>> /* For RV32 */
>> +#define RV32_KERNEL_ADDR_LEN 32
>> #define MENVCFGH_PBMTE BIT(30)
>> #define MENVCFGH_STCE BIT(31)
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym()
2023-01-16 12:45 ` Daniel Henrique Barboza
@ 2023-01-18 22:45 ` Alistair Francis
2023-01-18 23:34 ` Daniel Henrique Barboza
0 siblings, 1 reply; 11+ messages in thread
From: Alistair Francis @ 2023-01-18 22:45 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: Philippe Mathieu-Daudé, qemu-devel, qemu-riscv,
alistair.francis, Bin Meng
On Mon, Jan 16, 2023 at 10:46 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
>
>
> On 1/16/23 09:37, Philippe Mathieu-Daudé wrote:
> > On 16/1/23 13:29, Daniel Henrique Barboza wrote:
> >> Recent hw/risc/boot.c changes caused a regression in an use case with
> >> the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel'
> >> stopped working. The reason seems to be that Xvisor is using 64 bit to
> >> encode the 32 bit addresses from the guest, and load_elf_ram_sym() is
> >> sign-extending the result with '1's [1].
> >>
> >> Use a translate_fn() callback to be called by load_elf_ram_sym() and
> >> return only the 32 bits address if we're running a 32 bit CPU.
> >>
> >> [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html
> >>
> >> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> >> Suggested-by: Bin Meng <bmeng.cn@gmail.com>
> >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> >> ---
> >> hw/riscv/boot.c | 20 +++++++++++++++++++-
> >> hw/riscv/microchip_pfsoc.c | 4 ++--
> >> hw/riscv/opentitan.c | 3 ++-
> >> hw/riscv/sifive_e.c | 3 ++-
> >> hw/riscv/sifive_u.c | 4 ++--
> >> hw/riscv/spike.c | 2 +-
> >> hw/riscv/virt.c | 4 ++--
> >> include/hw/riscv/boot.h | 1 +
> >> target/riscv/cpu_bits.h | 1 +
> >> 9 files changed, 32 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> >> index e868fb6ade..0fd39df7f3 100644
> >> --- a/hw/riscv/boot.c
> >> +++ b/hw/riscv/boot.c
> >> @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
> >> }
> >> }
> >> +static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
> >> +{
> >> + RISCVHartArrayState *harts = opaque;
> >> +
> >> + /*
> >> + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e.
> >> + * it can be padded with '1's) if the hypervisor is using
> >> + * 64 bit addresses with 32 bit guests.
> >> + */
> >> + if (riscv_is_32bit(harts)) {
> >
> > Maybe move the comment within the if() and add " so remove the sign
> > extension by truncating to 32-bit".
> >
> >> + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN);
> >
> > For 32-bit maybe a definition is not necessary, I asked before
> > you used 24-bit in the previous version. As the maintainer prefer :)
>
> That was unintentional. I missed a 'f' in that 0x0fffffff, which I noticed only
> now when doing this version. It's curious because Alistair mentioned that
> the patch apparently solved the bug ....
I never tested it, I'm not sure if this solves the problem or not.
This patch needs to be merged *before* the initrd patch (patch 1 of
this series) to avoid breaking users.
>
> I don't mind creating a macro for the 32 bit value. If we decide it's unneeded
> I can remove it and just put a '32' there. I'll also make the comment change
> you mentioned above.
I think 32 if fine, I don't think we need a macro
Alistair
>
>
> Thanks,
>
>
> Daniel
>
> >
> >> + }
> >> +
> >> + return addr;
> >> +}
> >
> >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> >> index 8b0d7e20ea..8fcaeae342 100644
> >> --- a/target/riscv/cpu_bits.h
> >> +++ b/target/riscv/cpu_bits.h
> >> @@ -751,6 +751,7 @@ typedef enum RISCVException {
> >> #define MENVCFG_STCE (1ULL << 63)
> >> /* For RV32 */
> >> +#define RV32_KERNEL_ADDR_LEN 32
> >> #define MENVCFGH_PBMTE BIT(30)
> >> #define MENVCFGH_STCE BIT(31)
> >
> > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> >
> >
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym()
2023-01-18 22:45 ` Alistair Francis
@ 2023-01-18 23:34 ` Daniel Henrique Barboza
0 siblings, 0 replies; 11+ messages in thread
From: Daniel Henrique Barboza @ 2023-01-18 23:34 UTC (permalink / raw)
To: Alistair Francis
Cc: Philippe Mathieu-Daudé, qemu-devel, qemu-riscv,
alistair.francis, Bin Meng
On 1/18/23 19:45, Alistair Francis wrote:
> On Mon, Jan 16, 2023 at 10:46 PM Daniel Henrique Barboza
> <dbarboza@ventanamicro.com> wrote:
>>
>>
>> On 1/16/23 09:37, Philippe Mathieu-Daudé wrote:
>>> On 16/1/23 13:29, Daniel Henrique Barboza wrote:
>>>> Recent hw/risc/boot.c changes caused a regression in an use case with
>>>> the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel'
>>>> stopped working. The reason seems to be that Xvisor is using 64 bit to
>>>> encode the 32 bit addresses from the guest, and load_elf_ram_sym() is
>>>> sign-extending the result with '1's [1].
>>>>
>>>> Use a translate_fn() callback to be called by load_elf_ram_sym() and
>>>> return only the 32 bits address if we're running a 32 bit CPU.
>>>>
>>>> [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html
>>>>
>>>> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>>> Suggested-by: Bin Meng <bmeng.cn@gmail.com>
>>>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>>>> ---
>>>> hw/riscv/boot.c | 20 +++++++++++++++++++-
>>>> hw/riscv/microchip_pfsoc.c | 4 ++--
>>>> hw/riscv/opentitan.c | 3 ++-
>>>> hw/riscv/sifive_e.c | 3 ++-
>>>> hw/riscv/sifive_u.c | 4 ++--
>>>> hw/riscv/spike.c | 2 +-
>>>> hw/riscv/virt.c | 4 ++--
>>>> include/hw/riscv/boot.h | 1 +
>>>> target/riscv/cpu_bits.h | 1 +
>>>> 9 files changed, 32 insertions(+), 10 deletions(-)
>>>>
>>>> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
>>>> index e868fb6ade..0fd39df7f3 100644
>>>> --- a/hw/riscv/boot.c
>>>> +++ b/hw/riscv/boot.c
>>>> @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
>>>> }
>>>> }
>>>> +static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
>>>> +{
>>>> + RISCVHartArrayState *harts = opaque;
>>>> +
>>>> + /*
>>>> + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e.
>>>> + * it can be padded with '1's) if the hypervisor is using
>>>> + * 64 bit addresses with 32 bit guests.
>>>> + */
>>>> + if (riscv_is_32bit(harts)) {
>>> Maybe move the comment within the if() and add " so remove the sign
>>> extension by truncating to 32-bit".
>>>
>>>> + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN);
>>> For 32-bit maybe a definition is not necessary, I asked before
>>> you used 24-bit in the previous version. As the maintainer prefer :)
>> That was unintentional. I missed a 'f' in that 0x0fffffff, which I noticed only
>> now when doing this version. It's curious because Alistair mentioned that
>> the patch apparently solved the bug ....
> I never tested it, I'm not sure if this solves the problem or not.
>
> This patch needs to be merged *before* the initrd patch (patch 1 of
> this series) to avoid breaking users.
Makes sense. I'll change it in v9.
Daniel
>> I don't mind creating a macro for the 32 bit value. If we decide it's unneeded
>> I can remove it and just put a '32' there. I'll also make the comment change
>> you mentioned above.
> I think 32 if fine, I don't think we need a macro
>
> Alistair
>
>>
>> Thanks,
>>
>>
>> Daniel
>>
>>>> + }
>>>> +
>>>> + return addr;
>>>> +}
>>>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>>>> index 8b0d7e20ea..8fcaeae342 100644
>>>> --- a/target/riscv/cpu_bits.h
>>>> +++ b/target/riscv/cpu_bits.h
>>>> @@ -751,6 +751,7 @@ typedef enum RISCVException {
>>>> #define MENVCFG_STCE (1ULL << 63)
>>>> /* For RV32 */
>>>> +#define RV32_KERNEL_ADDR_LEN 32
>>>> #define MENVCFGH_PBMTE BIT(30)
>>>> #define MENVCFGH_STCE BIT(31)
>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>>
>>>
>>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym()
2023-01-16 12:37 ` Philippe Mathieu-Daudé
2023-01-16 12:45 ` Daniel Henrique Barboza
@ 2023-01-19 0:17 ` Bin Meng
1 sibling, 0 replies; 11+ messages in thread
From: Bin Meng @ 2023-01-19 0:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Daniel Henrique Barboza, qemu-devel, qemu-riscv, alistair.francis
On Mon, Jan 16, 2023 at 8:37 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> On 16/1/23 13:29, Daniel Henrique Barboza wrote:
> > Recent hw/risc/boot.c changes caused a regression in an use case with
> > the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel'
> > stopped working. The reason seems to be that Xvisor is using 64 bit to
> > encode the 32 bit addresses from the guest, and load_elf_ram_sym() is
> > sign-extending the result with '1's [1].
> >
> > Use a translate_fn() callback to be called by load_elf_ram_sym() and
> > return only the 32 bits address if we're running a 32 bit CPU.
> >
> > [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html
> >
> > Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> > Suggested-by: Bin Meng <bmeng.cn@gmail.com>
> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> > ---
> > hw/riscv/boot.c | 20 +++++++++++++++++++-
> > hw/riscv/microchip_pfsoc.c | 4 ++--
> > hw/riscv/opentitan.c | 3 ++-
> > hw/riscv/sifive_e.c | 3 ++-
> > hw/riscv/sifive_u.c | 4 ++--
> > hw/riscv/spike.c | 2 +-
> > hw/riscv/virt.c | 4 ++--
> > include/hw/riscv/boot.h | 1 +
> > target/riscv/cpu_bits.h | 1 +
> > 9 files changed, 32 insertions(+), 10 deletions(-)
> >
> > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> > index e868fb6ade..0fd39df7f3 100644
> > --- a/hw/riscv/boot.c
> > +++ b/hw/riscv/boot.c
> > @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
> > }
> > }
> >
> > +static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
> > +{
> > + RISCVHartArrayState *harts = opaque;
> > +
> > + /*
> > + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e.
> > + * it can be padded with '1's) if the hypervisor is using
> > + * 64 bit addresses with 32 bit guests.
> > + */
> > + if (riscv_is_32bit(harts)) {
>
> Maybe move the comment within the if() and add " so remove the sign
> extension by truncating to 32-bit".
>
> > + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN);
>
> For 32-bit maybe a definition is not necessary, I asked before
> you used 24-bit in the previous version. As the maintainer prefer :)
>
> > + }
> > +
> > + return addr;
> > +}
>
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 8b0d7e20ea..8fcaeae342 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -751,6 +751,7 @@ typedef enum RISCVException {
> > #define MENVCFG_STCE (1ULL << 63)
> >
> > /* For RV32 */
> > +#define RV32_KERNEL_ADDR_LEN 32
> > #define MENVCFGH_PBMTE BIT(30)
> > #define MENVCFGH_STCE BIT(31)
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>
Isn't the problem in the ELF loader?
Why does it return a 64-bit signed extended address given the 32-bit ELF image?
Regards,
Bin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym()
2023-01-16 12:29 ` [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() Daniel Henrique Barboza
2023-01-16 12:37 ` Philippe Mathieu-Daudé
@ 2023-01-19 0:20 ` Bin Meng
1 sibling, 0 replies; 11+ messages in thread
From: Bin Meng @ 2023-01-19 0:20 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis,
Philippe Mathieu-Daudé
On Mon, Jan 16, 2023 at 8:30 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Recent hw/risc/boot.c changes caused a regression in an use case with
> the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel'
> stopped working. The reason seems to be that Xvisor is using 64 bit to
> encode the 32 bit addresses from the guest, and load_elf_ram_sym() is
> sign-extending the result with '1's [1].
>
> Use a translate_fn() callback to be called by load_elf_ram_sym() and
> return only the 32 bits address if we're running a 32 bit CPU.
>
> [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html
>
> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Suggested-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> hw/riscv/boot.c | 20 +++++++++++++++++++-
> hw/riscv/microchip_pfsoc.c | 4 ++--
> hw/riscv/opentitan.c | 3 ++-
> hw/riscv/sifive_e.c | 3 ++-
> hw/riscv/sifive_u.c | 4 ++--
> hw/riscv/spike.c | 2 +-
> hw/riscv/virt.c | 4 ++--
> include/hw/riscv/boot.h | 1 +
> target/riscv/cpu_bits.h | 1 +
> 9 files changed, 32 insertions(+), 10 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index e868fb6ade..0fd39df7f3 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
> }
> }
>
> +static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
> +{
> + RISCVHartArrayState *harts = opaque;
> +
> + /*
> + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e.
> + * it can be padded with '1's) if the hypervisor is using
> + * 64 bit addresses with 32 bit guests.
This comment is not accurate. It has nothing to do with the hypervisor
using a 64-bit address. It's the ELF loader that is sign-extending the
32-bit address.
> + */
> + if (riscv_is_32bit(harts)) {
> + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN);
> + }
> +
> + return addr;
> +}
> +
> target_ulong riscv_load_kernel(MachineState *machine,
> + RISCVHartArrayState *harts,
> target_ulong kernel_start_addr,
> bool load_initrd,
> symbol_fn_t sym_cb)
> @@ -231,7 +248,8 @@ target_ulong riscv_load_kernel(MachineState *machine,
> * the (expected) load address load address. This allows kernels to have
> * separate SBI and ELF entry points (used by FreeBSD, for example).
> */
> - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
> + if (load_elf_ram_sym(kernel_filename, NULL,
> + translate_kernel_address, NULL,
> NULL, &kernel_load_base, NULL, NULL, 0,
> EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
> kernel_entry = kernel_load_base;
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index c45023a2b1..b7e171b605 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -629,8 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
> kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
> firmware_end_addr);
>
> - kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
> - true, NULL);
> + kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
> + kernel_start_addr, true, NULL);
>
> /* Compute the fdt load address in dram */
> fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index f6fd9725a5..1404a52da0 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machine)
> }
>
> if (machine->kernel_filename) {
> - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL);
> + riscv_load_kernel(machine, &s->soc.cpus,
> + memmap[IBEX_DEV_RAM].base, false, NULL);
> }
> }
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 6835d1c807..04939b60c3 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine)
> memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
>
> if (machine->kernel_filename) {
> - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base,
> + riscv_load_kernel(machine, &s->soc.cpus,
> + memmap[SIFIVE_E_DEV_DTIM].base,
> false, NULL);
> }
> }
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index ccad386920..b0b3e6f03a 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -598,8 +598,8 @@ static void sifive_u_machine_init(MachineState *machine)
> kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
> firmware_end_addr);
>
> - kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
> - true, NULL);
> + kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
> + kernel_start_addr, true, NULL);
> } else {
> /*
> * If dynamic firmware is used, it doesn't know where is the next mode
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 91bf194ec1..3c0ac916c0 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -305,7 +305,7 @@ static void spike_board_init(MachineState *machine)
> kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
> firmware_end_addr);
>
> - kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
> + kernel_entry = riscv_load_kernel(machine, &s->soc[0], kernel_start_addr,
> true, htif_symbol_callback);
> } else {
> /*
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index e374b58f89..cf64da65bf 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -1281,8 +1281,8 @@ static void virt_machine_done(Notifier *notifier, void *data)
> kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
> firmware_end_addr);
>
> - kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
> - true, NULL);
> + kernel_entry = riscv_load_kernel(machine, &s->soc[0],
> + kernel_start_addr, true, NULL);
> } else {
> /*
> * If dynamic firmware is used, it doesn't know where is the next mode
> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
> index cbd131bad7..bc9faed397 100644
> --- a/include/hw/riscv/boot.h
> +++ b/include/hw/riscv/boot.h
> @@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
> hwaddr firmware_load_addr,
> symbol_fn_t sym_cb);
> target_ulong riscv_load_kernel(MachineState *machine,
> + RISCVHartArrayState *harts,
> target_ulong firmware_end_addr,
> bool load_initrd,
> symbol_fn_t sym_cb);
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 8b0d7e20ea..8fcaeae342 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -751,6 +751,7 @@ typedef enum RISCVException {
> #define MENVCFG_STCE (1ULL << 63)
>
> /* For RV32 */
> +#define RV32_KERNEL_ADDR_LEN 32
> #define MENVCFGH_PBMTE BIT(30)
> #define MENVCFGH_STCE BIT(31)
>
> --
Regards,
Bin
^ permalink raw reply [flat|nested] 11+ messages in thread