RE: [PATCH] ASoC: rt712-sdca: reconfigure PLL2 to fix calibration time-out

[Jack Yu <jack.yu@realtek.com>]

> -----Original Message-----
> From: Mark Brown <broonie@kernel.org>
> Sent: Tuesday, September 8, 2026 5:32 AM
> To: Jack Yu <jack.yu@realtek.com>
> Cc: lgirdwood@gmail.com; alsa-devel@alsa-project.org; lars@metafoo.de;
> Flove(HsinFu) <flove@realtek.com>; Oder Chiou <oder_chiou@realtek.com>;
> Shuming [范書銘] <shumingf@realtek.com>; Derek [方德義]
> <derek.fang@realtek.com>; Trevor.Wu@mediatek.com
> Subject: Re: [PATCH] ASoC: rt712-sdca: reconfigure PLL2 to fix calibration
> time-out
> 
> On Mon, Sep 07, 2026 at 02:41:14PM +0800, jack.yu@realtek.com wrote:
> > From: Jack Yu <jack.yu@realtek.com>
> >
> > Add pll2 reconfiguration sequence in order to fix calibration time-out
> > issue and to support 24.576MHz MCLK on specific platforms.
> 
> > +static void rt712_sdca_clk_patch2(struct rt712_sdca_priv *rt712) {
> 
> 
> > +	regmap_write(rt712->regmap, RT712_SDW_SCALE_CLK0, 0x03);
> > +	regmap_write(rt712->regmap, RT712_SDW_SCALE_CLK1, 0x03);
> 
> This looks like it collides with sdw_slave_set_frequency()?

After testing, these two registers can be removed from the patch and the patch can still fix issue.
I'll update this in V2 patch.
> 
> > +	if (loop_dc == chk_cnt) {
> > +		if (clk_base == RT712_CLK_FREQ_24_576MHZ) {
> > +			rt712_sdca_clk_patch(rt712);
> > +			rt712_sdca_clk_patch2(rt712);
> > +		}
> 
> Perhaps the patching should be checking that the scaling registers are the ones
> written above and only kicking in if that's the case, or have more cases that
> work with other scaling setups?  Or restore whatever the core set if that's
> possible?
I'll remove those two registers mentioned above and update a V2 patch.