Re: [PATCH] ASoC: rt712-sdca: reconfigure PLL2 to fix calibration time-out

[Mark Brown <broonie@kernel.org>]

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On Mon, Sep 07, 2026 at 02:41:14PM +0800, jack.yu@realtek.com wrote:
> From: Jack Yu <jack.yu@realtek.com>
> 
> Add pll2 reconfiguration sequence in order to fix calibration
> time-out issue and to support 24.576MHz MCLK on specific platforms.

> +static void rt712_sdca_clk_patch2(struct rt712_sdca_priv *rt712)
> +{


> +	regmap_write(rt712->regmap, RT712_SDW_SCALE_CLK0, 0x03);
> +	regmap_write(rt712->regmap, RT712_SDW_SCALE_CLK1, 0x03);

This looks like it collides with sdw_slave_set_frequency()?

> +	if (loop_dc == chk_cnt) {
> +		if (clk_base == RT712_CLK_FREQ_24_576MHZ) {
> +			rt712_sdca_clk_patch(rt712);
> +			rt712_sdca_clk_patch2(rt712);
> +		}

Perhaps the patching should be checking that the scaling registers are
the ones written above and only kicking in if that's the case, or have
more cases that work with other scaling setups?  Or restore whatever the
core set if that's possible?

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