From: Yi Liu <yi.l.liu@intel.com>
To: "Duan, Zhenzhong" <zhenzhong.duan@intel.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"clg@redhat.com" <clg@redhat.com>,
"eric.auger@redhat.com" <eric.auger@redhat.com>,
"mst@redhat.com" <mst@redhat.com>,
"jasowang@redhat.com" <jasowang@redhat.com>,
"peterx@redhat.com" <peterx@redhat.com>,
"ddutile@redhat.com" <ddutile@redhat.com>,
"jgg@nvidia.com" <jgg@nvidia.com>,
"nicolinc@nvidia.com" <nicolinc@nvidia.com>,
"shameerali.kolothum.thodi@huawei.com"
<shameerali.kolothum.thodi@huawei.com>,
"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
"clement.mathieu--drif@eviden.com"
<clement.mathieu--drif@eviden.com>,
"Tian, Kevin" <kevin.tian@intel.com>,
"Peng, Chao P" <chao.p.peng@intel.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>
Subject: Re: [PATCH v1 02/15] intel_iommu: Optimize context entry cache utilization
Date: Tue, 17 Jun 2025 18:57:48 +0800 [thread overview]
Message-ID: <9add1df3-1a2d-41bb-ba6b-ef625e05d7e9@intel.com> (raw)
In-Reply-To: <IA3PR11MB913640374E35567AA052B6DD9275A@IA3PR11MB9136.namprd11.prod.outlook.com>
On 2025/6/11 18:06, Duan, Zhenzhong wrote:
>
>
>> -----Original Message-----
>> From: Liu, Yi L <yi.l.liu@intel.com>
>> Subject: Re: [PATCH v1 02/15] intel_iommu: Optimize context entry cache
>> utilization
>>
>> On 2025/6/6 18:04, Zhenzhong Duan wrote:
>>> There are many call sites referencing context entry by calling
>>> vtd_dev_to_context_entry() which will traverse the DMAR table.
>>>
>>> In most cases we can use cached context entry in vtd_as->context_cache_entry
>>> except when its entry is stale. Currently only global and domain context
>>> invalidation stale it.
>>>
>>> So introduce a helper function vtd_as_to_context_entry() to fetch from cache
>>> before trying with vtd_dev_to_context_entry().
>>
>> The cached context entry is now protected by vtd_iommu_lock(). While not
>> all caller of vtd_dev_to_context_entry() are under this lock.
>>
>> Also, the cached context entry is created in the translate path. IMHO,
>> this path is not supposed to be triggered for passthrough devices.
>> While this may need double check and may change in the future. But let's
>> see if any locking issue with the current code.
>
> Good finding, yes.
> Previously I thought translation path updates cc_entry->context_entry after cc_entry->context_cache_gen.
> In vtd_as_to_context_entry() cc_entry->context_cache_gen is checked first, so there was no real race.
> But I still missed a memory barrier like below:
yeah, testing context_cache_gen is necessary. But without lock, this
cannot guarantee the cc_entry is valid after the test.
> @@ -2277,6 +2286,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
> cc_entry->context_cache_gen,
> s->context_cache_gen);
> cc_entry->context_entry = ce;
> + smp_wmb();
> cc_entry->context_cache_gen = s->context_cache_gen;
> }
>
> Another option I can think of is adding lock to cache reading like below:
this is in-enough as well since the cc_entry->context_entry can be modified
after lock is released.
> @@ -1659,11 +1659,15 @@ static int vtd_as_to_context_entry(VTDAddressSpace *vtd_as, VTDContextEntry *ce)
> uint8_t devfn = vtd_as->devfn;
> VTDContextCacheEntry *cc_entry = &vtd_as->context_cache_entry;
>
> + vtd_iommu_lock(s);
> +
> /* Try to fetch context-entry from cache first */
> if (cc_entry->context_cache_gen == s->context_cache_gen) {
> *ce = cc_entry->context_entry;
> + vtd_iommu_unlock(s);
> return 0;
> } else {
> + vtd_iommu_unlock(s);
> return vtd_dev_to_context_entry(s, bus_num, devfn, ce);
> }
> }
>
> Which one do you prefer?
If it's just optimization, perhaps just drop it. :)
--
Regards,
Yi Liu
next prev parent reply other threads:[~2025-06-17 10:53 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-06 10:04 [PATCH v1 00/15] intel_iommu: Enable stage-1 translation for passthrough device Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 01/15] intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry Zhenzhong Duan
2025-06-11 7:20 ` Yi Liu
2025-06-17 17:16 ` Eric Auger
2025-06-06 10:04 ` [PATCH v1 02/15] intel_iommu: Optimize context entry cache utilization Zhenzhong Duan
2025-06-11 7:48 ` Yi Liu
2025-06-11 10:06 ` Duan, Zhenzhong
2025-06-17 10:57 ` Yi Liu [this message]
2025-06-18 1:58 ` Duan, Zhenzhong
2025-06-17 17:24 ` Eric Auger
2025-06-18 2:10 ` Duan, Zhenzhong
2025-06-18 7:08 ` Eric Auger
2025-06-06 10:04 ` [PATCH v1 03/15] intel_iommu: Check for compatibility with IOMMUFD backed device when x-flts=on Zhenzhong Duan
2025-06-17 17:49 ` Eric Auger
2025-06-18 2:14 ` Duan, Zhenzhong
2025-06-18 7:08 ` Eric Auger
2025-06-06 10:04 ` [PATCH v1 04/15] intel_iommu: Introduce a new structure VTDHostIOMMUDevice Zhenzhong Duan
2025-06-12 16:04 ` CLEMENT MATHIEU--DRIF
2025-06-13 9:08 ` Duan, Zhenzhong
2025-06-20 7:08 ` Eric Auger
2025-06-06 10:04 ` [PATCH v1 05/15] intel_iommu: Introduce two helpers vtd_as_from/to_iommu_pasid_locked Zhenzhong Duan
2025-06-11 9:54 ` Yi Liu
2025-06-11 10:46 ` Duan, Zhenzhong
2025-06-17 10:58 ` Yi Liu
2025-06-06 10:04 ` [PATCH v1 06/15] intel_iommu: Handle PASID entry removing and updating Zhenzhong Duan
2025-06-17 12:29 ` Yi Liu
2025-06-18 6:03 ` Duan, Zhenzhong
2025-06-06 10:04 ` [PATCH v1 07/15] intel_iommu: Handle PASID entry adding Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 08/15] intel_iommu: Introduce a new pasid cache invalidation type FORCE_RESET Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 09/15] intel_iommu: Bind/unbind guest page table to host Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 10/15] intel_iommu: ERRATA_772415 workaround Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 11/15] intel_iommu: Replay pasid binds after context cache invalidation Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 12/15] intel_iommu: Propagate PASID-based iotlb invalidation to host Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 13/15] intel_iommu: Refresh pasid bind when either SRTP or TE bit is changed Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 14/15] intel_iommu: Bypass replay in stage-1 page table mode Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 15/15] intel_iommu: Enable host device when x-flts=on in scalable mode Zhenzhong Duan
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