From: Yi Liu <yi.l.liu@intel.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>, <qemu-devel@nongnu.org>
Cc: <alex.williamson@redhat.com>, <clg@redhat.com>,
<eric.auger@redhat.com>, <mst@redhat.com>, <jasowang@redhat.com>,
<peterx@redhat.com>, <ddutile@redhat.com>, <jgg@nvidia.com>,
<nicolinc@nvidia.com>, <shameerali.kolothum.thodi@huawei.com>,
<joao.m.martins@oracle.com>, <clement.mathieu--drif@eviden.com>,
<kevin.tian@intel.com>, <chao.p.peng@intel.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>
Subject: Re: [PATCH v1 02/15] intel_iommu: Optimize context entry cache utilization
Date: Wed, 11 Jun 2025 15:48:14 +0800 [thread overview]
Message-ID: <a36077a1-9eee-4c3b-9365-1b7a9dac3b41@intel.com> (raw)
In-Reply-To: <20250606100416.346132-3-zhenzhong.duan@intel.com>
On 2025/6/6 18:04, Zhenzhong Duan wrote:
> There are many call sites referencing context entry by calling
> vtd_dev_to_context_entry() which will traverse the DMAR table.
>
> In most cases we can use cached context entry in vtd_as->context_cache_entry
> except when its entry is stale. Currently only global and domain context
> invalidation stale it.
>
> So introduce a helper function vtd_as_to_context_entry() to fetch from cache
> before trying with vtd_dev_to_context_entry().
The cached context entry is now protected by vtd_iommu_lock(). While not
all caller of vtd_dev_to_context_entry() are under this lock.
Also, the cached context entry is created in the translate path. IMHO,
this path is not supposed to be triggered for passthrough devices.
While this may need double check and may change in the future. But let's
see if any locking issue with the current code.
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> ---
> hw/i386/intel_iommu.c | 36 +++++++++++++++++++++++-------------
> 1 file changed, 23 insertions(+), 13 deletions(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index f0b1f90eff..a2f3250724 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -1597,6 +1597,22 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
> return 0;
> }
>
> +static int vtd_as_to_context_entry(VTDAddressSpace *vtd_as, VTDContextEntry *ce)
> +{
> + IntelIOMMUState *s = vtd_as->iommu_state;
> + uint8_t bus_num = pci_bus_num(vtd_as->bus);
> + uint8_t devfn = vtd_as->devfn;
> + VTDContextCacheEntry *cc_entry = &vtd_as->context_cache_entry;
> +
> + /* Try to fetch context-entry from cache first */
> + if (cc_entry->context_cache_gen == s->context_cache_gen) {
> + *ce = cc_entry->context_entry;
> + return 0;
> + } else {
> + return vtd_dev_to_context_entry(s, bus_num, devfn, ce);
> + }
> +}
> +
> static int vtd_sync_shadow_page_hook(const IOMMUTLBEvent *event,
> void *private)
> {
> @@ -1649,9 +1665,7 @@ static int vtd_address_space_sync(VTDAddressSpace *vtd_as)
> return 0;
> }
>
> - ret = vtd_dev_to_context_entry(vtd_as->iommu_state,
> - pci_bus_num(vtd_as->bus),
> - vtd_as->devfn, &ce);
> + ret = vtd_as_to_context_entry(vtd_as, &ce);
> if (ret) {
> if (ret == -VTD_FR_CONTEXT_ENTRY_P) {
> /*
> @@ -1710,8 +1724,7 @@ static bool vtd_as_pt_enabled(VTDAddressSpace *as)
> assert(as);
>
> s = as->iommu_state;
> - if (vtd_dev_to_context_entry(s, pci_bus_num(as->bus), as->devfn,
> - &ce)) {
> + if (vtd_as_to_context_entry(as, &ce)) {
> /*
> * Possibly failed to parse the context entry for some reason
> * (e.g., during init, or any guest configuration errors on
> @@ -2435,8 +2448,7 @@ static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
> vtd_iommu_unlock(s);
>
> QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
> - if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
> - vtd_as->devfn, &ce) &&
> + if (!vtd_as_to_context_entry(vtd_as, &ce) &&
this one apparently is called out of lock.
> domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) {
> vtd_address_space_sync(vtd_as);
> }
> @@ -2458,8 +2470,7 @@ static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
> hwaddr size = (1 << am) * VTD_PAGE_SIZE;
>
> QLIST_FOREACH(vtd_as, &(s->vtd_as_with_notifiers), next) {
> - ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
> - vtd_as->devfn, &ce);
> + ret = vtd_as_to_context_entry(vtd_as, &ce);
> if (!ret && domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) {
> uint32_t rid2pasid = PCI_NO_PASID;
>
> @@ -2966,8 +2977,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
> vtd_iommu_unlock(s);
>
> QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
> - if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
> - vtd_as->devfn, &ce) &&
> + if (!vtd_as_to_context_entry(vtd_as, &ce) &&
> domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) {
> uint32_t rid2pasid = VTD_CE_GET_RID2PASID(&ce);
>
> @@ -4146,7 +4156,7 @@ static void vtd_report_ir_illegal_access(VTDAddressSpace *vtd_as,
> assert(vtd_as->pasid != PCI_NO_PASID);
>
> /* Try out best to fetch FPD, we can't do anything more */
> - if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) == 0) {
> + if (vtd_as_to_context_entry(vtd_as, &ce) == 0) {
> is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
> if (!is_fpd_set && s->root_scalable) {
> vtd_ce_get_pasid_fpd(s, &ce, &is_fpd_set, vtd_as->pasid);
> @@ -4506,7 +4516,7 @@ static void vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
> /* replay is protected by BQL, page walk will re-setup it safely */
> iova_tree_remove(vtd_as->iova_tree, map);
>
> - if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) == 0) {
> + if (vtd_as_to_context_entry(vtd_as, &ce) == 0) {
> trace_vtd_replay_ce_valid(s->root_scalable ? "scalable mode" :
> "legacy mode",
> bus_n, PCI_SLOT(vtd_as->devfn),
--
Regards,
Yi Liu
next prev parent reply other threads:[~2025-06-11 7:43 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-06 10:04 [PATCH v1 00/15] intel_iommu: Enable stage-1 translation for passthrough device Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 01/15] intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry Zhenzhong Duan
2025-06-11 7:20 ` Yi Liu
2025-06-17 17:16 ` Eric Auger
2025-06-06 10:04 ` [PATCH v1 02/15] intel_iommu: Optimize context entry cache utilization Zhenzhong Duan
2025-06-11 7:48 ` Yi Liu [this message]
2025-06-11 10:06 ` Duan, Zhenzhong
2025-06-17 10:57 ` Yi Liu
2025-06-18 1:58 ` Duan, Zhenzhong
2025-06-17 17:24 ` Eric Auger
2025-06-18 2:10 ` Duan, Zhenzhong
2025-06-18 7:08 ` Eric Auger
2025-06-06 10:04 ` [PATCH v1 03/15] intel_iommu: Check for compatibility with IOMMUFD backed device when x-flts=on Zhenzhong Duan
2025-06-17 17:49 ` Eric Auger
2025-06-18 2:14 ` Duan, Zhenzhong
2025-06-18 7:08 ` Eric Auger
2025-06-06 10:04 ` [PATCH v1 04/15] intel_iommu: Introduce a new structure VTDHostIOMMUDevice Zhenzhong Duan
2025-06-12 16:04 ` CLEMENT MATHIEU--DRIF
2025-06-13 9:08 ` Duan, Zhenzhong
2025-06-20 7:08 ` Eric Auger
2025-06-06 10:04 ` [PATCH v1 05/15] intel_iommu: Introduce two helpers vtd_as_from/to_iommu_pasid_locked Zhenzhong Duan
2025-06-11 9:54 ` Yi Liu
2025-06-11 10:46 ` Duan, Zhenzhong
2025-06-17 10:58 ` Yi Liu
2025-06-06 10:04 ` [PATCH v1 06/15] intel_iommu: Handle PASID entry removing and updating Zhenzhong Duan
2025-06-17 12:29 ` Yi Liu
2025-06-18 6:03 ` Duan, Zhenzhong
2025-06-06 10:04 ` [PATCH v1 07/15] intel_iommu: Handle PASID entry adding Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 08/15] intel_iommu: Introduce a new pasid cache invalidation type FORCE_RESET Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 09/15] intel_iommu: Bind/unbind guest page table to host Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 10/15] intel_iommu: ERRATA_772415 workaround Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 11/15] intel_iommu: Replay pasid binds after context cache invalidation Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 12/15] intel_iommu: Propagate PASID-based iotlb invalidation to host Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 13/15] intel_iommu: Refresh pasid bind when either SRTP or TE bit is changed Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 14/15] intel_iommu: Bypass replay in stage-1 page table mode Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 15/15] intel_iommu: Enable host device when x-flts=on in scalable mode Zhenzhong Duan
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