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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Atish Patra <atishp@rivosinc.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: kaiwenxue1@gmail.com, palmer@dabbelt.com, liwei1518@gmail.com,
	zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com,
	alistair.francis@wdc.com
Subject: Re: [PATCH v3 05/11] target/riscv: Add properties for counter delegation ISA extensions
Date: Thu, 28 Nov 2024 08:55:01 -0300	[thread overview]
Message-ID: <9cbfaa84-6d6c-4702-837d-45b9d218f2e2@ventanamicro.com> (raw)
In-Reply-To: <20241117-counter_delegation-v3-5-476d6f36e3c8@rivosinc.com>



On 11/17/24 10:15 PM, Atish Patra wrote:
> This adds the properties for counter delegation ISA extensions
> (Smcdeleg/Ssccfg). Definitions of new registers and and implementation
> will come in the next set of patches.
> 
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c     | 2 ++
>   target/riscv/cpu_cfg.h | 2 ++
>   2 files changed, 4 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 963f1f3af9ae..82edd28e2e1d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -184,11 +184,13 @@ const RISCVIsaExtData isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
>       ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
>       ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
> +    ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg),
>       ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
>       ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind),
>       ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
>       ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
>       ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
> +    ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_13_0, ext_ssccfg),
>       ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
>       ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
>       ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 8b974255f6fb..ae2b019703fe 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -78,6 +78,8 @@ struct RISCVCPUConfig {
>       bool ext_ztso;
>       bool ext_smstateen;
>       bool ext_sstc;
> +    bool ext_smcdeleg;
> +    bool ext_ssccfg;
>       bool ext_smcntrpmf;
>       bool ext_smcsrind;
>       bool ext_sscsrind;
> 



  reply	other threads:[~2024-11-28 11:55 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-18  1:15 [PATCH v3 00/11] Add RISC-V Counter delegation ISA extension support Atish Patra
2024-11-18  1:15 ` [PATCH v3 01/11] target/riscv: Add properties for Indirect CSR Access extension Atish Patra
2024-11-28 11:39   ` Daniel Henrique Barboza
2024-11-18  1:15 ` [PATCH v3 02/11] target/riscv: Decouple AIA processing from xiselect and xireg Atish Patra
2024-11-18  1:15 ` [PATCH v3 03/11] target/riscv: Enable S*stateen bits for AIA Atish Patra
2024-11-18  1:15 ` [PATCH v3 04/11] target/riscv: Support generic CSR indirect access Atish Patra
2024-11-28 11:52   ` Daniel Henrique Barboza
2024-11-28 12:52     ` Richard Henderson
2024-12-02 21:16     ` Atish Kumar Patra
2024-11-18  1:15 ` [PATCH v3 05/11] target/riscv: Add properties for counter delegation ISA extensions Atish Patra
2024-11-28 11:55   ` Daniel Henrique Barboza [this message]
2024-11-18  1:15 ` [PATCH v3 06/11] target/riscv: Add counter delegation definitions Atish Patra
2024-11-18  1:15 ` [PATCH v3 07/11] target/riscv: Add select value range check for counter delegation Atish Patra
2024-11-18  1:15 ` [PATCH v3 08/11] target/riscv: Add counter delegation/configuration support Atish Patra
2024-11-28 12:53   ` Daniel Henrique Barboza
2024-12-02 21:15     ` Atish Kumar Patra
2024-12-02 21:49       ` Daniel Henrique Barboza
2024-12-02 23:47         ` Atish Kumar Patra
2024-11-18  1:15 ` [PATCH v3 09/11] target/riscv: Invoke pmu init after feature enable Atish Patra
2024-11-18  1:15 ` [PATCH v3 10/11] target/riscv: Add implied rule for counter delegation extensions Atish Patra
2024-11-28 12:54   ` Daniel Henrique Barboza
2024-11-18  1:15 ` [PATCH v3 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg Atish Patra
2024-11-28 12:58   ` Daniel Henrique Barboza

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