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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Atish Patra <atishp@rivosinc.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: kaiwenxue1@gmail.com, palmer@dabbelt.com, liwei1518@gmail.com,
	zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com,
	alistair.francis@wdc.com
Subject: Re: [PATCH v3 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg
Date: Thu, 28 Nov 2024 09:58:55 -0300	[thread overview]
Message-ID: <fca701ec-a3b8-4db1-a14f-73d72fcb85b2@ventanamicro.com> (raw)
In-Reply-To: <20241117-counter_delegation-v3-11-476d6f36e3c8@rivosinc.com>



On 11/17/24 10:15 PM, Atish Patra wrote:
> Add configuration options so that they can be enabled/disabld from
> qemu commandline.
> 
> Acked-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 410ca2e3a666..2a4f285a974f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1477,6 +1477,10 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>       /* Defaults for standard extensions */
>       MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
>       MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false),
> +    MULTI_EXT_CFG_BOOL("smcsrind", ext_smcsrind, false),
> +    MULTI_EXT_CFG_BOOL("smcdeleg", ext_smcdeleg, false),
> +    MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false),
> +    MULTI_EXT_CFG_BOOL("ssccfg", ext_ssccfg, false),
>       MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
>       MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false),
>       MULTI_EXT_CFG_BOOL("zicfiss", ext_zicfiss, false),
> 



      reply	other threads:[~2024-11-28 12:59 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-18  1:15 [PATCH v3 00/11] Add RISC-V Counter delegation ISA extension support Atish Patra
2024-11-18  1:15 ` [PATCH v3 01/11] target/riscv: Add properties for Indirect CSR Access extension Atish Patra
2024-11-28 11:39   ` Daniel Henrique Barboza
2024-11-18  1:15 ` [PATCH v3 02/11] target/riscv: Decouple AIA processing from xiselect and xireg Atish Patra
2024-11-18  1:15 ` [PATCH v3 03/11] target/riscv: Enable S*stateen bits for AIA Atish Patra
2024-11-18  1:15 ` [PATCH v3 04/11] target/riscv: Support generic CSR indirect access Atish Patra
2024-11-28 11:52   ` Daniel Henrique Barboza
2024-11-28 12:52     ` Richard Henderson
2024-12-02 21:16     ` Atish Kumar Patra
2024-11-18  1:15 ` [PATCH v3 05/11] target/riscv: Add properties for counter delegation ISA extensions Atish Patra
2024-11-28 11:55   ` Daniel Henrique Barboza
2024-11-18  1:15 ` [PATCH v3 06/11] target/riscv: Add counter delegation definitions Atish Patra
2024-11-18  1:15 ` [PATCH v3 07/11] target/riscv: Add select value range check for counter delegation Atish Patra
2024-11-18  1:15 ` [PATCH v3 08/11] target/riscv: Add counter delegation/configuration support Atish Patra
2024-11-28 12:53   ` Daniel Henrique Barboza
2024-12-02 21:15     ` Atish Kumar Patra
2024-12-02 21:49       ` Daniel Henrique Barboza
2024-12-02 23:47         ` Atish Kumar Patra
2024-11-18  1:15 ` [PATCH v3 09/11] target/riscv: Invoke pmu init after feature enable Atish Patra
2024-11-18  1:15 ` [PATCH v3 10/11] target/riscv: Add implied rule for counter delegation extensions Atish Patra
2024-11-28 12:54   ` Daniel Henrique Barboza
2024-11-18  1:15 ` [PATCH v3 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg Atish Patra
2024-11-28 12:58   ` Daniel Henrique Barboza [this message]

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