From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Jiri Slaby <jirislaby@kernel.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-serial <linux-serial@vger.kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
"linux-renesas-soc@vger.kernel.org"
<linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH v3 3/3] serial: 8250_em: Add serial_out() to struct serial8250_em_hw_info
Date: Mon, 13 Feb 2023 11:22:26 +0200 (EET) [thread overview]
Message-ID: <9d141bd9-ca58-4ea-e17b-4a3229eda9b2@linux.intel.com> (raw)
In-Reply-To: <56c8fdab-a037-ea00-d83e-f75c92566d92@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 1555 bytes --]
On Mon, 13 Feb 2023, Jiri Slaby wrote:
> On 13. 02. 23, 10:10, Jiri Slaby wrote:
> > On 13. 02. 23, 9:53, Biju Das wrote:
> > > > > +static void serial8250_rzv2m_reg_update(struct uart_port *p, int off,
> > > > > +int value) {
> > > > > + unsigned int ier, fcr, lcr, mcr, hcr0;
> > > > > +
> > > > > + ier = serial8250_em_serial_in(p, UART_IER);
> > > > > + lcr = serial8250_em_serial_in(p, UART_LCR);
> > > > > + mcr = serial8250_em_serial_in(p, UART_MCR);
> > > > > + hcr0 = serial8250_em_serial_in(p, UART_HCR0);
> > > > > + /*
> > > > > + * The value of UART_IIR and UART_FCR are 2, but corresponding
> > > > > + * RZ/V2M address offset are different(0x08 and 0x0c). So we need
> > > > > to
> > > > > + * use readl() here.
> > > > > + */
> > > > > + fcr = readl(p->membase + ((UART_FCR + 1) << 2));
> > > >
> > > > I don't get the meaning of that comment. It doesn't seem to match what
> > > > your
> > > > code does as the code seemingly has nothing to do with IIR (and none of
> > > > you
> > > > changelogs refer to IIR either)?
> > >
> > > The generic macro UART_IIR and UART_FCR in linux/serial_reg.h has a value
> > > of 2.
> >
> > Sure, IIR is normally WO and FCR RO and share the same register. I would
> > simply define UART_FCR_RZ (or alike)
>
> Or even UART_FCR_RO_RZ?
>
> > for 0x12.
>
> I mean 12 or 0xc.
Won't that collide with LCR reads then? They are currently mapped by
return 0; but after adding a case for UART_FCR_RO_RZ they'll read from
what is the FCR register on this HW?
--
i.
next prev parent reply other threads:[~2023-02-13 9:22 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-10 20:34 [PATCH v3 0/3] Update Renesas RZ/V2M UART Port type Biju Das
2023-02-10 20:34 ` [PATCH v3 1/3] serial: 8250_em: Use dev_err_probe() Biju Das
2023-02-13 6:23 ` Jiri Slaby
2023-02-14 11:07 ` Biju Das
2023-02-10 20:34 ` [PATCH v3 2/3] serial: 8250_em: Update RZ/V2M port type as PORT_16750 Biju Das
2023-02-12 11:02 ` Andy Shevchenko
2023-02-13 6:26 ` Jiri Slaby
2023-02-13 16:02 ` Biju Das
2023-02-10 20:34 ` [PATCH v3 3/3] serial: 8250_em: Add serial_out() to struct serial8250_em_hw_info Biju Das
2023-02-12 11:09 ` Andy Shevchenko
2023-02-13 8:42 ` Ilpo Järvinen
2023-02-13 8:53 ` Biju Das
2023-02-13 9:10 ` Jiri Slaby
2023-02-13 9:12 ` Jiri Slaby
2023-02-13 9:14 ` Jiri Slaby
2023-02-13 9:31 ` Biju Das
2023-02-13 9:32 ` Jiri Slaby
2023-02-13 11:12 ` Biju Das
2023-02-13 11:31 ` Ilpo Järvinen
2023-02-13 11:40 ` Biju Das
2023-02-13 12:05 ` Ilpo Järvinen
2023-02-13 12:18 ` Biju Das
2023-02-13 16:06 ` Biju Das
2023-02-13 9:57 ` Niklas Söderlund
2023-02-13 10:06 ` Biju Das
2023-02-13 10:29 ` Niklas Söderlund
2023-02-13 13:01 ` Biju Das
2023-02-13 14:09 ` Niklas Söderlund
2023-02-13 14:26 ` Biju Das
2023-02-13 9:22 ` Ilpo Järvinen [this message]
2023-02-13 9:28 ` Jiri Slaby
2023-02-13 9:40 ` Ilpo Järvinen
2023-02-13 9:53 ` Jiri Slaby
2023-02-13 9:12 ` Ilpo Järvinen
2023-02-13 8:37 ` [PATCH v3 0/3] Update Renesas RZ/V2M UART Port type Ilpo Järvinen
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