Re: [PATCH v2 0/3] cxl/pci: Fix the GPF DVSEC setup path

[Dave Jiang <dave.jiang@intel.com>]

On 10/7/26 8:46 PM, Guixin Liu wrote:
> Three small fixes for the GPF setup path in cxl/core/pci.c, found
> while reworking the same area for a downstream backport.
> 
> Patch 1 is the one with user-visible impact: on an RCD the GPF DVSEC
> lookup takes the port path, so dirty shutdown tracking never arms and
> the count stays invalid. The other two deal with error handling and
> a full-register rewrite of the phase control register.
> 
> Testing on a QEMU CXL topology, with the patched cxl_core hot-swapped
> in and the topology re-enumerated. With the phase 1/2 timeout
> registers of all four dports (two root ports, two switch downstream
> ports) zeroed beforehand, every dport came back at 0x0702 — base 2,
> scale 7, the same value the unpatched code writes. So the timeout
> write ran on each of them: the read-modify-write of patch 3, through
> the error-checked setup of patch 2. With the registers left at their
> programmed value instead, the setup takes the "already at max" early
> return and writes nothing. Re-enumeration comes up clean, all three
> memdevs back.
> 
> What QEMU cannot exercise: the topology has no RCD, so the RC_END
> branch of patch 1 never ran — though the emulated type-3 devices do
> expose the Device GPF DVSEC that the fix selects for a restricted
> endpoint. A config write to a live DVSEC does not fail, so the error
> paths of patch 2 stayed cold. And the phase control register defines
> no non-timeout bits today, so patch 3 lands on the same value the old
> full rewrite did.
> 
> Changes since v1 [1]:
> 
> - Collect the Reviewed-by tags from Jonathan Cameron and Dave Jiang
>   for patches 1 and 2 (code unchanged).
> 
> - Rework patch 3 to use a pair of FIELD_MODIFY() calls instead of
>   clearing and setting the timeout masks by hand, as suggested by
>   Jonathan Cameron. The generated code for update_gpf_port_dvsec()
>   is identical to the manual version.
> 
> [1] https://lore.kernel.org/all/20260922100026.3742401-1-kanie@linux.alibaba.com/
> 
> Guixin Liu (3):
>   cxl/pci: Use the Device GPF DVSEC for restricted endpoints
>   cxl/pci: Program the Port GPF timeouts before caching the DVSEC
>   cxl/pci: Update only the Port GPF timeout fields
> 
>  drivers/cxl/core/pci.c | 37 +++++++++++++++++++++++++------------
>  1 file changed, 25 insertions(+), 12 deletions(-)
> 

Applied to cxl/next:
b5d14009bdb1
ec2e30a68294
d2654fa0d841