From: Alison Schofield <alison.schofield@intel.com>
To: Guixin Liu <kanie@linux.alibaba.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jic23@kernel.org>,
Dave Jiang <dave.jiang@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Dan Williams <djbw@kernel.org>, Ira Weiny <iweiny@kernel.org>,
Li Ming <ming.li@zohomail.com>, <linux-cxl@vger.kernel.org>
Subject: Re: [PATCH v2 3/3] cxl/pci: Update only the Port GPF timeout fields
Date: Fri, 9 Oct 2026 12:03:40 -0700 [thread overview]
Message-ID: <ask6jMPLO7XIvnOG@aschofie-mobl2.lan> (raw)
In-Reply-To: <20261008034619.28059-4-kanie@linux.alibaba.com>
On Thu, Oct 08, 2026 at 11:46:14AM +0800, Guixin Liu wrote:
> update_gpf_port_dvsec() rebuilds the phase control register from just
> the timeout base and scale, so the rest of the register is cleared by
> the write. The other bits are reserved today and nothing is lost, but
> the full-register rewrite would clobber any field the spec defines
> there later.
>
> Read-modify-write the register and change only the two timeout
> fields.
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
next prev parent reply other threads:[~2026-10-09 19:03 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-08 3:46 [PATCH v2 0/3] cxl/pci: Fix the GPF DVSEC setup path Guixin Liu
2026-10-08 3:46 ` [PATCH v2 1/3] cxl/pci: Use the Device GPF DVSEC for restricted endpoints Guixin Liu
2026-10-09 19:02 ` Alison Schofield
2026-10-08 3:46 ` [PATCH v2 2/3] cxl/pci: Program the Port GPF timeouts before caching the DVSEC Guixin Liu
2026-10-08 3:58 ` sashiko-bot
2026-10-09 19:03 ` Alison Schofield
2026-10-08 3:46 ` [PATCH v2 3/3] cxl/pci: Update only the Port GPF timeout fields Guixin Liu
2026-10-09 17:27 ` Dave Jiang
2026-10-09 19:03 ` Alison Schofield [this message]
2026-10-09 21:48 ` [PATCH v2 0/3] cxl/pci: Fix the GPF DVSEC setup path Dave Jiang
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