* [Bug #14380] Video tearing/glitching with T400 laptops
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List
Cc: Kernel Testers List, Arkadiusz Miskiewicz, Jesse Barnes,
Theodore Ts'o
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14380
Subject : Video tearing/glitching with T400 laptops
Submitter : Theodore Ts'o <tytso@mit.edu>
Date : 2009-10-02 22:40 (10 days old)
References : http://marc.info/?l=linux-kernel&m=125452324520623&w=4
Handled-By : Jesse Barnes <jbarnes@virtuousgeek.org>
^ permalink raw reply
* [Bug #14379] ACPI Warning for _SB_.BAT0._BIF: Converted Buffer to expected String
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List; +Cc: Kernel Testers List, Justin Mattock
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14379
Subject : ACPI Warning for _SB_.BAT0._BIF: Converted Buffer to expected String
Submitter : Justin Mattock <justinmattock@gmail.com>
Date : 2009-10-08 21:46 (4 days old)
References : http://marc.info/?l=linux-kernel&m=125504031328941&w=4
^ permalink raw reply
* [PATCH v3 7/7] mfd: add AB4500 SPI used in U8500
From: srinidhi kasagar @ 2009-10-11 22:28 UTC (permalink / raw)
To: linux-arm-kernel
From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
This adds core driver support for AB4500 mixed signal
multimedia & power management chip. This connects to U8500
on the SSP (pl022) and exports read/write functions for
the device to get access to this chip. This also registers
the client devices and sets the parent.
The chip is now called as AB4500, whereas in the older version
it was called as STW4500. This just renames stw4500 as ab4500.
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
Reviewed-by: Mark Brown <broonie@sirena.org.uk>
Reviewed-by: Jean-Christophe <plagnioj@jcrosoft.com>
---
drivers/mfd/Kconfig | 10 ++
drivers/mfd/Makefile | 1 +
drivers/mfd/ab4500-core.c | 207 ++++++++++++++++++++++++++++++++++
include/linux/mfd/ab4500.h | 262 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 480 insertions(+), 0 deletions(-)
create mode 100755 drivers/mfd/ab4500-core.c
create mode 100644 include/linux/mfd/ab4500.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 570be13..4b2c97d 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -305,6 +305,16 @@ config EZX_PCAP
This enables the PCAP ASIC present on EZX Phones. This is
needed for MMC, TouchScreen, Sound, USB, etc..
+config AB4500_CORE
+ tristate "ST-Ericsson's AB4500 Mixed Signal Power management chip"
+ depends on SPI
+ default y
+ help
+ Select this option to enable access to AB4500 power management
+ chip. This connects to U8500 on the SSP/SPI bus and exports
+ read/write functions for the devices to get access to this chip.
+ This chip embeds various other multimedia funtionalities as well.
+
endmenu
menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index f3b277b..0d98968 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -50,3 +50,4 @@ obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o
obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o
obj-$(CONFIG_AB3100_CORE) += ab3100-core.o
obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o
+obj-$(CONFIG_AB4500_CORE) += ab4500-core.o
diff --git a/drivers/mfd/ab4500-core.c b/drivers/mfd/ab4500-core.c
new file mode 100755
index 0000000..3ad91f7
--- /dev/null
+++ b/drivers/mfd/ab4500-core.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
+ *
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation.
+ *
+ * AB4500 is a companion power management chip used with U8500.
+ * On this platform, this is interfaced with SSP0 controller
+ * which is a ARM primecell pl022.
+ *
+ * At the moment the module just exports read/write features.
+ * Interrupt management to be added - TODO.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/ab4500.h>
+
+/* just required if probe fails, we need to
+ * unregister the device
+ */
+static struct spi_driver ab4500_driver;
+
+/*
+ * This funtion writes to any AB4500 registers using
+ * SPI protocol & before it writes it packs the data
+ * in the below 24 bit frame format
+ *
+ * *|------------------------------------|
+ * *| 23|22...18|17.......10|9|8|7......0|
+ * *| r/w bank adr data |
+ * * ------------------------------------
+ *
+ * This function shouldn't be called from interrupt
+ * context
+ */
+int ab4500_write(struct ab4500 *ab4500, unsigned char block,
+ unsigned long addr, unsigned char data)
+{
+ struct spi_transfer xfer;
+ struct spi_message msg;
+ int err;
+ unsigned long spi_data =
+ block << 18 | addr << 10 | data;
+
+ mutex_lock(&ab4500->lock);
+ ab4500->tx_buf[0] = spi_data;
+ ab4500->rx_buf[0] = 0;
+
+ xfer.tx_buf = ab4500->tx_buf;
+ xfer.rx_buf = NULL;
+ xfer.len = sizeof(unsigned long);
+
+ spi_message_init(&msg);
+ spi_message_add_tail(&xfer, &msg);
+
+ err = spi_sync(ab4500->spi, &msg);
+ mutex_unlock(&ab4500->lock);
+
+ return err;
+}
+EXPORT_SYMBOL(ab4500_write);
+
+int ab4500_read(struct ab4500 *ab4500, unsigned char block,
+ unsigned long addr)
+{
+ struct spi_transfer xfer;
+ struct spi_message msg;
+ unsigned long spi_data =
+ 1 << 23 | block << 18 | addr << 10;
+
+ mutex_lock(&ab4500->lock);
+ ab4500->tx_buf[0] = spi_data;
+ ab4500->rx_buf[0] = 0;
+
+ xfer.tx_buf = ab4500->tx_buf;
+ xfer.rx_buf = ab4500->rx_buf;
+ xfer.len = sizeof(unsigned long);
+
+ spi_message_init(&msg);
+ spi_message_add_tail(&xfer, &msg);
+
+ spi_sync(ab4500->spi, &msg);
+ mutex_unlock(&ab4500->lock);
+
+ return ab4500->rx_buf[0];
+}
+EXPORT_SYMBOL(ab4500_read);
+
+/* ref: ab3100 core */
+#define AB4500_DEVICE(devname, devid) \
+static struct platform_device ab4500_##devname##_device = { \
+ .name = devid, \
+ .id = -1, \
+}
+
+/* list of childern devices of ab4500 - all are
+ * not populated here - TODO
+ */
+AB4500_DEVICE(charger, "ab4500-charger");
+AB4500_DEVICE(audio, "ab4500-audio");
+AB4500_DEVICE(usb, "ab4500-usb");
+AB4500_DEVICE(tvout, "ab4500-tvout");
+AB4500_DEVICE(sim, "ab4500-sim");
+AB4500_DEVICE(gpadc, "ab4500-gpadc");
+AB4500_DEVICE(clkmgt, "ab4500-clkmgt");
+AB4500_DEVICE(misc, "ab4500-misc");
+
+static struct platform_device *ab4500_platform_devs[] = {
+ &ab4500_charger_device,
+ &ab4500_audio_device,
+ &ab4500_usb_device,
+ &ab4500_tvout_device,
+ &ab4500_sim_device,
+ &ab4500_gpadc_device,
+ &ab4500_clkmgt_device,
+ &ab4500_misc_device,
+};
+
+static int __init ab4500_probe(struct spi_device *spi)
+{
+ struct ab4500 *ab4500;
+ unsigned char revision;
+ int err = 0;
+ int i;
+
+ ab4500 = kzalloc(sizeof *ab4500, GFP_KERNEL);
+ if (!ab4500) {
+ dev_err(&spi->dev, "could not allocate AB4500\n");
+ err = -ENOMEM;
+ goto not_detect;
+ }
+
+ ab4500->spi = spi;
+ spi_set_drvdata(spi, ab4500);
+
+ mutex_init(&ab4500->lock);
+
+ /* read the revision register */
+ revision = ab4500_read(ab4500, AB4500_MISC, AB4500_REV_REG);
+
+ /* revision id 0x0 is for early drop, 0x10 is for cut1.0 */
+ if (revision == 0x0 || revision == 0x10)
+ dev_info(&spi->dev, "Detected chip: %s, revision = %x\n",
+ ab4500_driver.driver.name, revision);
+ else {
+ dev_err(&spi->dev, "unknown chip: 0x%x\n", revision);
+ goto not_detect;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ab4500_platform_devs); i++) {
+ ab4500_platform_devs[i]->dev.parent =
+ &spi->dev;
+ platform_set_drvdata(ab4500_platform_devs[i], ab4500);
+ }
+
+ /* register the ab4500 platform devices */
+ platform_add_devices(ab4500_platform_devs,
+ ARRAY_SIZE(ab4500_platform_devs));
+
+ return err;
+
+ not_detect:
+ spi_unregister_driver(&ab4500_driver);
+ kfree(ab4500);
+ return err;
+}
+
+static int __devexit ab4500_remove(struct spi_device *spi)
+{
+ struct ab4500 *ab4500 =
+ spi_get_drvdata(spi);
+
+ kfree(ab4500);
+
+ return 0;
+}
+
+static struct spi_driver ab4500_driver = {
+ .driver = {
+ .name = "ab4500",
+ .owner = THIS_MODULE,
+ },
+ .probe = ab4500_probe,
+ .remove = __devexit_p(ab4500_remove)
+};
+
+static int __devinit ab4500_init(void)
+{
+ return spi_register_driver(&ab4500_driver);
+}
+
+static void __exit ab4500_exit(void)
+{
+ spi_unregister_driver(&ab4500_driver);
+}
+
+subsys_initcall_sync(ab4500_init);
+
+MODULE_AUTHOR("Srinidhi KASAGAR <srinidhi.kasagar at stericsson.com");
+MODULE_DESCRIPTION("AB4500 core driver");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/mfd/ab4500.h b/include/linux/mfd/ab4500.h
new file mode 100644
index 0000000..a42a703
--- /dev/null
+++ b/include/linux/mfd/ab4500.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ * AB4500 device core funtions, for client access
+ */
+#ifndef MFD_AB4500_H
+#define MFD_AB4500_H
+
+#include <linux/device.h>
+
+/*
+ * AB4500 bank addresses
+ */
+#define AB4500_SYS_CTRL1_BLOCK 0x1
+#define AB4500_SYS_CTRL2_BLOCK 0x2
+#define AB4500_REGU_CTRL1 0x3
+#define AB4500_REGU_CTRL2 0x4
+#define AB4500_USB 0x5
+#define AB4500_TVOUT 0x6
+#define AB4500_DBI 0x7
+#define AB4500_ECI_AV_ACC 0x8
+#define AB4500_RESERVED 0x9
+#define AB4500_GPADC 0xA
+#define AB4500_CHARGER 0xB
+#define AB4500_GAS_GAUGE 0xC
+#define AB4500_AUDIO 0xD
+#define AB4500_INTERRUPT 0xE
+#define AB4500_RTC 0xF
+#define AB4500_MISC 0x10
+#define AB4500_DEBUG 0x12
+#define AB4500_PROD_TEST 0x13
+#define AB4500_OTP_EMUL 0x15
+
+/*
+ * System control 1 register offsets.
+ * Bank = 0x01
+ */
+#define AB4500_TURNON_STAT_REG 0x0100
+#define AB4500_RESET_STAT_REG 0x0101
+#define AB4500_PONKEY1_PRESS_STAT_REG 0x0102
+
+#define AB4500_FSM_STAT1_REG 0x0140
+#define AB4500_FSM_STAT2_REG 0x0141
+#define AB4500_SYSCLK_REQ_STAT_REG 0x0142
+#define AB4500_USB_STAT1_REG 0x0143
+#define AB4500_USB_STAT2_REG 0x0144
+#define AB4500_STATUS_SPARE1_REG 0x0145
+#define AB4500_STATUS_SPARE2_REG 0x0146
+
+#define AB4500_CTRL1_REG 0x0180
+#define AB4500_CTRL2_REG 0x0181
+
+/*
+ * System control 2 register offsets.
+ * bank = 0x02
+ */
+#define AB4500_CTRL3_REG 0x0200
+#define AB4500_MAIN_WDOG_CTRL_REG 0x0201
+#define AB4500_MAIN_WDOG_TIMER_REG 0x0202
+#define AB4500_LOW_BAT_REG 0x0203
+#define AB4500_BATT_OK_REG 0x0204
+#define AB4500_SYSCLK_TIMER_REG 0x0205
+#define AB4500_SMPSCLK_CTRL_REG 0x0206
+#define AB4500_SMPSCLK_SEL1_REG 0x0207
+#define AB4500_SMPSCLK_SEL2_REG 0x0208
+#define AB4500_SMPSCLK_SEL3_REG 0x0209
+#define AB4500_SYSULPCLK_CONF_REG 0x020A
+#define AB4500_SYSULPCLK_CTRL1_REG 0x020B
+#define AB4500_SYSCLK_CTRL_REG 0x020C
+#define AB4500_SYSCLK_REQ1_VALID_REG 0x020D
+#define AB4500_SYSCLK_REQ_VALID_REG 0x020E
+#define AB4500_SYSCTRL_SPARE_REG 0x020F
+#define AB4500_PAD_CONF_REG 0x0210
+
+/*
+ * Regu control1 register offsets
+ * Bank = 0x03
+ */
+#define AB4500_REGU_SERIAL_CTRL1_REG 0x0300
+#define AB4500_REGU_SERIAL_CTRL2_REG 0x0301
+#define AB4500_REGU_SERIAL_CTRL3_REG 0x0302
+#define AB4500_REGU_REQ_CTRL1_REG 0x0303
+#define AB4500_REGU_REQ_CTRL2_REG 0x0304
+#define AB4500_REGU_REQ_CTRL3_REG 0x0305
+#define AB4500_REGU_REQ_CTRL4_REG 0x0306
+#define AB4500_REGU_MISC1_REG 0x0380
+#define AB4500_REGU_OTGSUPPLY_CTRL_REG 0x0381
+#define AB4500_REGU_VUSB_CTRL_REG 0x0382
+#define AB4500_REGU_VAUDIO_SUPPLY_REG 0x0383
+#define AB4500_REGU_CTRL1_SPARE_REG 0x0384
+
+/*
+ * Regu control2 Vmod register offsets
+ */
+#define AB4500_REGU_VMOD_REGU_REG 0x0440
+#define AB4500_REGU_VMOD_SEL1_REG 0x0441
+#define AB4500_REGU_VMOD_SEL2_REG 0x0442
+#define AB4500_REGU_CTRL_DISCH_REG 0x0443
+#define AB4500_REGU_CTRL_DISCH2_REG 0x0444
+
+/*
+ * USB/ULPI register offsets
+ * Bank : 0x5
+ */
+#define AB4500_USB_LINE_STAT_REG 0x0580
+#define AB4500_USB_LINE_CTRL1_REG 0x0581
+#define AB4500_USB_LINE_CTRL2_REG 0x0582
+#define AB4500_USB_LINE_CTRL3_REG 0x0583
+#define AB4500_USB_LINE_CTRL4_REG 0x0584
+#define AB4500_USB_LINE_CTRL5_REG 0x0585
+#define AB4500_USB_OTG_CTRL_REG 0x0587
+#define AB4500_USB_OTG_STAT_REG 0x0588
+#define AB4500_USB_OTG_STAT_REG 0x0588
+#define AB4500_USB_CTRL_SPARE_REG 0x0589
+#define AB4500_USB_PHY_CTRL_REG 0x058A
+
+/*
+ * TVOUT / CTRL register offsets
+ * Bank : 0x06
+ */
+#define AB4500_TVOUT_CTRL_REG 0x0680
+
+/*
+ * DBI register offsets
+ * Bank : 0x07
+ */
+#define AB4500_DBI_REG1_REG 0x0700
+#define AB4500_DBI_REG2_REG 0x0701
+
+/*
+ * ECI regsiter offsets
+ * Bank : 0x08
+ */
+#define AB4500_ECI_CTRL_REG 0x0800
+#define AB4500_ECI_HOOKLEVEL_REG 0x0801
+#define AB4500_ECI_DATAOUT_REG 0x0802
+#define AB4500_ECI_DATAIN_REG 0x0803
+
+/*
+ * AV Connector register offsets
+ * Bank : 0x08
+ */
+#define AB4500_AV_CONN_REG 0x0840
+
+/*
+ * Accessory detection register offsets
+ * Bank : 0x08
+ */
+#define AB4500_ACC_DET_DB1_REG 0x0880
+#define AB4500_ACC_DET_DB2_REG 0x0881
+
+/*
+ * GPADC register offsets
+ * Bank : 0x0A
+ */
+#define AB4500_GPADC_CTRL1_REG 0x0A00
+#define AB4500_GPADC_CTRL2_REG 0x0A01
+#define AB4500_GPADC_CTRL3_REG 0x0A02
+#define AB4500_GPADC_AUTO_TIMER_REG 0x0A03
+#define AB4500_GPADC_STAT_REG 0x0A04
+#define AB4500_GPADC_MANDATAL_REG 0x0A05
+#define AB4500_GPADC_MANDATAH_REG 0x0A06
+#define AB4500_GPADC_AUTODATAL_REG 0x0A07
+#define AB4500_GPADC_AUTODATAH_REG 0x0A08
+#define AB4500_GPADC_MUX_CTRL_REG 0x0A09
+
+/*
+ * Charger / status register offfsets
+ * Bank : 0x0B
+ */
+#define AB4500_CH_STATUS1_REG 0x0B00
+#define AB4500_CH_STATUS2_REG 0x0B01
+#define AB4500_CH_USBCH_STAT1_REG 0x0B02
+#define AB4500_CH_USBCH_STAT2_REG 0x0B03
+#define AB4500_CH_FSM_STAT_REG 0x0B04
+#define AB4500_CH_STAT_REG 0x0B05
+
+/*
+ * Charger / control register offfsets
+ * Bank : 0x0B
+ */
+#define AB4500_CH_VOLT_LVL_REG 0x0B40
+
+/*
+ * Charger / main control register offfsets
+ * Bank : 0x0B
+ */
+#define AB4500_MCH_CTRL1 0x0B80
+#define AB4500_MCH_CTRL2 0x0B81
+#define AB4500_MCH_IPT_CURLVL_REG 0x0B82
+#define AB4500_CH_WD_REG 0x0B83
+
+/*
+ * Charger / USB control register offsets
+ * Bank : 0x0B
+ */
+#define AB4500_USBCH_CTRL1_REG 0x0BC0
+#define AB4500_USBCH_CTRL2_REG 0x0BC1
+#define AB4500_USBCH_IPT_CRNTLVL_REG 0x0BC2
+
+/*
+ * RTC bank register offsets
+ * Bank : 0xF
+ */
+#define AB4500_RTC_SOFF_STAT_REG 0x0F00
+#define AB4500_RTC_CC_CONF_REG 0x0F01
+#define AB4500_RTC_READ_REQ_REG 0x0F02
+#define AB4500_RTC_WATCH_TSECMID_REG 0x0F03
+#define AB4500_RTC_WATCH_TSECHI_REG 0x0F04
+#define AB4500_RTC_WATCH_TMIN_LOW_REG 0x0F05
+#define AB4500_RTC_WATCH_TMIN_MID_REG 0x0F06
+#define AB4500_RTC_WATCH_TMIN_HI_REG 0x0F07
+#define AB4500_RTC_ALRM_MIN_LOW_REG 0x0F08
+#define AB4500_RTC_ALRM_MIN_MID_REG 0x0F09
+#define AB4500_RTC_ALRM_MIN_HI_REG 0x0F0A
+#define AB4500_RTC_STAT_REG 0x0F0B
+#define AB4500_RTC_BKUP_CHG_REG 0x0F0C
+#define AB4500_RTC_FORCE_BKUP_REG 0x0F0D
+#define AB4500_RTC_CALIB_REG 0x0F0E
+#define AB4500_RTC_SWITCH_STAT_REG 0x0F0F
+
+/*
+ * PWM Out generators
+ * Bank: 0x10
+ */
+#define AB4500_PWM_OUT_CTRL1_REG 0x1060
+#define AB4500_PWM_OUT_CTRL2_REG 0x1061
+#define AB4500_PWM_OUT_CTRL3_REG 0x1062
+#define AB4500_PWM_OUT_CTRL4_REG 0x1063
+#define AB4500_PWM_OUT_CTRL5_REG 0x1064
+#define AB4500_PWM_OUT_CTRL6_REG 0x1065
+#define AB4500_PWM_OUT_CTRL7_REG 0x1066
+
+#define AB4500_I2C_PAD_CTRL_REG 0x1067
+#define AB4500_REV_REG 0x1080
+
+/**
+ * struct ab4500
+ * @spi: spi device structure
+ * @tx_buf: transmit buffer
+ * @rx_buf: receive buffer
+ * @lock: sync primitive
+ */
+struct ab4500 {
+ struct spi_device *spi;
+ unsigned long tx_buf[4];
+ unsigned long rx_buf[4];
+ struct mutex lock;
+};
+
+int ab4500_write(struct ab4500 *ab4500, unsigned char block,
+ unsigned long addr, unsigned char data);
+int ab4500_read(struct ab4500 *ab4500, unsigned char block,
+ unsigned long addr);
+
+#endif /* MFD_AB4500_H */
--
1.6.3.GIT
^ permalink raw reply related
* [PATCH v3 6/7] [ARM]: adds AB4500 as pl022 device
From: srinidhi kasagar @ 2009-10-11 22:28 UTC (permalink / raw)
To: linux-arm-kernel
From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
This adds AB4500 device support for the
mop500 board. AB4500 connects to U8500
on the SSP/SPI bus.
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
---
arch/arm/mach-ux500/board-mop500.c | 67 ++++++++++++++++++++++++++++++++++++
1 files changed, 67 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index fc02e9a..db5aa9e 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -14,6 +14,8 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/amba/bus.h>
+#include <linux/amba/pl022.h>
+#include <linux/spi/spi.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -43,10 +45,72 @@ static struct amba_device uart2_device = {
.irq = {IRQ_UART2, NO_IRQ},
};
+static void ab4500_spi_cs_control(u32 command)
+{
+ /* set the FRM signal, which is CS - TODO */
+}
+
+struct pl022_config_chip ab4500_chip_info = {
+ .lbm = LOOPBACK_DISABLED,
+ .com_mode = INTERRUPT_TRANSFER,
+ .iface = SSP_INTERFACE_MOTOROLA_SPI,
+ /* we can act as master only */
+ .hierarchy = SSP_MASTER,
+ .slave_tx_disable = 0,
+ .endian_rx = SSP_RX_MSB,
+ .endian_tx = SSP_TX_MSB,
+ .data_size = SSP_DATA_BITS_24,
+ .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
+ .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
+ .clk_phase = SSP_CLK_SECOND_EDGE,
+ .clk_pol = SSP_CLK_POL_IDLE_HIGH,
+ .cs_control = ab4500_spi_cs_control,
+};
+
+static struct spi_board_info u8500_spi_devices[] = {
+ {
+ .modalias = "ab4500",
+ .platform_data = NULL,
+ .controller_data = &ab4500_chip_info,
+ .max_speed_hz = 12000000,
+ .bus_num = 0,
+ .chip_select = 0,
+ .mode = SPI_MODE_0,
+ .irq = AB4500_IRQ,
+ },
+};
+
+static struct pl022_ssp_controller ssp0_platform_data = {
+ .bus_id = 0,
+ /* pl022 not yet supports dma */
+ .enable_dma = 0,
+ /* on this platform, gpio 31,142,144,214 &
+ * 224 are connected as chip selects
+ */
+ .num_chipselect = 5,
+};
+
+static struct amba_device pl022_device = {
+ .dev = {
+ .coherent_dma_mask = ~0,
+ .init_name = "pl022",
+ .platform_data = &ssp0_platform_data,
+ },
+ .res = {
+ .start = U8500_SSP0_BASE,
+ .end = U8500_SSP0_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_SSP0, NO_IRQ },
+ /* ST-Ericsson modified id */
+ .periphid = 0x01080022,
+};
+
static struct amba_device *amba_devs[] __initdata = {
&uart0_device,
&uart1_device,
&uart2_device,
+ &pl022_device,
};
/* add any platform devices here - TODO */
@@ -64,6 +128,9 @@ static void __init u8500_init_machine(void)
/* Register the platform devices */
platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
+ spi_register_board_info(u8500_spi_devices,
+ ARRAY_SIZE(u8500_spi_devices));
+
u8500_init_devices();
}
--
1.6.3.GIT
^ permalink raw reply related
* [Bug #14383] hackbench regression with kernel 2.6.32-rc1
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List
Cc: Kernel Testers List, Peter Zijlstra, Zhang, Yanmin
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14383
Subject : hackbench regression with kernel 2.6.32-rc1
Submitter : Zhang, Yanmin <yanmin_zhang@linux.intel.com>
Date : 2009-10-09 9:19 (3 days old)
First-Bad-Commit: http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=29cd8bae396583a2ee9a3340db8c5102acf9f6fd
References : http://marc.info/?l=linux-kernel&m=125508007510274&w=4
Handled-By : Peter Zijlstra <a.p.zijlstra@chello.nl>
^ permalink raw reply
* [PATCH v3 5/7] [ARM]: U8500 integrate to ARM architecture
From: srinidhi kasagar @ 2009-10-11 22:28 UTC (permalink / raw)
To: linux-arm-kernel
From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
This hooks the U8500 support into the ARM kbuild
system. This integration also enables SMP and its
helper funtions for u8500 platform
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
---
arch/arm/Kconfig | 19 +++++++++++++++----
arch/arm/Makefile | 1 +
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1c4119c..459f1ce 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -702,6 +702,15 @@ config ARCH_BCMRING
help
Support for Broadcom's BCMRing platform.
+config ARCH_U8500
+ bool "ST-Ericsson U8500 Series"
+ select ARM_AMBA
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select COMMON_CLKDEV
+ help
+ Include support for ST-Ericsson's Cortex-A9 Platform.
+
endchoice
source "arch/arm/mach-clps711x/Kconfig"
@@ -800,6 +809,8 @@ source "arch/arm/mach-msm/Kconfig"
source "arch/arm/mach-u300/Kconfig"
+source "arch/arm/mach-ux500/Kconfig"
+
source "arch/arm/mach-w90x900/Kconfig"
source "arch/arm/mach-bcmring/Kconfig"
@@ -955,10 +966,10 @@ source "kernel/time/Kconfig"
config SMP
bool "Symmetric Multi-Processing (EXPERIMENTAL)"
depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
- MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
+ MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
depends on GENERIC_CLOCKEVENTS
select USE_GENERIC_SMP_HELPERS
- select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4)
+ select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
help
This enables support for systems with more than one CPU. If you have
a system with only one CPU, like most personal computers, say N. If
@@ -1027,9 +1038,9 @@ config HOTPLUG_CPU
config LOCAL_TIMERS
bool "Use local timer interrupts"
depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
- REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
+ REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
default y
- select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4)
+ select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a73caaf..aef2404 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -166,6 +166,7 @@ machine-$(CONFIG_ARCH_SHARK) := shark
machine-$(CONFIG_ARCH_STMP378X) := stmp378x
machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx
machine-$(CONFIG_ARCH_U300) := u300
+machine-$(CONFIG_ARCH_U8500) := ux500
machine-$(CONFIG_ARCH_VERSATILE) := versatile
machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_FOOTBRIDGE) := footbridge
--
1.6.3.GIT
^ permalink raw reply related
* [PATCH v3 4/7] [ARM]: U8500 Makefile.boot
From: srinidhi kasagar @ 2009-10-11 22:27 UTC (permalink / raw)
To: linux-arm-kernel
From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
The Makefile.boot for the U8500 platform.
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
---
.../{mach-footbridge => mach-ux500}/Makefile.boot | 0
1 files changed, 0 insertions(+), 0 deletions(-)
copy arch/arm/{mach-footbridge => mach-ux500}/Makefile.boot (100%)
diff --git a/arch/arm/mach-footbridge/Makefile.boot b/arch/arm/mach-ux500/Makefile.boot
similarity index 100%
copy from arch/arm/mach-footbridge/Makefile.boot
copy to arch/arm/mach-ux500/Makefile.boot
--
1.6.3.GIT
^ permalink raw reply
* [Bug #14387] deadlock with fallocate
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List
Cc: Kernel Testers List, Andrew Morton, Christoph Hellwig,
Thomas Neumann
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14387
Subject : deadlock with fallocate
Submitter : Thomas Neumann <tneumann@users.sourceforge.net>
Date : 2009-10-07 3:00 (5 days old)
References : http://marc.info/?l=linux-kernel&m=125488495526471&w=4
Handled-By : Christoph Hellwig <hch@lst.de>
^ permalink raw reply
* [PATCH v3 3/7] [ARM]: U8500 core machine support
From: srinidhi kasagar @ 2009-10-11 22:27 UTC (permalink / raw)
To: linux-arm-kernel
From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
This adds core support for the ST-Ericsson U8500
platform. It supports memory mappings, binds to
the existing modules like GIC, SCU, TWD and local
timers, set up the infrastructure for the
secondary core, and adds MultiTimerUnit as system
timer with clocksource/clockevent support.
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
Reviewed-by: Alessandro Rubini <rubini@unipv.it>
Reviewed-by: Linus Walleij <linus.walleij@stericsson.com>
---
arch/arm/mach-ux500/Kconfig | 15 ++
arch/arm/mach-ux500/Makefile | 8 +
arch/arm/mach-ux500/board-mop500.c | 79 ++++++++++
arch/arm/mach-ux500/cpu-u8500.c | 78 ++++++++++
arch/arm/mach-ux500/headsmp.S | 38 +++++
arch/arm/mach-ux500/include/mach/debug-macro.S | 19 +++
arch/arm/mach-ux500/include/mach/entry-macro.S | 89 +++++++++++
arch/arm/mach-ux500/include/mach/memory.h | 18 +++
arch/arm/mach-ux500/include/mach/mtu.h | 53 +++++++
arch/arm/mach-ux500/include/mach/setup.h | 22 +++
arch/arm/mach-ux500/include/mach/smp.h | 32 ++++
arch/arm/mach-ux500/include/mach/system.h | 25 +++
arch/arm/mach-ux500/include/mach/timex.h | 6 +
arch/arm/mach-ux500/include/mach/uncompress.h | 58 ++++++++
arch/arm/mach-ux500/include/mach/vmalloc.h | 18 +++
arch/arm/mach-ux500/localtimer.c | 28 ++++
arch/arm/mach-ux500/platsmp.c | 186 ++++++++++++++++++++++++
arch/arm/mach-ux500/timer.c | 163 +++++++++++++++++++++
18 files changed, 935 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-ux500/Kconfig
create mode 100644 arch/arm/mach-ux500/Makefile
create mode 100644 arch/arm/mach-ux500/board-mop500.c
create mode 100644 arch/arm/mach-ux500/cpu-u8500.c
create mode 100644 arch/arm/mach-ux500/headsmp.S
create mode 100644 arch/arm/mach-ux500/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-ux500/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-ux500/include/mach/memory.h
create mode 100644 arch/arm/mach-ux500/include/mach/mtu.h
create mode 100644 arch/arm/mach-ux500/include/mach/setup.h
create mode 100644 arch/arm/mach-ux500/include/mach/smp.h
create mode 100644 arch/arm/mach-ux500/include/mach/system.h
create mode 100644 arch/arm/mach-ux500/include/mach/timex.h
create mode 100644 arch/arm/mach-ux500/include/mach/uncompress.h
create mode 100644 arch/arm/mach-ux500/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-ux500/localtimer.c
create mode 100644 arch/arm/mach-ux500/platsmp.c
create mode 100644 arch/arm/mach-ux500/timer.c
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
new file mode 100644
index 0000000..612b0b7
--- /dev/null
+++ b/arch/arm/mach-ux500/Kconfig
@@ -0,0 +1,15 @@
+menu "ST-Ericsson platform type"
+ depends on ARCH_U8500
+
+comment "ST-Ericsson Multicore Mobile Platforms"
+
+config MACH_U8500_MOP
+ bool "U8500 Development platform"
+ default y
+ select CPU_V7
+ select ARM_GIC
+ help
+ Include support for mop500 development platform
+ based on U8500 architecture. The platform is based
+ on early drop silicon version of 8500.
+endmenu
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
new file mode 100644
index 0000000..e71431c
--- /dev/null
+++ b/arch/arm/mach-ux500/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel, U8500 machine.
+#
+
+obj-y := clock.o timer.o
+obj-$(CONFIG_ARCH_U8500) += cpu-u8500.o
+obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
new file mode 100644
index 0000000..fc02e9a
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2008-2009 ST-Ericsson
+ *
+ * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/amba/bus.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/hardware.h>
+#include <mach/setup.h>
+
+#define __MEM_4K_RESOURCE(x) \
+ .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
+
+/* These are active devices on this board */
+static struct amba_device uart0_device = {
+ .dev = { .init_name = "uart0" },
+ __MEM_4K_RESOURCE(U8500_UART0_BASE),
+ .irq = {IRQ_UART0, NO_IRQ},
+};
+
+static struct amba_device uart1_device = {
+ .dev = { .init_name = "uart1" },
+ __MEM_4K_RESOURCE(U8500_UART1_BASE),
+ .irq = {IRQ_UART1, NO_IRQ},
+};
+
+static struct amba_device uart2_device = {
+ .dev = { .init_name = "uart2" },
+ __MEM_4K_RESOURCE(U8500_UART2_BASE),
+ .irq = {IRQ_UART2, NO_IRQ},
+};
+
+static struct amba_device *amba_devs[] __initdata = {
+ &uart0_device,
+ &uart1_device,
+ &uart2_device,
+};
+
+/* add any platform devices here - TODO */
+static struct platform_device *platform_devs[] __initdata = {
+ /* yet to be added, add i2c0, gpio.. */
+};
+
+static void __init u8500_init_machine(void)
+{
+ int i;
+ /* Register the active AMBA devices*/
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+ amba_device_register(amba_devs[i], &iomem_resource);
+
+ /* Register the platform devices */
+ platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
+
+ u8500_init_devices();
+}
+
+MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
+ /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */
+ .phys_io = U8500_UART2_BASE,
+ .io_pg_offst = (IO_ADDRESS(U8500_UART2_BASE) >> 18) & 0xfffc,
+ .boot_params = 0x100,
+ .map_io = u8500_map_io,
+ .init_irq = u8500_init_irq,
+ .timer = &u8500_timer,
+ .init_machine = u8500_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-ux500/cpu-u8500.c b/arch/arm/mach-ux500/cpu-u8500.c
new file mode 100644
index 0000000..7a5bc4f
--- /dev/null
+++ b/arch/arm/mach-ux500/cpu-u8500.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2008-2009 ST-Ericsson
+ *
+ * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/amba/bus.h>
+#include <linux/irq.h>
+
+#include <asm/hardware/gic.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+
+/* Minimum static i/o mapping required to boot U8500 platorms */
+static struct map_desc u8500_io_desc[] __initdata = {
+ {
+ .virtual = IO_ADDRESS(U8500_GIC_CPU_BASE),
+ .pfn = __phys_to_pfn(U8500_GIC_CPU_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = IO_ADDRESS(U8500_GIC_DIST_BASE),
+ .pfn = __phys_to_pfn(U8500_GIC_DIST_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = IO_ADDRESS(U8500_MTU0_BASE),
+ .pfn = __phys_to_pfn(U8500_MTU0_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = IO_ADDRESS(U8500_TWD_BASE),
+ .pfn = __phys_to_pfn(U8500_TWD_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = IO_ADDRESS(U8500_SCU_BASE),
+ .pfn = __phys_to_pfn(U8500_SCU_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = U8500_BACKUPRAM0_VA_BASE,
+ .pfn = __phys_to_pfn(U8500_BACKUPRAM0_BASE),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+ },
+};
+
+void __init u8500_map_io(void)
+{
+ iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
+}
+
+void __init u8500_init_irq(void)
+{
+ gic_dist_init(0, __io_address(U8500_GIC_DIST_BASE), 29);
+ gic_cpu_init(0, __io_address(U8500_GIC_CPU_BASE));
+}
+
+/*
+ * This function is called from the board init ("init_machine").
+ */
+void __init u8500_init_devices(void)
+{
+ return;
+}
diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S
new file mode 100644
index 0000000..a6be2cd
--- /dev/null
+++ b/arch/arm/mach-ux500/headsmp.S
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2009 ST-Ericsson
+ * This file is based ARM Realview platform
+ * Copyright (c) 2003 ARM Limited
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ __INIT
+
+/*
+ * U8500 specific entry point for secondary CPUs.
+ */
+ENTRY(u8500_secondary_startup)
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #15
+ adr r4, 1f
+ ldmia r4, {r5, r6}
+ sub r4, r4, r5
+ add r6, r6, r4
+ dsb
+pen: ldr r7, [r6]
+ cmp r7, r0
+ bne pen
+
+ /*
+ * we've been released from the holding pen: secondary_stack
+ * should now contain the SVC stack for this core
+ */
+ b secondary_startup
+
+1: .long .
+ .long pen_release
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
new file mode 100644
index 0000000..8f21b6a
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -0,0 +1,19 @@
+/*
+ * Debugging macro include header
+ *
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+ .macro addruart,rx
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1 @MMU enabled?
+ moveq \rx, #0x80000000 @MMU off, Physical address
+ movne \rx, #0xF0000000 @MMU on, Virtual address
+ orr \rx, \rx, #0x7000
+ .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
new file mode 100644
index 0000000..eece330
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -0,0 +1,89 @@
+/*
+ * Low-level IRQ helper macros for U8500 platforms
+ *
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * This file is a copy of ARM Realview platform.
+ * -just satisfied checkpatch script.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ ldr \base, =IO_ADDRESS(U8500_GIC_CPU_BASE)
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ /*
+ * The interrupt numbering scheme is defined in the
+ * interrupt controller spec. To wit:
+ *
+ * Interrupts 0-15 are IPI
+ * 16-28 are reserved
+ * 29-31 are local. We allow 30 to be used for the watchdog.
+ * 32-1020 are global
+ * 1021-1022 are reserved
+ * 1023 is "spurious" (no interrupt)
+ *
+ * For now, we ignore all local interrupts so only return an
+ * interrupt if it's between 30 and 1020. The test_for_ipi
+ * routine below will pick up on IPIs.
+ *
+ * A simple read from the controller will tell us the number
+ * of the highest priority enabled interrupt. We then just
+ * need to check whether it is in the valid range for an
+ * IRQ (30-1020 inclusive).
+ */
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+ /* bits 12-10 = src CPU, 9-0 = int # */
+ ldr \irqstat, [\base, #GIC_CPU_INTACK]
+
+ ldr \tmp, =1021
+
+ bic \irqnr, \irqstat, #0x1c00
+
+ cmp \irqnr, #29
+ cmpcc \irqnr, \irqnr
+ cmpne \irqnr, \tmp
+ cmpcs \irqnr, \irqnr
+
+ .endm
+
+ /* We assume that irqstat (the raw value of the IRQ
+ * acknowledge register) is preserved from the macro above.
+ * If there is an IPI, we immediately signal end of
+ * interrupt on the controller, since this requires the
+ * original irqstat value which we won't easily be able
+ * to recreate later.
+ */
+
+ .macro test_for_ipi, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ cmp \irqnr, #16
+ strcc \irqstat, [\base, #GIC_CPU_EOI]
+ cmpcs \irqnr, \irqnr
+ .endm
+
+ /* As above, this assumes that irqstat and base
+ * are preserved..
+ */
+
+ .macro test_for_ltirq, irqnr, irqstat, base, tmp
+ bic \irqnr, \irqstat, #0x1c00
+ mov \tmp, #0
+ cmp \irqnr, #29
+ moveq \tmp, #1
+ streq \irqstat, [\base, #GIC_CPU_EOI]
+ cmp \tmp, #0
+ .endm
diff --git a/arch/arm/mach-ux500/include/mach/memory.h b/arch/arm/mach-ux500/include/mach/memory.h
new file mode 100644
index 0000000..510571a
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/memory.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET UL(0x00000000)
+#define BUS_OFFSET UL(0x00000000)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/mtu.h b/arch/arm/mach-ux500/include/mach/mtu.h
new file mode 100644
index 0000000..32380be
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mtu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ * MultiTimerUnit register definitions, copied from Nomadik 8815
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __ASM_ARCH_MTU_H
+#define __ASM_ARCH_MTU_H
+
+/*
+ * The MTU device hosts four different counters, with 4 set of
+ * registers. These are register names.
+ */
+
+#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
+#define MTU_RIS 0x04 /* Raw interrupt status */
+#define MTU_MIS 0x08 /* Masked interrupt status */
+#define MTU_ICR 0x0C /* Interrupt clear register */
+
+/* per-timer registers take 0..3 as argument */
+#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
+#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
+#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
+#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
+
+/* bits for the control register */
+#define MTU_CRn_ENA 0x80
+#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
+#define MTU_CRn_PRESCALE_MASK 0x0c
+#define MTU_CRn_PRESCALE_1 0x00
+#define MTU_CRn_PRESCALE_16 0x04
+#define MTU_CRn_PRESCALE_256 0x08
+#define MTU_CRn_32BITS 0x02
+#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
+
+/* Other registers are usual amba/primecell registers, currently not used */
+#define MTU_ITCR 0xff0
+#define MTU_ITOP 0xff4
+
+#define MTU_PERIPH_ID0 0xfe0
+#define MTU_PERIPH_ID1 0xfe4
+#define MTU_PERIPH_ID2 0xfe8
+#define MTU_PERIPH_ID3 0xfeC
+
+#define MTU_PCELL0 0xff0
+#define MTU_PCELL1 0xff4
+#define MTU_PCELL2 0xff8
+#define MTU_PCELL3 0xffC
+
+#endif /* __ASM_ARCH_MTU_H */
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
new file mode 100644
index 0000000..0807e4f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * These symbols are needed for board-specific files to call their
+ * own cpu-specific files
+ */
+#ifndef __ASM_ARCH_SETUP_H
+#define __ASM_ARCH_SETUP_H
+
+#include <asm/mach/time.h>
+#include <linux/init.h>
+
+extern void u8500_map_io(void);
+extern void u8500_init_devices(void);
+extern void u8500_init_irq(void);
+extern struct sys_timer u8500_timer;
+
+#endif /* __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
new file mode 100644
index 0000000..b59f7bc
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -0,0 +1,32 @@
+/*
+ * This file is based ARM realview platform.
+ * Copyright (C) ARM Limited.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef ASMARM_ARCH_SMP_H
+#define ASMARM_ARCH_SMP_H
+
+#include <asm/hardware/gic.h>
+
+/* This is required to wakeup the secondary core */
+extern void u8500_secondary_startup(void);
+
+#define hard_smp_processor_id() \
+ ({ \
+ unsigned int cpunum; \
+ __asm__("mrc p15, 0, %0, c0, c0, 5" \
+ : "=r" (cpunum)); \
+ cpunum &= 0x0F; \
+ })
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(const struct cpumask *mask)
+{
+ gic_raise_softirq(mask, 1);
+}
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/system.h b/arch/arm/mach-ux500/include/mach/system.h
new file mode 100644
index 0000000..c0cd800
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/system.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks
+ */
+ cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+ /* yet to be implemented - TODO */
+}
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/timex.h b/arch/arm/mach-ux500/include/mach/timex.h
new file mode 100644
index 0000000..d0942c1
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/timex.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#define CLOCK_TICK_RATE 110000000
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
new file mode 100644
index 0000000..8552eb1
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <asm/setup.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+
+#define U8500_UART_DR 0x80007000
+#define U8500_UART_LCRH 0x8000702c
+#define U8500_UART_CR 0x80007030
+#define U8500_UART_FR 0x80007018
+
+static void putc(const char c)
+{
+ /* Do nothing if the UART is not enabled. */
+ if (!(readb(U8500_UART_CR) & 0x1))
+ return;
+
+ if (c == '\n')
+ putc('\r');
+
+ while (readb(U8500_UART_FR) & (1 << 5))
+ barrier();
+ writeb(c, U8500_UART_DR);
+}
+
+static void flush(void)
+{
+ if (!(readb(U8500_UART_CR) & 0x1))
+ return;
+ while (readb(U8500_UART_FR) & (1 << 3))
+ barrier();
+}
+
+static inline void arch_decomp_setup(void)
+{
+}
+
+#define arch_decomp_wdog() /* nothing to do here */
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-ux500/include/mach/vmalloc.h b/arch/arm/mach-ux500/include/mach/vmalloc.h
new file mode 100644
index 0000000..86cdbbc
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/vmalloc.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#define VMALLOC_END 0xf0000000
diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c
new file mode 100644
index 0000000..2288f6a
--- /dev/null
+++ b/arch/arm/mach-ux500/localtimer.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2008-2009 ST-Ericsson
+ * Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
+ *
+ * This file is heavily based on relaview platform, almost a copy.
+ *
+ * Copyright (C) 2002 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+
+#include <asm/irq.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+
+/*
+ * Setup the local clock events for a CPU.
+ */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+ evt->irq = IRQ_LOCALTIMER;
+ twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
new file mode 100644
index 0000000..54daec1
--- /dev/null
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2002 ARM Ltd.
+ * Copyright (C) 2008 STMicroelctronics.
+ * Copyright (C) 2009 ST-Ericsson.
+ * added support to boot from non volatile memory device
+ * Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
+ *
+ * This file is based on arm realview platform
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+#include <asm/localtimer.h>
+#include <asm/smp_scu.h>
+#include <mach/hardware.h>
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+
+static unsigned int __init get_core_count(void)
+{
+ return scu_get_core_count(__io_address(U8500_SCU_BASE));
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+ trace_hardirqs_off();
+
+ /*
+ * if any interrupts are already enabled for the primary
+ * core (e.g. timer irq), then they will not have been enabled
+ * for us: do so
+ */
+ gic_cpu_init(0, __io_address(U8500_GIC_CPU_BASE));
+
+ /*
+ * let the primary processor know we're out of the
+ * pen, then head off into the C entry point
+ */
+ pen_release = -1;
+
+ /* make sure write buffer is drained */
+ smp_wmb();
+
+ /*
+ * Synchronise with the boot thread.
+ */
+ spin_lock(&boot_lock);
+ spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ unsigned long timeout;
+
+ /*
+ * set synchronisation state between this boot processor
+ * and the secondary one
+ */
+ spin_lock(&boot_lock);
+
+ /*
+ * The secondary processor is waiting to be released from
+ * the holding pen - release it, then wait for it to flag
+ * that it has been released by resetting pen_release.
+ */
+ pen_release = cpu;
+ flush_cache_all();
+
+ smp_cross_call(cpumask_of(cpu));
+
+ timeout = jiffies + (1 * HZ);
+ while (time_before(jiffies, timeout)) {
+ smp_rmb();
+ if (pen_release == -1)
+ break;
+
+ udelay(10);
+ }
+
+ /*
+ * now the secondary core is starting up let it run its
+ * calibrations, then wait for it to finish
+ */
+ spin_unlock(&boot_lock);
+
+ return pen_release != -1 ? -ENOSYS : 0;
+}
+
+static void __init wakeup_secondary(void)
+{
+ /* nobody is to be released from the pen yet */
+ pen_release = -1;
+
+ /*
+ * write the address of secondary startup into the backup ram register
+ * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
+ * backup ram register at offset 0x1FF0, which is what boot rom code
+ * is waiting for. This would wake up the secondary core from WFE
+ */
+#define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4
+ __raw_writel(virt_to_phys(u8500_secondary_startup),
+ (void __iomem *)U8500_BACKUPRAM0_VA_BASE +
+ U8500_CPU1_JUMPADDR_OFFSET);
+
+#define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
+ __raw_writel(0xA1FEED01,
+ (void __iomem *)U8500_BACKUPRAM0_VA_BASE +
+ U8500_CPU1_WAKEMAGIC_OFFSET);
+
+ /* make sure write buffer is drained */
+ mb();
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+ unsigned int i, ncores = get_core_count();
+
+ for (i = 0; i < ncores; i++)
+ set_cpu_possible(i, true);
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+ unsigned int ncores = get_core_count();
+ unsigned int cpu = smp_processor_id();
+ int i;
+
+ /* sanity check */
+ if (ncores == 0) {
+ printk(KERN_ERR
+ "U8500: strange CM count of 0? Default to 1\n");
+ ncores = 1;
+ }
+
+ if (ncores > num_possible_cpus()) {
+ printk(KERN_WARNING
+ "U8500: no. of cores (%d) greater than configured "
+ "maximum of %d - clipping\n",
+ ncores, num_possible_cpus());
+ ncores = num_possible_cpus();
+ }
+
+ smp_store_cpu_info(cpu);
+
+ /*
+ * are we trying to boot more cores than exist?
+ */
+ if (max_cpus > ncores)
+ max_cpus = ncores;
+
+ /*
+ * Initialise the present map, which describes the set of CPUs
+ * actually populated at the present time.
+ */
+ for (i = 0; i < max_cpus; i++)
+ set_cpu_present(i, true);
+
+ if (max_cpus > 1) {
+ /*
+ * Enable the local timer or broadcast device for the
+ * boot CPU, but only if we have more than one CPU.
+ */
+ percpu_timer_setup();
+ scu_enable(__io_address(U8500_SCU_BASE));
+ wakeup_secondary();
+ }
+}
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
new file mode 100644
index 0000000..b97c0ba
--- /dev/null
+++ b/arch/arm/mach-ux500/timer.c
@@ -0,0 +1,163 @@
+/*
+ * linux/arch/arm/mach-u8500/timer.c
+ *
+ * Copyright (C) 2008 STMicroelectronics
+ * Copyright (C) 2009 Alessandro Rubini
+ * Copyright (C) 2009 ST-Ericsson.
+ * Adapted to u8500 platform, heavily based on 8815
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/clockchips.h>
+#include <linux/jiffies.h>
+#include <asm/mach/time.h>
+#include <asm/localtimer.h>
+#include <mach/mtu.h>
+
+static u32 u8500_count; /* accumulated count */
+static u32 u8500_cycle; /* write-once */
+static __iomem void *mtu_base;
+
+/*
+ * clocksource: the MTU device is a decrementing counters, so we negate
+ * the value being read.
+ */
+static cycle_t u8500_read_timer(struct clocksource *cs)
+{
+ u32 count = readl(mtu_base + MTU_VAL(0));
+ return u8500_count + u8500_cycle - count;
+}
+
+static struct clocksource u8500_clksrc = {
+ .name = "mtu_0",
+ .rating = 400,
+ .read = u8500_read_timer,
+ .shift = 20,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+/*
+ * Clockevent device: currently only periodic mode is supported
+ */
+static void u8500_clkevt_mode(enum clock_event_mode mode,
+ struct clock_event_device *dev)
+{
+ unsigned long flags;
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ /* enable interrupts -- and count current value? */
+ raw_local_irq_save(flags);
+ writel(readl(mtu_base + MTU_IMSC) | 1, mtu_base + MTU_IMSC);
+ raw_local_irq_restore(flags);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ BUG(); /* Not yet supported */
+ /* FALLTHROUGH */
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ case CLOCK_EVT_MODE_UNUSED:
+ /* disable irq */
+ raw_local_irq_save(flags);
+ writel(readl(mtu_base + MTU_IMSC) & ~1, mtu_base + MTU_IMSC);
+ raw_local_irq_restore(flags);
+ break;
+ case CLOCK_EVT_MODE_RESUME:
+ break;
+ }
+}
+
+static struct clock_event_device u8500_clkevt = {
+ .name = "mtu_0",
+ .features = CLOCK_EVT_FEAT_PERIODIC,
+ .shift = 32,
+ .rating = 400,
+ .set_mode = u8500_clkevt_mode,
+};
+
+/*
+ * IRQ Handler for the timer 0 of the MTU block. The irq is not shared
+ * as we are the only users of mtu0 by now.
+ */
+static irqreturn_t u8500_timer_interrupt(int irq, void *dev_id)
+{
+ /* ack: "interrupt clear register" */
+ writel(1 << 0, mtu_base + MTU_ICR);
+
+ /* we can't count lost ticks, unfortunately */
+ u8500_count += u8500_cycle;
+ u8500_clkevt.event_handler(&u8500_clkevt);
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+static struct irqaction u8500_timer_irq = {
+ .name = "U8500 Timer Tick",
+ .flags = IRQF_DISABLED | IRQF_TIMER,
+ .handler = u8500_timer_interrupt,
+};
+
+static void u8500_timer_reset(void)
+{
+ u32 cr;
+
+ writel(0, mtu_base + MTU_CR(0)); /* off */
+
+ /* configure load and background-load, and fire it up */
+ writel(u8500_cycle, mtu_base + MTU_LR(0));
+ writel(u8500_cycle, mtu_base + MTU_BGLR(0));
+ cr = MTU_CRn_PERIODIC | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS;
+ writel(cr, mtu_base + MTU_CR(0));
+ writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
+}
+
+static void __init u8500_timer_init(void)
+{
+ unsigned long rate;
+ int bits;
+
+#ifdef CONFIG_LOCAL_TIMERS
+ twd_base = __io_address(U8500_TWD_BASE);
+#endif
+ rate = CLOCK_TICK_RATE; /* 2.4MHz */
+ u8500_cycle = (rate + HZ/2) / HZ;
+
+ /* Save global pointer to mtu, used by functions above */
+ mtu_base = __io_address(U8500_MTU0_BASE);
+
+ /* Init the timer and register clocksource */
+ u8500_timer_reset();
+
+ u8500_clksrc.mult = clocksource_hz2mult(rate, u8500_clksrc.shift);
+ bits = 8*sizeof(u8500_count);
+ u8500_clksrc.mask = CLOCKSOURCE_MASK(bits);
+
+ if (clocksource_register(&u8500_clksrc))
+ printk(KERN_ERR "u8500 timer: failed to initialize clock "
+ "source %s\n", u8500_clksrc.name);
+
+ /* Register irq and clockevents */
+ setup_irq(IRQ_MTU0, &u8500_timer_irq);
+ u8500_clkevt.mult = div_sc(rate, NSEC_PER_SEC, u8500_clkevt.shift);
+ u8500_clkevt.cpumask = cpumask_of(0);
+ clockevents_register_device(&u8500_clkevt);
+}
+
+static void u8500_timer_suspend(void)
+{
+ /* not supported yet */
+}
+
+struct sys_timer u8500_timer = {
+ .init = u8500_timer_init,
+ .suspend = u8500_timer_suspend,
+ .resume = u8500_timer_reset,
+};
--
1.6.3.GIT
^ permalink raw reply related
* [Bug #14378] Problems with net/core/skbuff.c
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List; +Cc: Kernel Testers List, Massimo Cetra
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14378
Subject : Problems with net/core/skbuff.c
Submitter : Massimo Cetra <mcetra@navynet.it>
Date : 2009-10-08 14:51 (4 days old)
References : http://marc.info/?l=linux-kernel&m=125501488220358&w=4
^ permalink raw reply
* [PATCH v3 2/7] [ARM]: U8500 clock framework
From: srinidhi kasagar @ 2009-10-11 22:27 UTC (permalink / raw)
To: linux-arm-kernel
From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
This adds basic clock framework to the U8500 platform.
At the moment it just uses the clock lookup table
and add the each entry to the clkdevice. More complex
clock management to follow soon.
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
---
arch/arm/mach-ux500/clock.c | 95 ++++++++++++++++++++
.../include/mach/clkdev.h | 0
2 files changed, 95 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-ux500/clock.c
copy arch/arm/{mach-bcmring => mach-ux500}/include/mach/clkdev.h (100%)
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
new file mode 100644
index 0000000..20b6ebb
--- /dev/null
+++ b/arch/arm/mach-ux500/clock.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ * heavily based on realview platform
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+
+#include <asm/clkdev.h>
+
+/* currently the clk structure
+ * just supports rate. This would
+ * be extended as and when new devices are
+ * added - TODO
+ */
+struct clk {
+ unsigned long rate;
+};
+
+int clk_enable(struct clk *clk)
+{
+ return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+ /*TODO*/
+ return rate;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ clk->rate = rate;
+ return 0;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+/* ssp clock */
+static struct clk ssp_clk = {
+ .rate = 48000000,
+};
+
+/* fixed clock */
+static struct clk f38_clk = {
+ .rate = 38400000,
+};
+
+static struct clk_lookup lookups[] = {
+ {
+ /* UART0 */
+ .dev_id = "uart0",
+ .clk = &f38_clk,
+ }, { /* UART1 */
+ .dev_id = "uart1",
+ .clk = &f38_clk,
+ }, { /* UART2 */
+ .dev_id = "uart2",
+ .clk = &f38_clk,
+ }, { /* SSP */
+ .dev_id = "pl022",
+ .clk = &ssp_clk,
+ }
+};
+
+static int __init clk_init(void)
+{
+ int i;
+
+ /* register the clock lookups */
+ for (i = 0; i < ARRAY_SIZE(lookups); i++)
+ clkdev_add(&lookups[i]);
+ return 0;
+}
+arch_initcall(clk_init);
diff --git a/arch/arm/mach-bcmring/include/mach/clkdev.h b/arch/arm/mach-ux500/include/mach/clkdev.h
similarity index 100%
copy from arch/arm/mach-bcmring/include/mach/clkdev.h
copy to arch/arm/mach-ux500/include/mach/clkdev.h
--
1.6.3.GIT
^ permalink raw reply related
* [PATCH v3 1/7] [ARM]: U8500 register definitions
From: srinidhi kasagar @ 2009-10-11 22:27 UTC (permalink / raw)
To: linux-arm-kernel
From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
This adds registers, shared peripheral interrupt numbers
and IO mappings for the U8500 platform core support.
Shared peripheral interrupts (SPI) are assigned to
[160:32], wherein first 32 interrupts are reserved.
Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
Reviewed-by: Alessandro Rubini <rubini@unipv.it>
---
arch/arm/mach-ux500/include/mach/hardware.h | 129 +++++++++++++++++++++++++++
arch/arm/mach-ux500/include/mach/io.h | 22 +++++
arch/arm/mach-ux500/include/mach/irqs.h | 71 +++++++++++++++
3 files changed, 222 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-ux500/include/mach/hardware.h
create mode 100644 arch/arm/mach-ux500/include/mach/io.h
create mode 100644 arch/arm/mach-ux500/include/mach/irqs.h
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
new file mode 100644
index 0000000..23fec82
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * U8500 hardware definitions
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* macros to get at IO space when running virtually
+ * We dont map all the peripherals, let ioremap do
+ * this for us. We map only very basic peripherals here.
+ */
+#define U8500_IO_VIRTUAL 0xf0000000
+#define U8500_IO_PHYSICAL 0xa0000000
+
+/* this macro is used in assembly, so no cast */
+#define IO_ADDRESS(x) ((x) - U8500_IO_PHYSICAL + U8500_IO_VIRTUAL)
+
+/* typesafe io address */
+#define __io_address(n) __io(IO_ADDRESS(n))
+
+/*
+ * Base address definitions for U8500 Onchip IPs. All the
+ * peripherals are contained in a single 1 Mbyte region, with
+ * AHB peripherals at the bottom and APB peripherals at the
+ * top of the region. PER stands for PERIPHERAL region which
+ * itself divided into sub regions.
+ */
+#define U8500_PER3_BASE 0x80000000
+#define U8500_PER2_BASE 0x80110000
+#define U8500_PER1_BASE 0x80120000
+#define U8500_PER4_BASE 0x80150000
+
+#define U8500_PER6_BASE 0xa03c0000
+#define U8500_PER5_BASE 0xa03e0000
+#define U8500_PER7_BASE 0xa03d0000
+
+#define U8500_SVA_BASE 0xa0100000
+#define U8500_SIA_BASE 0xa0200000
+
+#define U8500_SGA_BASE 0xa0300000
+#define U8500_MCDE_BASE 0xa0350000
+#define U8500_DMA_BASE 0xa0362000
+
+#define U8500_SCU_BASE 0xa0410000
+#define U8500_GIC_CPU_BASE 0xa0410100
+#define U8500_TWD_BASE 0xa0410600
+#define U8500_GIC_DIST_BASE 0xa0411000
+#define U8500_L2CC_BASE 0xa0412000
+
+#define U8500_TWD_SIZE 0x100
+
+/* per7 base addressess */
+#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000)
+#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000)
+#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000)
+#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000)
+#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
+
+/* per6 base addressess */
+#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
+#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
+#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
+#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
+#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
+#define U8500_CLKRST6_BASE (U8500_PER7_BASE + 0xf000)
+
+/* per5 base addressess */
+#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
+#define U8500_GPIO5_BASE (U8500_PER5_BASE + 0x1e000)
+#define U8500_CLKRST5_BASE (U8500_PER7_BASE + 0x1f000)
+
+/* per4 base addressess */
+#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x0000)
+#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x1000)
+#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x2000)
+#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x3000)
+#define U8500_RTC_BASE (U8500_PER4_BASE + 0x4000)
+#define U8500_SCR_BASE (U8500_PER4_BASE + 0x5000)
+#define U8500_DMC_BASE (U8500_PER4_BASE + 0x6000)
+#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x7000)
+
+/* per3 base addressess */
+#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
+#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
+#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
+#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
+#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
+#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
+#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
+#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
+#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xe000)
+#define U8500_CLKRST3_BASE (U8500_PER7_BASE + 0xf000)
+
+/* per2 base addressess */
+#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
+#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
+#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
+#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
+#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
+#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
+#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
+#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
+#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
+#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
+#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
+#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xe000)
+#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
+
+/* per1 base addresses */
+#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
+#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
+#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
+#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
+#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
+#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
+#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
+#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
+#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xa000)
+#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000)
+#define U8500_CLKRST1_BASE (U8500_PER2_BASE + 0xf000)
+
+#define U8500_BACKUPRAM0_VA_BASE 0xf0413000
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h
new file mode 100644
index 0000000..1cf3f44
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/io.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-u8500/include/mach/io.h
+ *
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Modifications:
+ * 06-12-1997 RMK Created.
+ * 07-04-1999 RMK Major cleanup
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a) __typesafe_io(a)
+#define __mem_pci(a) (a)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
new file mode 100644
index 0000000..69d6dde
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2008 STMicroelectronics
+ * Copyright (C) 2009 ST-Ericsson.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef ASM_ARCH_IRQS_H
+#define ASM_ARCH_IRQS_H
+
+#include <mach/hardware.h>
+
+#define IRQ_LOCALTIMER 29
+#define IRQ_LOCALWDOG 30
+
+/* Shared Peripheral Interrupt */
+#define IRQ_SPI_START 32
+
+/* Interrupt numbers generic for shared peripheral */
+#define IRQ_MTU0 (IRQ_SPI_START + 4)
+#define IRQ_SPI2 (IRQ_SPI_START + 6)
+#define IRQ_SPI0 (IRQ_SPI_START + 8)
+#define IRQ_UART0 (IRQ_SPI_START + 11)
+#define IRQ_I2C3 (IRQ_SPI_START + 12)
+#define IRQ_SSP0 (IRQ_SPI_START + 14)
+#define IRQ_MTU1 (IRQ_SPI_START + 17)
+#define IRQ_RTC_RTT (IRQ_SPI_START + 18)
+#define IRQ_UART1 (IRQ_SPI_START + 19)
+#define IRQ_I2C0 (IRQ_SPI_START + 21)
+#define IRQ_I2C1 (IRQ_SPI_START + 22)
+#define IRQ_USBOTG (IRQ_SPI_START + 23)
+#define IRQ_DMA (IRQ_SPI_START + 25)
+#define IRQ_UART2 (IRQ_SPI_START + 26)
+#define IRQ_HSIR_EXCEP (IRQ_SPI_START + 29)
+#define IRQ_MSP0 (IRQ_SPI_START + 31)
+#define IRQ_HSIR_CH0_OVRRUN (IRQ_SPI_START + 32)
+#define IRQ_HSIR_CH1_OVRRUN (IRQ_SPI_START + 33)
+#define IRQ_HSIR_CH2_OVRRUN (IRQ_SPI_START + 34)
+#define IRQ_HSIR_CH3_OVRRUN (IRQ_SPI_START + 35)
+#define AB4500_IRQ (IRQ_SPI_START + 40)
+#define IRQ_DISP (IRQ_SPI_START + 48)
+#define IRQ_SPI3 (IRQ_SPI_START + 49)
+#define IRQ_SSP1 (IRQ_SPI_START + 52)
+#define IRQ_I2C2 (IRQ_SPI_START + 55)
+#define IRQ_SDMMC0 (IRQ_SPI_START + 60)
+#define IRQ_MSP1 (IRQ_SPI_START + 62)
+#define IRQ_SPI1 (IRQ_SPI_START + 96)
+#define IRQ_MSP2 (IRQ_SPI_START + 98)
+#define IRQ_SDMMC4 (IRQ_SPI_START + 99)
+#define IRQ_HSIRD0 (IRQ_SPI_START + 104)
+#define IRQ_HSIRD1 (IRQ_SPI_START + 105)
+#define IRQ_HSITD0 (IRQ_SPI_START + 106)
+#define IRQ_HSITD1 (IRQ_SPI_START + 107)
+#define IRQ_GPIO0 (IRQ_SPI_START + 119)
+#define IRQ_GPIO1 (IRQ_SPI_START + 120)
+#define IRQ_GPIO2 (IRQ_SPI_START + 121)
+#define IRQ_GPIO3 (IRQ_SPI_START + 122)
+#define IRQ_GPIO4 (IRQ_SPI_START + 123)
+#define IRQ_GPIO5 (IRQ_SPI_START + 124)
+#define IRQ_GPIO6 (IRQ_SPI_START + 125)
+#define IRQ_GPIO7 (IRQ_SPI_START + 126)
+#define IRQ_GPIO8 (IRQ_SPI_START + 127)
+
+/* There are 128 shared peripheral interrupts assigned to
+ * INTID[160:32]. The first 32 interrupts are reserved.
+ */
+#define NR_IRQS 161
+
+#endif /*ASM_ARCH_IRQS_H*/
--
1.6.3.GIT
^ permalink raw reply related
* [PATCH v3 0/8] [ARM] ST-Ericsson's U8500 SMP platform, a new patch set
From: srinidhi kasagar @ 2009-10-11 22:26 UTC (permalink / raw)
To: linux-arm-kernel
From: srinidhi kasagar <srinidhi.kasagar@stericsson.com>
This adds a new machine support for ST-Ericsson's U8500 platform. This is
an entry level patch which has bindings to existing modules like GIC, SCU,
TWD, PL011 UART. This also adds a new SPI device AB4500 (odler name STW4500)
which uses ARM pl022 bus driver.
There are similarly numbered platforms will appear in the near future bearing
ux500 naming scheme, and hence this patch set has this name for the first
U8500 platform. This is v3 patch re-based to linux-2.6.32-rc3, and fixed most
of the review comments. For the patch 7/7 to work on hardware, get the
patch 5741 from Russell's patch tracking system.
srinidhi kasagar (7):
[ARM]: U8500 register definitions
[ARM]: U8500 clock framework
[ARM]: U8500 core machine support
[ARM]: U8500 Makefile.boot
[ARM]: U8500 integrate to ARM architecture
[ARM]: adds AB4500 as pl022 device
mfd: add AB4500 SPI used in U8500
arch/arm/Kconfig | 19 ++-
arch/arm/Makefile | 1 +
arch/arm/mach-ux500/Kconfig | 15 ++
arch/arm/mach-ux500/Makefile | 8 +
.../{mach-footbridge => mach-ux500}/Makefile.boot | 0
arch/arm/mach-ux500/board-mop500.c | 146 +++++++++++
arch/arm/mach-ux500/clock.c | 95 +++++++
arch/arm/mach-ux500/cpu-u8500.c | 78 ++++++
arch/arm/mach-ux500/headsmp.S | 38 +++
.../include/mach/clkdev.h | 0
arch/arm/mach-ux500/include/mach/debug-macro.S | 19 ++
arch/arm/mach-ux500/include/mach/entry-macro.S | 89 +++++++
arch/arm/mach-ux500/include/mach/hardware.h | 129 ++++++++++
arch/arm/mach-ux500/include/mach/io.h | 22 ++
arch/arm/mach-ux500/include/mach/irqs.h | 71 ++++++
arch/arm/mach-ux500/include/mach/memory.h | 18 ++
arch/arm/mach-ux500/include/mach/mtu.h | 53 ++++
arch/arm/mach-ux500/include/mach/setup.h | 22 ++
arch/arm/mach-ux500/include/mach/smp.h | 32 +++
arch/arm/mach-ux500/include/mach/system.h | 25 ++
arch/arm/mach-ux500/include/mach/timex.h | 6 +
arch/arm/mach-ux500/include/mach/uncompress.h | 58 +++++
arch/arm/mach-ux500/include/mach/vmalloc.h | 18 ++
arch/arm/mach-ux500/localtimer.c | 28 ++
arch/arm/mach-ux500/platsmp.c | 186 ++++++++++++++
arch/arm/mach-ux500/timer.c | 163 ++++++++++++
drivers/mfd/Kconfig | 10 +
drivers/mfd/Makefile | 1 +
drivers/mfd/ab4500-core.c | 207 +++++++++++++++
include/linux/mfd/ab4500.h | 262 ++++++++++++++++++++
30 files changed, 1815 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-ux500/Kconfig
create mode 100644 arch/arm/mach-ux500/Makefile
copy arch/arm/{mach-footbridge => mach-ux500}/Makefile.boot (100%)
create mode 100644 arch/arm/mach-ux500/board-mop500.c
create mode 100644 arch/arm/mach-ux500/clock.c
create mode 100644 arch/arm/mach-ux500/cpu-u8500.c
create mode 100644 arch/arm/mach-ux500/headsmp.S
copy arch/arm/{mach-bcmring => mach-ux500}/include/mach/clkdev.h (100%)
create mode 100644 arch/arm/mach-ux500/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-ux500/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-ux500/include/mach/hardware.h
create mode 100644 arch/arm/mach-ux500/include/mach/io.h
create mode 100644 arch/arm/mach-ux500/include/mach/irqs.h
create mode 100644 arch/arm/mach-ux500/include/mach/memory.h
create mode 100644 arch/arm/mach-ux500/include/mach/mtu.h
create mode 100644 arch/arm/mach-ux500/include/mach/setup.h
create mode 100644 arch/arm/mach-ux500/include/mach/smp.h
create mode 100644 arch/arm/mach-ux500/include/mach/system.h
create mode 100644 arch/arm/mach-ux500/include/mach/timex.h
create mode 100644 arch/arm/mach-ux500/include/mach/uncompress.h
create mode 100644 arch/arm/mach-ux500/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-ux500/localtimer.c
create mode 100644 arch/arm/mach-ux500/platsmp.c
create mode 100644 arch/arm/mach-ux500/timer.c
create mode 100755 drivers/mfd/ab4500-core.c
create mode 100644 include/linux/mfd/ab4500.h
^ permalink raw reply
* [Bug #14392] Touchpad "paste" stops working after suspend to RAM
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List
Cc: Kernel Testers List, Carlos R. Mafra, Dmitry Torokhov
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14392
Subject : Touchpad "paste" stops working after suspend to RAM
Submitter : Carlos R. Mafra <crmafra2@gmail.com>
Date : 2009-10-11 16:21 (1 days old)
References : http://marc.info/?l=linux-kernel&m=125527987316493&w=4
Handled-By : Dmitry Torokhov <dmitry.torokhov@gmail.com>
^ permalink raw reply
* [Bug #14386] GPF in snd_hda_intel
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List; +Cc: Kernel Testers List, Luca Tettamanti
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14386
Subject : GPF in snd_hda_intel
Submitter : Luca Tettamanti <kronos.it@gmail.com>
Date : 2009-10-10 13:01 (2 days old)
References : http://marc.info/?l=linux-kernel&m=125517999408019&w=4
^ permalink raw reply
* [Bug #14382] Transmit failure in et131x.
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List; +Cc: Kernel Testers List, Alan Cox, Nick Bowler
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14382
Subject : Transmit failure in et131x.
Submitter : Nick Bowler <nbowler@elliptictech.com>
Date : 2009-10-08 14:08 (4 days old)
References : http://marc.info/?l=linux-kernel&m=125501117713744&w=4
Handled-By : Alan Cox <alan@lxorguk.ukuu.org.uk>
Patch : http://patchwork.kernel.org/patch/52698/
^ permalink raw reply
* [Bug #14375] Intel(R) I/OAT DMA Engine init failed
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List
Cc: Kernel Testers List, Alexander Beregalov, Dan Williams
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14375
Subject : Intel(R) I/OAT DMA Engine init failed
Submitter : Alexander Beregalov <a.beregalov@gmail.com>
Date : 2009-10-02 9:46 (10 days old)
References : http://marc.info/?l=linux-kernel&m=125447680016160&w=4
Handled-By : Dan Williams <dan.j.williams@intel.com>
Patch : http://patchwork.kernel.org/patch/51808/
^ permalink raw reply
* [Bug #14390] "bind" a device to a driver doesn't not work anymore
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List; +Cc: Kernel Testers List, Éric Piel
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14390
Subject : "bind" a device to a driver doesn't not work anymore
Submitter : Éric Piel <Eric.Piel@tremplin-utc.net>
Date : 2009-10-11 0:04 (1 days old)
References : http://marc.info/?l=linux-kernel&m=125521979921241&w=4
^ permalink raw reply
* [Bug #14389] Build system issue
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List
Cc: Kernel Testers List, Ingo Molnar, Pavel Machek, Peter Zijlstra,
Sam Ravnborg
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14389
Subject : Build system issue
Submitter : Peter Zijlstra <peterz@infradead.org>
Date : 2009-10-09 8:58 (3 days old)
First-Bad-Commit: http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=575543347b5baed0ca927cb90ba8807396fe9cc9
References : http://marc.info/?l=linux-kernel&m=125507914909152&w=4
^ permalink raw reply
* [Bug #14376] Kernel NULL pointer dereference/ kvm subsystem
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List; +Cc: Kernel Testers List, Don Dupuis
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14376
Subject : Kernel NULL pointer dereference/ kvm subsystem
Submitter : Don Dupuis <dondster@gmail.com>
Date : 2009-10-06 14:38 (6 days old)
References : http://marc.info/?l=linux-kernel&m=125484025021737&w=4
^ permalink raw reply
* [Bug #14353] BUG: sleeping function called from invalid context at kernel/mutex.c:280
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List; +Cc: Kernel Testers List, Johannes Berg, Miles Lane
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14353
Subject : BUG: sleeping function called from invalid context at kernel/mutex.c:280
Submitter : Miles Lane <miles.lane@gmail.com>
Date : 2009-10-05 3:39 (7 days old)
References : http://marc.info/?l=linux-kernel&m=125471432208671&w=4
^ permalink raw reply
* [Bug #14352] WARNING: at net/mac80211/scan.c:267
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List; +Cc: Kernel Testers List, Maciej Rutecki
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14352
Subject : WARNING: at net/mac80211/scan.c:267
Submitter : Maciej Rutecki <maciej.rutecki@gmail.com>
Date : 2009-10-08 00:30 (4 days old)
References : http://bugzilla.intellinuxwireless.org/show_bug.cgi?id=2089#c7
^ permalink raw reply
* Re: [PATCH] generic_nvram: Turn nvram_ioctl into an unlocked ioctl
From: Arnd Bergmann @ 2009-10-11 22:25 UTC (permalink / raw)
To: Frederic Weisbecker
Cc: Thomas Gleixner, LKML, Ingo Molnar, John Kacur,
Sven-Thorsten Dietrich, Jonathan Corbet, Alessio Igor Bogani,
Arnd Bergmann, Alan Cox
In-Reply-To: <1255299165-8618-1-git-send-email-fweisbec@gmail.com>
On Monday 12 October 2009, Frederic Weisbecker wrote:
> nvram_ioctl is a bkl locked ioctl, but it can be an unlocked ioctl.
>
> - part is provided by the user
> - offset is provided by pmac_get_partition() which is safe as it only
> touches nvram_partitions, an array inistialized on __init time and
> read-only the rest of the time.
> - nvram_sync() only relies on core99_nvram_sync() which checks
> is_core_99, nvram_data, nvram_image. Those are variables initialized
> on __init time only and their direct values are not touched further.
> The rest modifies the nvram image header, protected by nv_lock
> already.
>
> So it's safe to call nvram_ioctl without the big kernel lock held.
>
> Reported-by: Arnd Bergmann <arndbergmann@googlemail.com>
> Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Ingo Molnar <mingo@elte.hu>
> Cc: John Kacur <jkacur@redhat.com>
> Cc: Sven-Thorsten Dietrich <sven@thebigcorporation.com>
> Cc: Jonathan Corbet <corbet@lwn.net>
> Cc: Alessio Igor Bogani <abogani@texware.it>
> Cc: Arnd Bergmann <arndbergmann@googlemail.com>
> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Hmm, I wish I had not started using the gmail MTA for sending out
mail, not that address is public forever.
> drivers/char/generic_nvram.c | 10 +++++-----
> 1 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/char/generic_nvram.c b/drivers/char/generic_nvram.c
> index c49200e..fd448aa 100644
> --- a/drivers/char/generic_nvram.c
> +++ b/drivers/char/generic_nvram.c
> @@ -118,11 +118,11 @@ static int nvram_ioctl(struct inode *inode, struct file *file,
> }
>
> const struct file_operations nvram_fops = {
> - .owner = THIS_MODULE,
> - .llseek = nvram_llseek,
> - .read = read_nvram,
> - .write = write_nvram,
> - .ioctl = nvram_ioctl,
> + .owner = THIS_MODULE,
> + .llseek = nvram_llseek,
> + .read = read_nvram,
> + .write = write_nvram,
> + .unlocked_ioctl = nvram_ioctl,
> };
>
> static struct miscdevice nvram_dev = {
The ioctl and unlocked_ioctl functions have a different signature, so you
need to adapt that, not just rename it.
Not sure if we should do it in the same patch, but this driver should also
have a compat_ioctl method pointing to the same function. The ioctl numbers
in this driver are all 32/64 bit clean, but are not listed in fs/compat_ioctl.c,
so adding a .compat_ioctl pointer is the easiest way to fix 32 bit userland
accessing the device.
Arnd <><
^ permalink raw reply
* [Bug #14297] console resume broken since ba15ab0e8d
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List
Cc: Kernel Testers List, Alan Cox, Deepak Saxena, Greg Kroah-Hartman,
Sascha Hauer
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14297
Subject : console resume broken since ba15ab0e8d
Submitter : Sascha Hauer <s.hauer@pengutronix.de>
Date : 2009-09-30 15:11 (12 days old)
References : http://marc.info/?l=linux-kernel&m=125432349404060&w=4
^ permalink raw reply
* [Bug #14279] Suspend to RAM freeze totally since 2.6.32-rc1 - Acer Aspire 1511Lmi laptop
From: Rafael J. Wysocki @ 2009-10-11 22:22 UTC (permalink / raw)
To: Linux Kernel Mailing List
Cc: Kernel Testers List, Christian Casteyde, Ingo Molnar, Jan Beulich,
Jan Beulich
In-Reply-To: <zJ_pXHNwoHC.A.akB.Aal0KB@chimera>
This message has been generated automatically as a part of a report
of recent regressions.
The following bug entry is on the current list of known regressions
from 2.6.31. Please verify if it still should be listed and let me know
(either way).
Bug-Entry : http://bugzilla.kernel.org/show_bug.cgi?id=14279
Subject : Suspend to RAM freeze totally since 2.6.32-rc1 - Acer Aspire 1511Lmi laptop
Submitter : Christian Casteyde <casteyde.christian@free.fr>
Date : 2009-09-30 18:14 (12 days old)
First-Bad-Commit: http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=5f68563996e812f9ca35b3939ad2a42e5d254d66
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