* Q1 RC2 test report for SNB H264 encoding driver
From: Lan, Hai @ 2011-04-09 7:42 UTC (permalink / raw)
To: SSD-OTC GFX QA; +Cc: intel-gfx
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The second round test result for the Linux SNB H264 encoding driver has come out. This version can support P frames now. Totally there are 1 P1 bug(Bug 464) and 4 P2 bugs(Bug 459, Bug 460, Bug 462, Bug 463). Following is the result for FVDO_Shore_4cif.yuv(704x576, QP=26).
H264 encoding quality
Linux driver PSNR (RC1, I frames only)
Linux driver PSNR (RC2, with 29 P frames per 30 frames)
Windows driver PSNR(I frames only)
SNR Y(dB)
14.15
41.23
43.38195
SNR U(dB)
11.42
47.92
49.67663
SNR V(dB)
10.68
48.62
49.02728
H264 encoding performance
Linux driver FPS (RC1, I frames only)
Linux driver FPS (RC2, with 29 P frames per 30 frames)
Windows driver FPS(I frames only)
FPS
6
104
516.61
The detailed result can be found in the attachment. Thanks.
Hai Lan
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply
* [U-Boot] [MIPS 0/2] Trivial cleanups
From: Shinya Kuribayashi @ 2011-04-09 7:43 UTC (permalink / raw)
To: u-boot
Two boring patches for common MIPS area.
Build tested on gth2, and verified no logical changes are incorporated.
^ permalink raw reply
* Recall: Q1 RC2 test report for SNB H264 encoding driver
From: Lan, Hai @ 2011-04-09 7:45 UTC (permalink / raw)
To: SSD-OTC GFX QA; +Cc: intel-gfx
Lan, Hai would like to recall the message, "Q1 RC2 test report for SNB H264 encoding driver".
^ permalink raw reply
* [U-Boot] [PATCH 1/2] MIPS: Remove mips_cache_lock() feature
From: Shinya Kuribayashi @ 2011-04-09 7:46 UTC (permalink / raw)
To: u-boot
In-Reply-To: <4DA00E3D.7010503@pobox.com>
As requested in commit e1390801a3c1a2b6d12fa90be368efc19f5b9bfd ([MIPS]
Request for the 'mips_cache_lock()' removal), such feature is no longer
needed for current MIPS implementation of U-Boot, and no one in the tree
use it for years.
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
---
arch/mips/cpu/mips32/cache.S | 93 ------------------------------------------
arch/mips/cpu/mips32/start.S | 7 ---
2 files changed, 0 insertions(+), 100 deletions(-)
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 2965938..edc0674 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -51,75 +51,6 @@
.set pop
.endm
-/*
- * cacheop macro to automate cache operations
- * first some helpers...
- */
-#define _mincache(size, maxsize) \
- bltu size,maxsize,9f ; \
- move size,maxsize ; \
-9:
-
-#define _align(minaddr, maxaddr, linesize) \
- .set noat ; \
- subu AT,linesize,1 ; \
- not AT ; \
- and minaddr,AT ; \
- addu maxaddr,-1 ; \
- and maxaddr,AT ; \
- .set at
-
-/* general operations */
-#define doop1(op1) \
- cache op1,0(a0)
-#define doop2(op1, op2) \
- cache op1,0(a0) ; \
- nop ; \
- cache op2,0(a0)
-
-/* specials for cache initialisation */
-#define doop1lw(op1) \
- lw zero,0(a0)
-#define doop1lw1(op1) \
- cache op1,0(a0) ; \
- lw zero,0(a0) ; \
- cache op1,0(a0)
-#define doop121(op1,op2) \
- cache op1,0(a0) ; \
- nop; \
- cache op2,0(a0) ; \
- nop; \
- cache op1,0(a0)
-
-#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
- .set noreorder ; \
-10: doop##tag##ops ; \
- bne minaddr,maxaddr,10b ; \
- add minaddr,linesize ; \
- .set reorder
-
-/* finally the cache operation macros */
-#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
- blez n,11f ; \
- addu n,kva ; \
- _align(kva, n, cacheLineSize) ; \
- _oploopn(kva, n, cacheLineSize, tag, ops) ; \
-11:
-
-#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
- _mincache(n, cacheSize); \
- blez n,11f ; \
- addu n,kva ; \
- _align(kva, n, cacheLineSize) ; \
- _oploopn(kva, n, cacheLineSize, tag, ops) ; \
-11:
-
-#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
- vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
-
-#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
- icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
-
.macro f_fill64 dst, offset, val
LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
@@ -302,27 +233,3 @@ LEAF(dcache_enable)
mtc0 t0, CP0_CONFIG
jr ra
END(dcache_enable)
-
-#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
-/*******************************************************************************
-*
-* mips_cache_lock - lock RAM area pointed to by a0 in cache.
-*
-* RETURNS: N/A
-*
-*/
-# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
- .globl mips_cache_lock
- .ent mips_cache_lock
-mips_cache_lock:
- li a1, CKSEG0 - CACHE_LOCK_SIZE
- addu a0, a1
- li a2, CACHE_LOCK_SIZE
- li a3, CONFIG_SYS_CACHELINE_SIZE
- move a1, a2
- icacheop(a0,a1,a2,a3,0x1d)
-
- jr ra
-
- .end mips_cache_lock
-#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index e661d46..0a9d9d5 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -252,13 +252,6 @@ reset:
/* Set up temporary stack.
*/
-#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
- li a0, CONFIG_SYS_INIT_SP_OFFSET
- la t9, mips_cache_lock
- jalr t9
- nop
-#endif
-
li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
la sp, 0(t0)
--
1.7.4.4
^ permalink raw reply related
* [U-Boot] [PATCH 2/2] MIPS: Coding style cleanups on common assembly files
From: Shinya Kuribayashi @ 2011-04-09 7:47 UTC (permalink / raw)
To: u-boot
In-Reply-To: <4DA00E3D.7010503@pobox.com>
Fix style issues and alignments globally. No logical changes.
- Replace C comments with AS line comments where possible
- Use ifndef where possible, rather than if !defined for simplicity
- An instruction executed in a delay slot is now indicated by a leading
space, not by C comment
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
---
arch/mips/cpu/mips32/cache.S | 81 ++++++++++++++---------------
arch/mips/cpu/mips32/start.S | 117 +++++++++++++++++++----------------------
2 files changed, 92 insertions(+), 106 deletions(-)
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index edc0674..5ce0ec4 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -76,8 +76,8 @@
* mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
*/
LEAF(mips_init_icache)
- blez a1, 9f
- mtc0 zero, CP0_TAGLO
+ blez a1, 9f
+ mtc0 zero, CP0_TAGLO
/* clear tag to invalidate */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
@@ -94,15 +94,15 @@ LEAF(mips_init_icache)
1: cache_op Index_Store_Tag_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
-9: jr ra
+9: jr ra
END(mips_init_icache)
/*
* mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
*/
LEAF(mips_init_dcache)
- blez a1, 9f
- mtc0 zero, CP0_TAGLO
+ blez a1, 9f
+ mtc0 zero, CP0_TAGLO
/* clear all tags */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
@@ -119,25 +119,23 @@ LEAF(mips_init_dcache)
1: cache_op Index_Store_Tag_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
-9: jr ra
+9: jr ra
END(mips_init_dcache)
-/*******************************************************************************
-*
-* mips_cache_reset - low level initialisation of the primary caches
-*
-* This routine initialises the primary caches to ensure that they
-* have good parity. It must be called by the ROM before any cached locations
-* are used to prevent the possibility of data with bad parity being written to
-* memory.
-* To initialise the instruction cache it is essential that a source of data
-* with good parity is available. This routine
-* will initialise an area of memory starting at location zero to be used as
-* a source of parity.
-*
-* RETURNS: N/A
-*
-*/
+/*
+ * mips_cache_reset - low level initialisation of the primary caches
+ *
+ * This routine initialises the primary caches to ensure that they have good
+ * parity. It must be called by the ROM before any cached locations are used
+ * to prevent the possibility of data with bad parity being written to memory.
+ *
+ * To initialise the instruction cache it is essential that a source of data
+ * with good parity is available. This routine will initialise an area of
+ * memory starting at location zero to be used as a source of parity.
+ *
+ * RETURNS: N/A
+ *
+ */
NESTED(mips_cache_reset, 0, ra)
move RA, ra
li t2, CONFIG_SYS_ICACHE_SIZE
@@ -185,13 +183,12 @@ NESTED(mips_cache_reset, 0, ra)
jr RA
END(mips_cache_reset)
-/*******************************************************************************
-*
-* dcache_status - get cache status
-*
-* RETURNS: 0 - cache disabled; 1 - cache enabled
-*
-*/
+/*
+ * dcache_status - get cache status
+ *
+ * RETURNS: 0 - cache disabled; 1 - cache enabled
+ *
+ */
LEAF(dcache_status)
mfc0 t0, CP0_CONFIG
li t1, CONF_CM_UNCACHED
@@ -202,13 +199,12 @@ LEAF(dcache_status)
2: jr ra
END(dcache_status)
-/*******************************************************************************
-*
-* dcache_disable - disable cache
-*
-* RETURNS: N/A
-*
-*/
+/*
+ * dcache_disable - disable cache
+ *
+ * RETURNS: N/A
+ *
+ */
LEAF(dcache_disable)
mfc0 t0, CP0_CONFIG
li t1, -8
@@ -218,13 +214,12 @@ LEAF(dcache_disable)
jr ra
END(dcache_disable)
-/*******************************************************************************
-*
-* dcache_enable - enable cache
-*
-* RETURNS: N/A
-*
-*/
+/*
+ * dcache_enable - enable cache
+ *
+ * RETURNS: N/A
+ *
+ */
LEAF(dcache_enable)
mfc0 t0, CP0_CONFIG
ori t0, CONF_CM_CMASK
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 0a9d9d5..f1e3447 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -62,11 +62,11 @@
.globl _start
.text
_start:
- RVECENT(reset,0) /* U-boot entry point */
- RVECENT(reset,1) /* software reboot */
-#if defined(CONFIG_INCA_IP)
- .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
- .word 0x00000000 /* phase of the flash */
+ RVECENT(reset,0) # U-boot entry point
+ RVECENT(reset,1) # software reboot
+#ifdef CONFIG_INCA_IP
+ .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during
+ .word 0x00000000 # booting phase of the flash
#else
RVECENT(romReserved,2)
#endif
@@ -131,7 +131,7 @@ _start:
RVECENT(romReserved,61)
RVECENT(romReserved,62)
RVECENT(romReserved,63)
- XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
+ XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector
RVECENT(romReserved,65)
RVECENT(romReserved,66)
RVECENT(romReserved,67)
@@ -147,7 +147,7 @@ _start:
RVECENT(romReserved,77)
RVECENT(romReserved,78)
RVECENT(romReserved,79)
- XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
+ XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector
RVECENT(romReserved,81)
RVECENT(romReserved,82)
RVECENT(romReserved,83)
@@ -163,7 +163,7 @@ _start:
RVECENT(romReserved,93)
RVECENT(romReserved,94)
RVECENT(romReserved,95)
- XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
+ XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector
RVECENT(romReserved,97)
RVECENT(romReserved,98)
RVECENT(romReserved,99)
@@ -196,19 +196,19 @@ _start:
RVECENT(romReserved,126)
RVECENT(romReserved,127)
- /* We hope there are no more reserved vectors!
+ /*
+ * We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
*/
.align 4
reset:
- /* Clear watch registers.
- */
+ /* Clear watch registers */
mtc0 zero, CP0_WATCHLO
mtc0 zero, CP0_WATCHHI
- /* WP(Watch Pending), SW0/1 should be cleared. */
+ /* WP(Watch Pending), SW0/1 should be cleared */
mtc0 zero, CP0_CAUSE
setup_c0_status_reset
@@ -217,47 +217,42 @@ reset:
mtc0 zero, CP0_COUNT
mtc0 zero, CP0_COMPARE
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/* CONFIG0 register */
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
+#endif
- /* Initialize $gp.
- */
+ /* Initialize $gp */
bal 1f
- nop
+ nop
.word _gp
1:
lw gp, 0(ra)
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
- /* Initialize any external memory.
- */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* Initialize any external memory */
la t9, lowlevel_init
jalr t9
- nop
+ nop
- /* Initialize caches...
- */
+ /* Initialize caches... */
la t9, mips_cache_reset
jalr t9
- nop
+ nop
- /* ... and enable them.
- */
+ /* ... and enable them */
li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
+#endif
- /* Set up temporary stack.
- */
+ /* Set up temporary stack */
li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
la sp, 0(t0)
la t9, board_init_f
jr t9
- nop
+ nop
/*
* void relocate_code (addr_sp, gd, addr_moni)
@@ -272,13 +267,13 @@ reset:
.globl relocate_code
.ent relocate_code
relocate_code:
- move sp, a0 /* Set new stack pointer */
+ move sp, a0 # set new stack pointer
li t0, CONFIG_SYS_MONITOR_BASE
la t3, in_ram
- lw t2, -12(t3) /* t2 <-- uboot_end_data */
+ lw t2, -12(t3) # t2 <-- uboot_end_data
move t1, a2
- move s2, a2 /* s2 <-- destination address */
+ move s2, a2 # s2 <-- destination address
/*
* Fix $gp:
@@ -287,8 +282,8 @@ relocate_code:
*/
move t6, gp
sub gp, CONFIG_SYS_MONITOR_BASE
- add gp, a2 /* gp now adjusted */
- sub s1, gp, t6 /* s1 <-- relocation offset */
+ add gp, a2 # gp now adjusted
+ sub s1, gp, t6 # s1 <-- relocation offset
/*
* t0 = source address
@@ -299,30 +294,28 @@ relocate_code:
/*
* Save destination address and size for later usage in flush_cache()
*/
- move s0, a1 /* save gd in s0 */
- move a0, t1 /* a0 <-- destination addr */
- sub a1, t2, t0 /* a1 <-- size */
+ move s0, a1 # save gd in s0
+ move a0, t1 # a0 <-- destination addr
+ sub a1, t2, t0 # a1 <-- size
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
ble t0, t2, 1b
- addu t1, 4 /* delay slot */
+ addu t1, 4
- /* If caches were enabled, we would have to flush them here.
- */
+ /* If caches were enabled, we would have to flush them here. */
/* a0 & a1 are already set up for flush_cache(start, size) */
la t9, flush_cache
jalr t9
- nop
+ nop
- /* Jump to where we've relocated ourselves.
- */
+ /* Jump to where we've relocated ourselves */
addi t0, s2, in_ram - _start
jr t0
- nop
+ nop
.word _gp
.word _GLOBAL_OFFSET_TABLE_
@@ -337,45 +330,43 @@ in_ram:
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
* generated by GNU ld. Skip these reserved entries from relocation.
*/
- lw t3, -4(t0) /* t3 <-- num_got_entries */
- lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */
- lw t5, -20(t0) /* t5 <-- _gp */
- sub t4, t5 /* compute offset*/
- add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */
- addi t4, t4, 8 /* Skipping first two entries. */
+ lw t3, -4(t0) # t3 <-- num_got_entries
+ lw t4, -16(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
+ lw t5, -20(t0) # t5 <-- _gp
+ sub t4, t5 # compute offset
+ add t4, t4, gp # t4 now holds relocated _G_O_T_
+ addi t4, t4, 8 # skipping first two entries
li t2, 2
1:
lw t1, 0(t4)
beqz t1, 2f
- add t1, s1
+ add t1, s1
sw t1, 0(t4)
2:
addi t2, 1
blt t2, t3, 1b
- addi t4, 4 /* delay slot */
+ addi t4, 4
- /* Clear BSS.
- */
- lw t1, -12(t0) /* t1 <-- uboot_end_data */
- lw t2, -8(t0) /* t2 <-- uboot_end */
- add t1, s1 /* adjust pointers */
+ /* Clear BSS */
+ lw t1, -12(t0) # t1 <-- uboot_end_data
+ lw t2, -8(t0) # t2 <-- uboot_end
+ add t1, s1 # adjust pointers
add t2, s1
sub t1, 4
1:
addi t1, 4
bltl t1, t2, 1b
- sw zero, 0(t1) /* delay slot */
+ sw zero, 0(t1)
- move a0, s0 /* a0 <-- gd */
+ move a0, s0 # a0 <-- gd
la t9, board_init_r
jr t9
- move a1, s2 /* delay slot */
+ move a1, s2
.end relocate_code
- /* Exception handlers.
- */
+ /* Exception handlers */
romReserved:
b romReserved
--
1.7.4.4
^ permalink raw reply related
* [Xenomai-help] ioremap domain
From: Doninelli Davide @ 2011-04-09 7:52 UTC (permalink / raw)
To: xenomai@xenomai.org
Hi,
ioremap and related function like readw/l or writew/l are executed in which domain?
Thanks in advance
Davide
^ permalink raw reply
* [PATCH] ux500: Adding support for u8500 Hsem functionality.
From: Ohad Ben-Cohen @ 2011-04-09 7:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1302294509-6595-1-git-send-email-mathieu.poirier@linaro.org>
Hi Mathieu,
On Fri, Apr 8, 2011 at 11:28 PM, <mathieu.poirier@linaro.org> wrote:
...
> + * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
> + * Heavily borrowed from the work of :
> + * ? Simon Que <sque@ti.com>
> + * ? Hddari Kanigeri <h-kanigeri2@ti.com>
s/Hddari/Hari/
> + ? ? ? platform_set_drvdata(pdev, state);
> +
> + ? ? ? /* no pm needed for HSem but required to comply
> + ? ? ? ?* with hwspilock core.
> + ? ? ? ?*/
> + ? ? ? pm_runtime_enable(&pdev->dev);
You seem to have removed the calls to pm_runtime_disable() throughout
the driver, is that on purpose ?
You should see an "Unbalanced pm_runtime_enable!" warning about this
if you tried rmmod'ing and insmod'ing the driver again.
And just a minor comment if you're submitting a v2: you have a bunch
of trailing whitespaces; try checkpatch to spot them easily.
Thanks,
Ohad.
^ permalink raw reply
* Re: [PATCH] ux500: Adding support for u8500 Hsem functionality.
From: Ohad Ben-Cohen @ 2011-04-09 7:53 UTC (permalink / raw)
To: mathieu.poirier
Cc: linux-arm-kernel, lee.jones, patches, linus.walleij, linux-kernel
In-Reply-To: <1302294509-6595-1-git-send-email-mathieu.poirier@linaro.org>
Hi Mathieu,
On Fri, Apr 8, 2011 at 11:28 PM, <mathieu.poirier@linaro.org> wrote:
...
> + * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
> + * Heavily borrowed from the work of :
> + * Simon Que <sque@ti.com>
> + * Hddari Kanigeri <h-kanigeri2@ti.com>
s/Hddari/Hari/
> + platform_set_drvdata(pdev, state);
> +
> + /* no pm needed for HSem but required to comply
> + * with hwspilock core.
> + */
> + pm_runtime_enable(&pdev->dev);
You seem to have removed the calls to pm_runtime_disable() throughout
the driver, is that on purpose ?
You should see an "Unbalanced pm_runtime_enable!" warning about this
if you tried rmmod'ing and insmod'ing the driver again.
And just a minor comment if you're submitting a v2: you have a bunch
of trailing whitespaces; try checkpatch to spot them easily.
Thanks,
Ohad.
^ permalink raw reply
* Re: [lm-sensors] ITE IT8721F, IT8758E it87 standalone driver report
From: Jean Delvare @ 2011-04-09 8:02 UTC (permalink / raw)
To: lm-sensors
In-Reply-To: <2610648201.20110407001722@mail.ru>
On Fri, 8 Apr 2011 22:06:48 +0400, Rebel wrote:
> Hello, Jean.
>
> You wrote:
>
> >> +5.00V 4.988V
> >> +12.0V 11.816V
>
> > For these two, we would need more values from the BIOS to conclude, as
> > we have 4 candidates (in0, in1, in2 and in6.)
>
> More values? But there is no more values in my BIOS.
I mean more samples for a given values. Often monitored values
oscillate between two or three values. On some systems you have to
leave and re-enter the monitoring screen in the BIOS to get new values,
but most of them update the values every second automatically.
> > This is simply not possible. "sensors" reads the configuration files
> > again each time to run it.
>
> I don't know how it can be, but before running sensors3 at first time,
> /etc/sensors.d was an empty folder, but now there is it8721.conf wich
> holds data i put into /etc/sensors.conf
Either you live in the 4th dimension, or your distribution has extra
code doing that kind of magic. The code at lm-sensors.org doesn't do
anything like this.
> > Not sure what you did exactly, but /etc/sensors.conf is not used by
> > lm-sensors 3.x if /etc/sensors3.conf is present. /etc/sensors3.conf is
> > always checked first, to make it possible to have both lm-sensors 2 and
> > lm-sensors 3 installed on a given machine (although nobody should be
> > doing this any longer.)
>
> Here is the log of my actions:
> - i have removed old sensors2 (apt-get remove lm-sensors) but may be
> Ubuntu hasn't deleted the old config file.
> - i compiled new sensors from sources and run it without parameters
> (the output was temp1 fan1 and so on)
> - in /etc/sensors.conf i put my chip and some labels
> - run newly built sensors with config /etc/srnsors.conf
> "sensors -c /etc/sensors.conf" and output was with correct labels i
> put in /etc/sensors.conf
> - i have deleted my chip and labesls from /etc/srnsors.conf and run
> sensors again without config, output was correct with my labels
>
> I think, when i run sensors with edited config /etc/sensors.conf it
> creates file in /etc/sensors.d. Is it right?
Our code doesn't do this, no. Your Linux distribution, maybe, but this
is the first time I hear of this.
--
Jean Delvare
http://khali.linux-fr.org/wishlist.html
_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors
^ permalink raw reply
* Wrong offset for SSB_SPROM4_ANTAVAIL?
From: Rafał Miłecki @ 2011-04-09 8:10 UTC (permalink / raw)
To: b43-dev
In-Reply-To: <BANLkTin-p+XQaWRezBP4Ux7NvLf3cB26DA@mail.gmail.com>
2011/4/9 Jonas Gorski <jonas.gorski@gmail.com>:
> while matching SPROM content to its offsets, I noticed that
> SSB_SPROM4_ANTAVAIL has an odd offset (0x5d)[1]. Shouldn't this be
> rather even (probably 0x5c), since the SPROM consists of 16 bit words?
>
> Regards
> Jonas
>
> [1] <http://git.kernel.org/?p=linux/kernel/git/linville/wireless-next-2.6.git;a=blob;f=include/linux/ssb/ssb_regs.h;h=402955ae48ceac9c118833bed28ca093407e4638;hb=HEAD#l290>
>
> P.S: I currently lack the free space for yet another kernel git tree,
> so I would prefer if somebody else fixes this - assuming my analysis
> is right ;-)
I'll have time after weekend. There is some mess generally. We have
ETHPHY instead of some LEDS and we have MASKs inverted for ANTENNA.
--
Rafa?
^ permalink raw reply
* [Qemu-devel] Patch1 for Mips64 usermode
From: Khansa Butt @ 2011-04-09 8:15 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 6173 bytes --]
*commands for patch apply*
git apply --ignore-whitespace --ignore-space-change --check ~/patch1
git am --ignore-whitespace --ignore-space-change ~/patch1
*Patch*
>From e96e20e50cada1c9e1b65de5925281cdd5659746 Mon Sep 17 00:00:00 2001
From: Ehsan-ul-Haq & Khansa Butt <khansa@kics.edu.pk>
Date: Sat, 9 Apr 2011 10:51:22 +0500
Subject: [PATCH 1/2] Support for MIPS64 user mode emulation
Signed-off-by: Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt <
khansa@kics.edu.pk>
---
configure | 1 +
default-configs/mips64-linux-user.mak | 1 +
linux-user/elfload.c | 2 +-
linux-user/main.c | 29 +++++++++++++++++++++++++++--
linux-user/mips64/syscall.h | 3 +++
linux-user/signal.c | 3 ++-
target-mips/translate.c | 1 +
7 files changed, 36 insertions(+), 4 deletions(-)
create mode 100644 default-configs/mips64-linux-user.mak
diff --git a/configure b/configure
index ae97e11..d1f7867 100755
--- a/configure
+++ b/configure
@@ -1039,6 +1039,7 @@ m68k-linux-user \
microblaze-linux-user \
microblazeel-linux-user \
mips-linux-user \
+mips64-linux-user \
mipsel-linux-user \
ppc-linux-user \
ppc64-linux-user \
diff --git a/default-configs/mips64-linux-user.mak
b/default-configs/mips64-linux-user.mak
new file mode 100644
index 0000000..1598bfc
--- /dev/null
+++ b/default-configs/mips64-linux-user.mak
@@ -0,0 +1 @@
+# Default configuration for mips64-linux-user
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index fe5410e..2832a33 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1384,7 +1384,7 @@ static void load_elf_image(const char *image_name, int
image_fd,
vaddr_po = TARGET_ELF_PAGEOFFSET(vaddr);
vaddr_ps = TARGET_ELF_PAGESTART(vaddr);
- error = target_mmap(vaddr_ps, eppnt->p_filesz + vaddr_po,
+ error = target_mmap(vaddr_ps, eppnt->p_memsz + vaddr_po,
elf_prot, MAP_PRIVATE | MAP_FIXED,
image_fd, eppnt->p_offset - vaddr_po);
if (error == -1) {
diff --git a/linux-user/main.c b/linux-user/main.c
index e651bfd..a7f4955 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1937,6 +1937,14 @@ static int do_store_exclusive(CPUMIPSState *env)
int d;
addr = env->lladdr;
+#if defined(TARGET_MIPS64)
+/* For MIPS64 on 32 bit host there is a need to make
+* the page accessible to which the above 'addr' is belonged */
+#if HOST_LONG_BITS == 32
+ int flag = PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_WRITE_ORG;
+ page_set_flags(addr, addr + 4096, flag);
+#endif
+#endif
page_addr = addr & TARGET_PAGE_MASK;
start_exclusive();
mmap_lock();
@@ -1978,7 +1986,8 @@ static int do_store_exclusive(CPUMIPSState *env)
void cpu_loop(CPUMIPSState *env)
{
target_siginfo_t info;
- int trapnr, ret;
+ int trapnr;
+ abi_long ret;
unsigned int syscall_num;
for(;;) {
@@ -1987,7 +1996,11 @@ void cpu_loop(CPUMIPSState *env)
cpu_exec_end(env);
switch(trapnr) {
case EXCP_SYSCALL:
+#if defined(TARGET_MIPS64)
+ syscall_num = env->active_tc.gpr[2] - 5000;
+#else
syscall_num = env->active_tc.gpr[2] - 4000;
+#endif
env->active_tc.PC += 4;
if (syscall_num >= sizeof(mips_syscall_args)) {
ret = -ENOSYS;
@@ -2008,12 +2021,22 @@ void cpu_loop(CPUMIPSState *env)
default:
break;
}
+#if defined(TARGET_MIPS64)
+ ret = do_syscall(env, env->active_tc.gpr[2],
+ env->active_tc.gpr[4],
+ env->active_tc.gpr[5],
+ env->active_tc.gpr[6],
+ env->active_tc.gpr[7],
+ env->active_tc.gpr[8],
+ env->active_tc.gpr[9]);
+#else
ret = do_syscall(env, env->active_tc.gpr[2],
env->active_tc.gpr[4],
env->active_tc.gpr[5],
env->active_tc.gpr[6],
env->active_tc.gpr[7],
arg5, arg6/*, arg7, arg8*/);
+#endif
}
if (ret == -TARGET_QEMU_ESIGRETURN) {
/* Returning from a successful sigreturn syscall.
@@ -2935,7 +2958,9 @@ int main(int argc, char **argv, char **envp)
#endif
#elif defined(TARGET_MIPS)
#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
- cpu_model = "20Kc";
+ /* we use this model so that we can decode MIPS64r2
+ reserved instruction */
+ cpu_model = "MIPS64R2-generic";
#else
cpu_model = "24Kf";
#endif
diff --git a/linux-user/mips64/syscall.h b/linux-user/mips64/syscall.h
index 668a2b9..ec65653 100644
--- a/linux-user/mips64/syscall.h
+++ b/linux-user/mips64/syscall.h
@@ -218,4 +218,7 @@ struct target_pt_regs {
+/* Nasty hack: define a fake errno value for use by sigreturn. */
+#define TARGET_QEMU_ESIGRETURN 255
+
#define UNAME_MACHINE "mips64"
diff --git a/linux-user/signal.c b/linux-user/signal.c
index ce033e9..a3d49dd 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -2413,7 +2413,8 @@ void sparc64_get_context(CPUSPARCState *env)
#endif
#elif defined(TARGET_ABI_MIPSN64)
-# warning signal handling not implemented
+/* This line is commented out to avoid compile time error */
+/* # warning signal handling not implemented */
static void setup_frame(int sig, struct target_sigaction *ka,
target_sigset_t *set, CPUState *env)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 0f93e2a..63c2563 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12694,6 +12694,7 @@ void cpu_reset (CPUMIPSState *env)
env->hflags |= MIPS_HFLAG_FPU;
}
#ifdef TARGET_MIPS64
+ env->hflags |= MIPS_HFLAG_UX;
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
env->hflags |= MIPS_HFLAG_F64;
}
--
1.7.3.4
[-- Attachment #2: Type: text/html, Size: 8249 bytes --]
^ permalink raw reply related
* Re: [PATCH] getopt: [getopt.c] add static qualifiers
From: Olivier Mengué @ 2011-04-09 8:17 UTC (permalink / raw)
To: Davidlohr Bueso; +Cc: util-linux
In-Reply-To: <1301355571.2073.1.camel@offworld>
I've noticed my patch has been committed in
0a626987e244b6fa30c18cfa86d12cd80b3977e8.
Thanks.
Le 29 mars 2011 01:39, Davidlohr Bueso <dave@gnu.org> a écrit :
>
> On Sun, 2011-03-27 at 18:29 +0200, Olivier Mengué wrote:
> > -void *our_malloc(size_t size);
> > -void *our_realloc(void *ptr, size_t size);
>
> It would be nice to use our xalloc lib for stuff like this.
Working on a patch for that.
However, note that xalloc error messages are not localized contrary to
the current implementation.
> > -void print_help(void)
> > +static void print_help(void)
>
> Lately we've been standardizing this kind of things too.
A real cleanup of this function would require to also merge the
multiple fputs() calls. This would have impact on localization.
What is the policy on changes having impact on localization? (Please,
add the answer to README.devel too).
Olivier.
^ permalink raw reply
* [xen-unstable test] 6812: tolerable FAIL - PUSHED
From: xen.org @ 2011-04-09 8:20 UTC (permalink / raw)
To: xen-devel; +Cc: ian.jackson
flight 6812 xen-unstable real [real]
http://www.chiark.greenend.org.uk/~xensrcts/logs/6812/
Failures :-/ but no regressions.
Tests which are failing intermittently (not blocking):
test-amd64-amd64-pv 18 leak-check/check fail pass in 6809
test-amd64-xcpkern-i386-xl-credit2 9 guest-start fail pass in 6809
test-i386-i386-pv 9 guest-start fail pass in 6809
test-i386-i386-win 14 guest-start.2 fail pass in 6809
test-i386-xcpkern-i386-pv 9 guest-start fail pass in 6809
Tests which did not succeed, but are not blocking,
including regressions (tests previously passed) regarded as allowable:
test-amd64-amd64-win 16 leak-check/check fail never pass
test-amd64-amd64-xl-win 13 guest-stop fail never pass
test-amd64-i386-rhel6hvm-amd 8 guest-saverestore fail never pass
test-amd64-i386-rhel6hvm-intel 8 guest-saverestore fail never pass
test-amd64-i386-win-vcpus1 16 leak-check/check fail never pass
test-amd64-i386-win 16 leak-check/check fail never pass
test-amd64-i386-xl-win-vcpus1 13 guest-stop fail never pass
test-amd64-xcpkern-i386-rhel6hvm-amd 8 guest-saverestore fail never pass
test-amd64-xcpkern-i386-rhel6hvm-intel 8 guest-saverestore fail never pass
test-amd64-xcpkern-i386-win 16 leak-check/check fail never pass
test-amd64-xcpkern-i386-xl-win 13 guest-stop fail never pass
test-i386-i386-xl-win 13 guest-stop fail never pass
test-i386-xcpkern-i386-win 16 leak-check/check fail never pass
version targeted for testing:
xen 49626dab3618
baseline version:
xen 97763efc41f9
------------------------------------------------------------
People who touched revisions under test:
Allen Kay <allen.m.kay@intel.com>
Christoph Egger <Christoph.Egger@amd.com>
Eddie Dong <eddie.dong@intel.com>
George Dunlap <george.dunlap@eu.citrix.com>
Gianni Tedesco <gianni.tedesco@citrix.com>
Ian Campbell <ian.campbell@citrix.com>
Ian Jackson <ian.jackson@eu.citrix.com>
Jim Fehlig <jfehlig@novell.com>
Keir Fraser <keir@xen.org>
Liu, Jinsong <jinsong.liu@intel.com>
Shriram Rajagopalan <rshriram@cs.ubc.ca>
Tim Deegan <Tim.Deegan@citrix.com>
Wei Huang <wei.huang2@amd.com>
------------------------------------------------------------
jobs:
build-i386-xcpkern pass
build-amd64 pass
build-i386 pass
build-amd64-oldkern pass
build-i386-oldkern pass
build-amd64-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl pass
test-amd64-i386-xl pass
test-i386-i386-xl pass
test-amd64-xcpkern-i386-xl pass
test-i386-xcpkern-i386-xl pass
test-amd64-i386-rhel6hvm-amd fail
test-amd64-xcpkern-i386-rhel6hvm-amd fail
test-amd64-i386-xl-credit2 pass
test-amd64-xcpkern-i386-xl-credit2 fail
test-amd64-i386-rhel6hvm-intel fail
test-amd64-xcpkern-i386-rhel6hvm-intel fail
test-amd64-i386-xl-multivcpu pass
test-amd64-xcpkern-i386-xl-multivcpu pass
test-amd64-amd64-pair pass
test-amd64-i386-pair pass
test-i386-i386-pair pass
test-amd64-xcpkern-i386-pair pass
test-i386-xcpkern-i386-pair pass
test-amd64-amd64-pv fail
test-amd64-i386-pv pass
test-i386-i386-pv fail
test-amd64-xcpkern-i386-pv pass
test-i386-xcpkern-i386-pv fail
test-amd64-i386-win-vcpus1 fail
test-amd64-i386-xl-win-vcpus1 fail
test-amd64-amd64-win fail
test-amd64-i386-win fail
test-i386-i386-win fail
test-amd64-xcpkern-i386-win fail
test-i386-xcpkern-i386-win fail
test-amd64-amd64-xl-win fail
test-i386-i386-xl-win fail
test-amd64-xcpkern-i386-xl-win fail
------------------------------------------------------------
sg-report-flight on woking.cam.xci-test.com
logs: /home/xc_osstest/logs
images: /home/xc_osstest/images
Logs, config files, etc. are available at
http://www.chiark.greenend.org.uk/~xensrcts/logs
Test harness code can be found at
http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary
Pushing revision :
+ branch=xen-unstable
+ revision=49626dab3618
+ . cri-lock-repos
++ . cri-common
+++ umask 002
+++ getconfig Repos
+++ perl -e '
use Osstest;
readconfigonly();
print $c{Repos} or die $!;
'
++ repos=/export/home/osstest/repos
++ repos_lock=/export/home/osstest/repos/lock
++ '[' x '!=' x/export/home/osstest/repos/lock ']'
++ OSSTEST_REPOS_LOCK_LOCKED=/export/home/osstest/repos/lock
++ exec with-lock-ex -w /export/home/osstest/repos/lock ./ap-push xen-unstable 49626dab3618
+ branch=xen-unstable
+ revision=49626dab3618
+ . cri-lock-repos
++ . cri-common
+++ umask 002
+++ getconfig Repos
+++ perl -e '
use Osstest;
readconfigonly();
print $c{Repos} or die $!;
'
++ repos=/export/home/osstest/repos
++ repos_lock=/export/home/osstest/repos/lock
++ '[' x/export/home/osstest/repos/lock '!=' x/export/home/osstest/repos/lock ']'
+ : xen@xenbits.xensource.com
+ : xen@xenbits.xensource.com:git/linux-pvops
+ : master
+ case "$branch" in
+ cd /export/home/osstest/repos/xen-unstable.hg
+ hg push -r 49626dab3618 ssh://xen@xenbits.xensource.com/HG/xen-unstable.hg
pushing to ssh://xen@xenbits.xensource.com/HG/xen-unstable.hg
searching for changes
remote: adding changesets
remote: adding manifests
remote: adding file changes
remote: added 45 changesets with 150 changes to 90 files
^ permalink raw reply
* Re: GSoC proposal for svn remote helper
From: Dmitry Ivankov @ 2011-04-09 8:21 UTC (permalink / raw)
To: Jonathan Nieder; +Cc: git, artagnon, david.barr, srabbelier, Eric Wong
In-Reply-To: <20110408223150.GA27284@elie>
Hi
On Sat, Apr 9, 2011 at 4:31 AM, Jonathan Nieder <jrnieder@gmail.com> wrote:
>
> At the moment I am more concerned with what its guts will look like
> than what features it will support. A feature list is just a way to
> advertise how good the guts are. ;-)
My current view is following:
Use svnrdump stream to track / in say svnroot branch. It'll be linear
(1), commits will include actual diffs, and some revprops translated
to their git counterparts like svn:log,svn:author,svn:date (2). And
it'll be a bridge for svn interaction.
In git-notes tree store sha1 -> svn rev mapping(3), and also for each
svn rev store all it's revprops.
Store and maintain /path branches - there we have some freedom of
choosing git parents.
That's all about fetch. Obviously svnrdump will be used to push
fast-forward linear history back to svnroot, or to a /path branch
which goes the same way in fast-forward case.
And to be somewhat usable we want to be able to rebase-push/dcommit
(if there is a dense stream of svn commits going, we don't want the
user to type git rebase, git push and fail until he gets a lucky
timing).
Merges need more thinking, and may be not that necessary for a start.
Path ignores, or even revision ignores should be possible to implement
in the code, but just an emergency tools for a user (sometimes people
(by mistake) commit something enormous or incompatible with
filesystems names or like, so that user considers it ok to trash this
out of his history), also there could be a need for permanent path
filter (like track /projX, not /bin) - just the same, be ready that
sometime it'll have to be implemented.
[skipped some of svn commit "races" and merge tricks]
>> -- if it was, create a svn branch of our parent, commit there, and
>> then create a merge commit of these two, commit it and get same merge
>> history back
>
> Yikes. I don't think typical projects would like the resulting
> history.
Will make them mad, but in some cases it should be ok, if we are
pushing a lengthy topic branch they'll sometimes prefer to see it as
one commit.
> Yes, this is an interesting question. Given a history like this (time
> flowing left to right):
>
> E --- F --- G
> / \
> A --- B --- C -- D -- H
>
> where A is the latest rev of trunk/, how do we push this history to
> svn? Where is the name of the side branch recorded in the git
> history?
Could be either autogenerated with some user pattern, like
/branches/user/tmpXX, or specified explicitly in git-notes or
somewhere, or maybe we have already pushed a placeholder branch to svn
and will commit there.
>
> On answer is that it's possible to learn the historical branch name by
> parsing the commit message for "H". Yuck.
>
> I'd put off pushing merges to start.
It's definitely not in the minimal plan.
> I think the cleanest solution is often to reject a push if it is not
> obvious how to represent it remotely, just as though the remote server
> had a hook that rejected it.
Makes sense, after all plain svn users want to see svn-like history,
because they still use svn.
(1) In theory we could track whole svnroot merges (from svnroot2 on
the same repo for example, or hypothetical merge from another repo)
but that's hardly used by anyone.
(2) The hardest thing is to decide which ones to store in git.
Translating more gives a better look and feel, translating less
reduces the chances to get the same git objects on another clone. And
what should git do if this data changes is not a trivial choice too.
(3) And a funny thing is could happen that there are path1@rev1
path2@rev2 that produce the same sha1. That's perfectly fine because
they are just refs, care should be taken when choosing a path to
commit to though. Also svn will distinguish them, but it's just a
corner case.
^ permalink raw reply
* Re: Tracking file metadata in git -- fix metastore or enhance git?
From: Chris Webb @ 2011-04-09 8:11 UTC (permalink / raw)
To: Richard Hartmann
Cc: Thorsten Glaser, Jonathan Nieder, Michael J Gruber, Git List
In-Reply-To: <BANLkTi=3LPRzohnZStAogddpL5ZLehb97Q@mail.gmail.com>
Richard Hartmann <richih.mailinglist@gmail.com> writes:
> * In most cases I can think of, it would be preferable to track
> changes in metadata along with the actual files.
>
> * It should be possible for other repositories to ignore this metadata.
>
> * I am not sure if notes are suitable for this. Using notes.displayRef
> to hide those notes is an option, but it would force everyone to set
> this up locally. Else, it would be very spammy.
>
> * .gitattributes is too important to fill with potentially thousands
> of lines, imo. Using it to define what metadata should be stored would
> make sense, though.
>
> * would a .gitmetadata make sense for storage? Alternatively, a
> .git/objects/??/*.metadata per object could make sense.
One other possibility which occurs: would it be possible to store
permissions, attributes and so on in a header line (or header lines) in the
blob itself, which are stripped from the file and applied to the filesystem
by a smudge filter, and added back by a clean filter?
If it works sensibly, this is roughly equivalent to adding a .gitmetadata
file as you suggest above, except that the permissions and attribute data
are stored with each file, so the resulting diffs will be nicer and merges
should always be trivial without any special handling.
(Disclaimer: I've never tried using smudge filters; maybe they can't be used
in the way I describe!)
Cheers,
Chris.
^ permalink raw reply
* Re: [Xenomai-help] ioremap domain
From: Gilles Chanteperdrix @ 2011-04-09 8:23 UTC (permalink / raw)
To: Doninelli Davide; +Cc: xenomai@xenomai.org
In-Reply-To: <68A9C7E0-33D0-4039-88AF-A1B62F1889BD@edu.hefr.ch>
Doninelli Davide wrote:
> Hi,
> ioremap and related function like readw/l or writew/l are executed in which domain?
The notion of "service X is executed in domain Y", only applies to
user-space services, because such services go through syscalls, and
Xenomai is able to switch automatically the calling thread domain.
For kernel-space services, what matter are the contexts from which
calling the function is valid. By default, you should consider that all
Linux services can only be called from Linux domain. After all, Linux
services were not written with the Xenomai kernel in mind.
This applies to ioremap.
There are, however, some exceptions:
- some services are modified to work in non-Linux domain, this is the
case of printk, or the spinlock services (but only for ipipe spinlocks).
- some services do not rely on the integrity of any data in the Linux
kernel, these ones are naturally safe to be called from Xenomai domain
even though they were not modified in any way. memcpy is an example of
such service on most architectures, and so are readl and writel.
--
Gilles.
^ permalink raw reply
* (no subject)
From: Irish Unit @ 2011-04-09 8:16 UTC (permalink / raw)
Irish lottery awarded you(1,350,000,00Pounds)Provide your
Names,Tel,Country,Occupation
^ permalink raw reply
* [PATCH 1/2] ARM: Differentiate SheevaPlugs and DockStars on the basis of the memory size.
From: Bernd Petrovitsch @ 2011-04-09 8:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4D9E42E1.1060902@ahsoftware.de>
On Fre, 2011-04-08 at 01:04 +0200, Alexander Holler wrote:
[...]
> I had a look at what's going on in the OMAP linux world for more than a
> year now and I think I've seen a lot of the stuff you are referring to.
Others were far longer in in several of these "Linux worlds" ....
> And I think one of the reasons that the mess happened is the same I've
> got trapped in. Why should anyone try to submit patches if he must fear
> to get caught in some senseless endless discussion about one line.
Welcome to the world where software is actually really maintained - and
not longer in the easy world of "fork it, hack it up to ship it and be
done with it - except of bugs actually reported by customers who care
enough to get the bug report that far" like it is not uncommon in the
embedded world.
> E.g. requiring people to use NULL than 0 or that stupid discussion now
You obviously where never forced to bugfix with source where you can
identify the writer of each be the style.
> about the simple patch I've posted. I'm writing whole (readable) C++
"readable" is quite subjective. And just because it is readable by you
doesn't imply it is readable for many others. Especially if you actually
wrote it .....
> applications (not crap!) in less time than what's is needed to submit
> and discuss a small patch for some silly hw.
That's precisely the point: Writing the source is the easiest job.
Maintaining it over years and keeping it clear is hard.
> So for me it's fully understandable why companies don't try to work with
> kernel people at first. They try to develop innovativ products they can
> sell, and it doesn't help if their developers would have to fear that
"Innovative products which actually sell" are neither necessary nor
sufficient to produce maintainable code.
IMHO it it quite the opposite - these companies just want to get their
products built as quickly as possible to minimize the time to market and
get it sold (as in "second place, first looser") and be done with it
(except the sales part of course).
And the vast majority of the software on these products is actually not
really maintained - they have just bugs fixed if they crop up and some
user works hard enough to get the bug report actually to someone who
might fix it.
Existing software is just patched to implement the "new features" far
enough to be usable on that one product - ignoring the big picture of
the upstream with all the features and possibilities.
For the next release/version/product, the old code is plain simply
forked and everyone moves on.
[...]
> It's one thing to say such to someone you know and work with, but it's a
> totally different thing to say such to someone you almost know nothing
> about. And not everybody who hasn't the name of a big company in his
> email address is a moron.
You have to read more mails on the LKML and you will see, that the
domain name in the mail address help in any direction - neither to avoid
being flamed nor that a patch goes faster in.
Of course, there *are* people out there where it looks like that a
well-known domain name helps - but most of them started to hack on the
kernel and (successfully) submit patches with other domains. Think about
it ...
> Sorry, I'm getting sick having to defend me here against people who like
> to call others crap and abonimation writing ones just because they have
> maintainer status or whatever.
The main reason was a pure technical one. Think about it ....
Bernd
--
Bernd Petrovitsch Email : bernd at petrovitsch.priv.at
LUGA : http://www.luga.at
^ permalink raw reply
* Re: [PATCH 1/2] ARM: Differentiate SheevaPlugs and DockStars on the basis of the memory size.
From: Bernd Petrovitsch @ 2011-04-09 8:29 UTC (permalink / raw)
To: Alexander Holler
Cc: Russell King - ARM Linux, Alexander Clouter, linux-kernel,
linux-arm-kernel
In-Reply-To: <4D9E42E1.1060902@ahsoftware.de>
On Fre, 2011-04-08 at 01:04 +0200, Alexander Holler wrote:
[...]
> I had a look at what's going on in the OMAP linux world for more than a
> year now and I think I've seen a lot of the stuff you are referring to.
Others were far longer in in several of these "Linux worlds" ....
> And I think one of the reasons that the mess happened is the same I've
> got trapped in. Why should anyone try to submit patches if he must fear
> to get caught in some senseless endless discussion about one line.
Welcome to the world where software is actually really maintained - and
not longer in the easy world of "fork it, hack it up to ship it and be
done with it - except of bugs actually reported by customers who care
enough to get the bug report that far" like it is not uncommon in the
embedded world.
> E.g. requiring people to use NULL than 0 or that stupid discussion now
You obviously where never forced to bugfix with source where you can
identify the writer of each be the style.
> about the simple patch I've posted. I'm writing whole (readable) C++
"readable" is quite subjective. And just because it is readable by you
doesn't imply it is readable for many others. Especially if you actually
wrote it .....
> applications (not crap!) in less time than what's is needed to submit
> and discuss a small patch for some silly hw.
That's precisely the point: Writing the source is the easiest job.
Maintaining it over years and keeping it clear is hard.
> So for me it's fully understandable why companies don't try to work with
> kernel people at first. They try to develop innovativ products they can
> sell, and it doesn't help if their developers would have to fear that
"Innovative products which actually sell" are neither necessary nor
sufficient to produce maintainable code.
IMHO it it quite the opposite - these companies just want to get their
products built as quickly as possible to minimize the time to market and
get it sold (as in "second place, first looser") and be done with it
(except the sales part of course).
And the vast majority of the software on these products is actually not
really maintained - they have just bugs fixed if they crop up and some
user works hard enough to get the bug report actually to someone who
might fix it.
Existing software is just patched to implement the "new features" far
enough to be usable on that one product - ignoring the big picture of
the upstream with all the features and possibilities.
For the next release/version/product, the old code is plain simply
forked and everyone moves on.
[...]
> It's one thing to say such to someone you know and work with, but it's a
> totally different thing to say such to someone you almost know nothing
> about. And not everybody who hasn't the name of a big company in his
> email address is a moron.
You have to read more mails on the LKML and you will see, that the
domain name in the mail address help in any direction - neither to avoid
being flamed nor that a patch goes faster in.
Of course, there *are* people out there where it looks like that a
well-known domain name helps - but most of them started to hack on the
kernel and (successfully) submit patches with other domains. Think about
it ...
> Sorry, I'm getting sick having to defend me here against people who like
> to call others crap and abonimation writing ones just because they have
> maintainer status or whatever.
The main reason was a pure technical one. Think about it ....
Bernd
--
Bernd Petrovitsch Email : bernd@petrovitsch.priv.at
LUGA : http://www.luga.at
^ permalink raw reply
* Re: Memory Sharing
From: Keir Fraser @ 2011-04-09 8:36 UTC (permalink / raw)
To: Lakshitha Harshan, xen-devel
In-Reply-To: <BANLkTimPJeKWJboj+bZ4EwrNHJ_=xNCEEA@mail.gmail.com>
On 09/04/2011 07:37, "Lakshitha Harshan" <harshan.dll@gmail.com> wrote:
> Hi guys,
>
> I'm receiving following errors when trying to create a VM.
>
> Error: Failed to create device.
> stdout:
> stderr: MEMSHR support not compiled in.
> Check that target "home/images/ubuntuX.img" exists and that blktap2 driver
> installed in dom0.
>
> In configuration file this is how i specify my disks.
>
> disk = ['tap2:tapdisk:aio:home/images/ubuntuX.img,hda,w',
> 'phy:/dev/sr0,hdc:cdrom,r' ]
>
> But if I use
> tapdisk2 -n aio:/home/images/ubuntuX.img command it executes and returns
> "/dev/xen/blktap-2/tapdev0".
>
> What I want is to test the memory sharing feature. So can anybody tell me how
> to do that?
You could try reverting changeset 20927:b882c558d4e4 and cross your fingers.
Looks like blktap2 devs disabled memshr extensions due to them not working
properly.
-- Keir
> Thanks,
> Harshan
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel
^ permalink raw reply
* Re: [Qemu-devel] MIPS64 user mode emulation Patch
From: Khansa Butt @ 2011-04-09 8:36 UTC (permalink / raw)
To: Riku Voipio; +Cc: qemu-devel
In-Reply-To: <20110329085558.GB29260@afflict.kos.to>
[-- Attachment #1: Type: text/plain, Size: 45282 bytes --]
Please see inline comments highlighted in red.
I will be sending 2 updated patches for mips64 user mode emulation.
On Tue, Mar 29, 2011 at 1:55 PM, Riku Voipio <riku.voipio@iki.fi> wrote:
> Hi,
>
> First, do you have some instructions on howto build Octeon usermode
> 64bit binaries. Second, I think we would prefer that the patch was split
> to smaller patches. At least the target-mips changes should be a separate
> patch.
>
> Some more comments included inline between the code.
>
> On Sat, Mar 26, 2011 at 11:58:37AM +0500, Khansa Butt wrote:
> > >From cd88be1263d0fc9802cd4dd358ed0299c0d106b0 Mon Sep 17 00:00:00 2001
> > From: Khansa Butt & Ehsan-ul-Haq <khansa@kics.edu.pk>
> > Date: Sat, 26 Mar 2011 11:53:11 +0500
> > Subject: [PATCH] MIPS64 user mode emulation in QEMU
> > This patch adds support for Cavium Network's
> > Octeon 57XX user mode instructions. Octeon
> > 57xx is based on MIPS64. So this patch is
> > the first MIPS64 User Mode Emulation in QEMU
> > This is the team(Khansa Butt, Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed)
> > work of HPCNL Lab at KICS-UET Lahore.
> >
> >
> > Signed-off-by: Khansa Butt <khansa@kics.edu.pk>
> > ---
> > configure | 1 +
> > default-configs/mips64-linux-user.mak | 1 +
> > exec.c | 1 +
> > linux-user/elfload.c | 15 +-
> > linux-user/main.c | 20 +-
> > linux-user/mips64/syscall.h | 2 +
> > linux-user/signal.c | 3 +-
> > linux-user/syscall.c | 2 +
> > target-mips/cpu.h | 16 +
> > target-mips/translate.c | 659
> > ++++++++++++++++++++++++++++++++-
> > 10 files changed, 704 insertions(+), 16 deletions(-)
> > create mode 100644 default-configs/mips64-linux-user.mak
> >
> > diff --git a/configure b/configure
> > index 438219b..045a4ef 100755
> > --- a/configure
> > +++ b/configure
> > @@ -1011,6 +1011,7 @@ cris-linux-user \
> > m68k-linux-user \
> > microblaze-linux-user \
> > mips-linux-user \
> > +mips64-linux-user \
> > mipsel-linux-user \
> > ppc-linux-user \
> > ppc64-linux-user \
> > diff --git a/default-configs/mips64-linux-user.mak
> > b/default-configs/mips64-linux-user.mak
> > new file mode 100644
> > index 0000000..1598bfc
> > --- /dev/null
> > +++ b/default-configs/mips64-linux-user.mak
> > @@ -0,0 +1 @@
> > +# Default configuration for mips64-linux-user
> > diff --git a/exec.c b/exec.c
> > index 49c28b1..ee3f78e 100644
> > --- a/exec.c
> > +++ b/exec.c
> > @@ -2441,6 +2441,7 @@ int page_check_range(target_ulong start,
> target_ulong
> > len, int flags)
> > for (addr = start, len = end - start;
> > len != 0;
> > len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
> > + addr &= qemu_host_page_mask;
> > p = page_find(addr >> TARGET_PAGE_BITS);
>
> Are you sure this will not generate ill effect on other target/host
> architecture
> combinations?
>
>
The line has been removed in order to avoid ill effects
> > if( !p )
> > return -1;
> > diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> > index 33d776d..60fe85e 100644
> > --- a/linux-user/elfload.c
> > +++ b/linux-user/elfload.c
> > @@ -16,6 +16,8 @@
> > #include "qemu.h"
> > #include "disas.h"
> >
> > +extern int TARGET_OCTEON;
> > +
> > #ifdef _ARCH_PPC64
> > #undef ARCH_DLINFO
> > #undef ELF_PLATFORM
> > @@ -25,6 +27,9 @@
> > #undef ELF_ARCH
> > #endif
> >
> > +#define EF_MIPS_MARCH 16711680
> > +#define E_MIPS_MACH_OCTEON 9109504
> > +
>
> please use hexadecimal values.
>
> > #define ELF_OSABI ELFOSABI_SYSV
> >
> > /* from personality.h */
> > @@ -1313,7 +1318,7 @@ static void load_elf_image(const char *image_name,
> int
> > image_fd,
> > vaddr_po = TARGET_ELF_PAGEOFFSET(vaddr);
> > vaddr_ps = TARGET_ELF_PAGESTART(vaddr);
> >
> > - error = target_mmap(vaddr_ps, eppnt->p_filesz + vaddr_po,
> > + error = target_mmap(vaddr_ps, eppnt->p_memsz + vaddr_po,
> > elf_prot, MAP_PRIVATE | MAP_FIXED,
> > image_fd, eppnt->p_offset - vaddr_po);
> > if (error == -1) {
> > @@ -1588,7 +1593,13 @@ int load_elf_binary(struct linux_binprm * bprm,
> > struct target_pt_regs * regs,
> > If we do nothing, we'll have overwritten this when we re-use
> > bprm->buf
> > when we load the interpreter. */
> > elf_ex = *(struct elfhdr *)bprm->buf;
> > -
> > +#if defined(TARGET_MIPS64)
> > + if ((elf_ex.e_flags & EF_MIPS_MARCH) == E_MIPS_MACH_OCTEON) {
> > + TARGET_OCTEON = 1;
> > + } else {
> > + TARGET_OCTEON = 0;
> > + }
> > +#endif
> > bprm->p = copy_elf_strings(1, &bprm->filename, bprm->page, bprm->p);
> > bprm->p =
> copy_elf_strings(bprm->envc,bprm->envp,bprm->page,bprm->p);
> > bprm->p =
> copy_elf_strings(bprm->argc,bprm->argv,bprm->page,bprm->p);
> > diff --git a/linux-user/main.c b/linux-user/main.c
> > index 0d627d6..8b4b90b 100644
> > --- a/linux-user/main.c
> > +++ b/linux-user/main.c
> > @@ -1937,10 +1937,16 @@ static int do_store_exclusive(CPUMIPSState *env)
> > int d;
> >
> > addr = env->lladdr;
> > + /* 64 bit address is converted to 32 bit value so that a valid
> > + * l1_map value can be accessed. This thing is needed for target
> > + * mips64 and host 32 bit x86
> > + */
> > + addr &= qemu_host_page_mask;
>
> same as earlier.
>
The above line is changed with following code snippet
#if defined(TARGET_MIPS64)
+/* For MIPS64 on 32 bit host there is a need to make
+* the page accessible to which the above 'addr' is belonged */
+#if HOST_LONG_BITS == 32
+ int flag = PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_WRITE_ORG;
+ page_set_flags(addr, addr + 4096, flag);
+#endif
+#endif
>
> > page_addr = addr & TARGET_PAGE_MASK;
> > start_exclusive();
> > mmap_lock();
> > flags = page_get_flags(page_addr);
> > + addr = env->lladdr;
> > if ((flags & PAGE_READ) == 0) {
> > segv = 1;
> > } else {
> > @@ -1978,7 +1984,8 @@ static int do_store_exclusive(CPUMIPSState *env)
> > void cpu_loop(CPUMIPSState *env)
> > {
> > target_siginfo_t info;
> > - int trapnr, ret;
> > + int trapnr;
> > + abi_long ret;
> > unsigned int syscall_num;
> >
> > for(;;) {
> > @@ -1987,7 +1994,11 @@ void cpu_loop(CPUMIPSState *env)
> > cpu_exec_end(env);
> > switch(trapnr) {
> > case EXCP_SYSCALL:
> > +#if defined(TARGET_MIPS64)
> > + syscall_num = env->active_tc.gpr[2] - 5000;
> > +#else
> > syscall_num = env->active_tc.gpr[2] - 4000;
> > +#endif
> > env->active_tc.PC += 4;
> > if (syscall_num >= sizeof(mips_syscall_args)) {
> > ret = -ENOSYS;
> > @@ -2013,7 +2024,8 @@ void cpu_loop(CPUMIPSState *env)
> > env->active_tc.gpr[5],
> > env->active_tc.gpr[6],
> > env->active_tc.gpr[7],
> > - arg5, arg6/*, arg7, arg8*/);
> > + env->active_tc.gpr[8],
> > + env->active_tc.gpr[9]/*, arg7, arg8*/);
> > }
> > if (ret == -TARGET_QEMU_ESIGRETURN) {
> > /* Returning from a successful sigreturn syscall.
> > @@ -2926,7 +2938,9 @@ int main(int argc, char **argv, char **envp)
> > #endif
> > #elif defined(TARGET_MIPS)
> > #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
> > - cpu_model = "20Kc";
> > + /* we use this model so that we can decode MIPS64r2
> > + reserved instruction */
> > + cpu_model = "MIPS64R2-generic";
> > #else
> > cpu_model = "24Kf";
> > #endif
> > diff --git a/linux-user/mips64/syscall.h b/linux-user/mips64/syscall.h
> > index 668a2b9..1395e61 100644
> > --- a/linux-user/mips64/syscall.h
> > +++ b/linux-user/mips64/syscall.h
> > @@ -217,5 +217,7 @@ struct target_pt_regs {
> > #define TARGET_ENOTRECOVERABLE 166 /* State not recoverable */
> >
> >
> > +/* Nasty hack: define a fake errno value for use by sigreturn. */
> > +#define TARGET_QEMU_ESIGRETURN 255
> >
> > #define UNAME_MACHINE "mips64"
> > diff --git a/linux-user/signal.c b/linux-user/signal.c
> > index c846b8c..114116c 100644
> > --- a/linux-user/signal.c
> > +++ b/linux-user/signal.c
> > @@ -2410,7 +2410,8 @@ void sparc64_get_context(CPUSPARCState *env)
> > #endif
> > #elif defined(TARGET_ABI_MIPSN64)
> >
> > -# warning signal handling not implemented
> > +/*this line is commented out to avoid compile time error*/
> > +/*# warning signal handling not implemented*/
> >
> > static void setup_frame(int sig, struct target_sigaction *ka,
> > target_sigset_t *set, CPUState *env)
> > diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> > index 499c4d7..47fef05 100644
> > --- a/linux-user/syscall.c
> > +++ b/linux-user/syscall.c
> > @@ -7195,6 +7195,8 @@ abi_long do_syscall(void *cpu_env, int num,
> abi_long
> > arg1,
> > case TARGET_NR_set_thread_area:
> > #if defined(TARGET_MIPS)
> > ((CPUMIPSState *) cpu_env)->tls_value = arg1;
> > + /*tls entry is moved to k0 so that this can be used later*/
> > + ((CPUMIPSState *) cpu_env)->active_tc.gpr[26] = arg1;
>
> Does this affect the non-octeon mips ?
>
The above thing has been made Octeon specific.
>
> > ret = 0;
> > break;
> > #elif defined(TARGET_CRIS)
>
> And someone else will need to comment the TCG changes.
>
> > diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> > index 2419aa9..59bcc0f 100644
> > --- a/target-mips/cpu.h
> > +++ b/target-mips/cpu.h
> > @@ -140,6 +140,20 @@ typedef struct mips_def_t mips_def_t;
> > #define MIPS_FPU_MAX 1
> > #define MIPS_DSP_ACC 4
> >
> > +typedef struct cavium_mul cavium_mul;
> > +struct cavium_mul {
> > + target_ulong MPL0;
> > + target_ulong MPL1;
> > + target_ulong MPL2;
> > + target_ulong P0;
> > + target_ulong P1;
> > + target_ulong P2;
> > +};
> > +typedef struct cvmctl_register cvmctl_register;
> > +struct cvmctl_register {
> > + target_ulong cvmctl;
> > +};
> > +
> > typedef struct TCState TCState;
> > struct TCState {
> > target_ulong gpr[32];
> > @@ -178,6 +192,8 @@ struct CPUMIPSState {
> > TCState active_tc;
> > CPUMIPSFPUContext active_fpu;
> >
> > + cavium_mul Reg;
> > + cvmctl_register CvmCtlRegister;
> > uint32_t current_tc;
> > uint32_t current_fpu;
> >
> > diff --git a/target-mips/translate.c b/target-mips/translate.c
> > index cce77be..9c3d772 100644
> > --- a/target-mips/translate.c
> > +++ b/target-mips/translate.c
> > @@ -36,6 +36,15 @@
> > #define GEN_HELPER 1
> > #include "helper.h"
> >
> > +int TARGET_OCTEON;
> > +#if defined(TARGET_MIPS64)
> > +/*Macros for setting values of cvmctl registers*/
> > +#define FUSE_START_BIT(cvmctl)(cvmctl | 0x80000000)
> > +#define KASUMI(cvmctl)(cvmctl | 0x20000000)
> > +#define IPPCI(cvmctl)(cvmctl | 0x380)
> > +#define IPTI(cvmctl)(cvmctl | 0x70)
> > +#endif
> > +
> > //#define MIPS_DEBUG_DISAS
> > //#define MIPS_DEBUG_SIGN_EXTENSIONS
> >
> > @@ -70,6 +79,11 @@ enum {
> > OPC_JAL = (0x03 << 26),
> > OPC_JALS = OPC_JAL | 0x5,
> > OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
> > + /* Cavium Specific */
> > + OPC_BBIT1 = (0x3a << 26), /*jump on bit set, cavium specific*/
> > + OPC_BBIT132 = (0x3e << 26), /*jump on bit set(one of the upper 32
> > bits)*/
> > + OPC_BBIT0 = (0x32 << 26), /*jump on bit clear, cavium specific*/
> > + OPC_BBIT032 = (0x36 << 26), /*jump on bit set(one of the upper 32
> > bits)*/
> > OPC_BEQL = (0x14 << 26),
> > OPC_BNE = (0x05 << 26),
> > OPC_BNEL = (0x15 << 26),
> > @@ -265,6 +279,31 @@ enum {
> > OPC_MADD = 0x00 | OPC_SPECIAL2,
> > OPC_MADDU = 0x01 | OPC_SPECIAL2,
> > OPC_MUL = 0x02 | OPC_SPECIAL2,
> > + /* Cavium Specific Instructions */
> > + OPC_BADDU = 0x28 | OPC_SPECIAL2,
> > + OPC_DMUL = 0x03 | OPC_SPECIAL2,
> > + OPC_EXTS = 0x3a | OPC_SPECIAL2,
> > + OPC_EXTS32 = 0x3b | OPC_SPECIAL2,
> > + OPC_CINS = 0x32 | OPC_SPECIAL2,
> > + OPC_CINS32 = 0x33 | OPC_SPECIAL2,
> > + OPC_SEQI = 0x2e | OPC_SPECIAL2,
> > + OPC_SNEI = 0x2f | OPC_SPECIAL2,
> > + OPC_MTM0 = 0x08 | OPC_SPECIAL2,
> > + OPC_MTM1 = 0x0c | OPC_SPECIAL2,
> > + OPC_MTM2 = 0x0d | OPC_SPECIAL2,
> > + OPC_MTP0 = 0x09 | OPC_SPECIAL2,
> > + OPC_MTP1 = 0x0a | OPC_SPECIAL2,
> > + OPC_MTP2 = 0x0b | OPC_SPECIAL2,
> > + OPC_V3MULU = 0x11 | OPC_SPECIAL2,
> > + OPC_VMM0 = 0x10 | OPC_SPECIAL2,
> > + OPC_VMULU = 0x0f | OPC_SPECIAL2,
> > + OPC_POP = 0X2C | OPC_SPECIAL2,
> > + OPC_DPOP = 0X2D | OPC_SPECIAL2,
> > + OPC_SEQ = 0x2a | OPC_SPECIAL2,
> > + OPC_SNE = 0x2b | OPC_SPECIAL2,
> > + OPC_SAA = 0x18 | OPC_SPECIAL2,
> > + OPC_SAAD = 0x19 | OPC_SPECIAL2,
> > +/**************************************/
> > OPC_MSUB = 0x04 | OPC_SPECIAL2,
> > OPC_MSUBU = 0x05 | OPC_SPECIAL2,
> > /* Loongson 2F */
> > @@ -483,7 +522,7 @@ enum {
> > static TCGv_ptr cpu_env;
> > static TCGv cpu_gpr[32], cpu_PC;
> > static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC],
> > cpu_ACX[MIPS_DSP_ACC];
> > -static TCGv cpu_dspctrl, btarget, bcond;
> > +static TCGv cpu_dspctrl, btarget, bcond, mpl0, mpl1, mpl2, p0, p1, p2;
> > static TCGv_i32 hflags;
> > static TCGv_i32 fpu_fcr0, fpu_fcr31;
> >
> > @@ -779,7 +818,9 @@ static inline void gen_op_addr_add (DisasContext
> *ctx,
> > TCGv ret, TCGv arg0, TCGv
> > See the MIPS64 PRA manual, section 4.10. */
> > if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
> > !(ctx->hflags & MIPS_HFLAG_UX)) {
> > - tcg_gen_ext32s_i64(ret, ret);
> > + /*This function sign extend 32 bit value to 64 bit, was causing
> > error
> > + when ld instruction came.Thats why it is commmented out*/
> > + /* tcg_gen_ext32s_i64(ret, ret);*/
> > }
> > #endif
> > }
> > @@ -1419,7 +1460,33 @@ static void gen_arith_imm (CPUState *env,
> > DisasContext *ctx, uint32_t opc,
> > (void)opn; /* avoid a compiler warning */
> > MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt],
> > regnames[rs], uimm);
> > }
> > -
> > +#if defined(TARGET_MIPS64)
> > +/*set on equal immidiate/seton not equal immidiate*/
> > +static void gen_set_imm(CPUState *env, uint32_t opc, int rt, int rs,
> > int16_t imm)
> > +{
> > + target_ulong uimm;
> > + TCGv t0, t1;
> > + const char *opn = "imm set";
> > + uimm = (uint16_t)imm;
> > + t0 = tcg_temp_new();
> > + t1 = tcg_temp_new();
> > + switch (opc) {
> > + case OPC_SEQI:
> > + tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
> > + gen_load_gpr(t0, rt);
> > + tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, 1);
> > + opn = "seqi";
> > + break;
> > + case OPC_SNEI:
> > + tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
> > + gen_load_gpr(t0, rt);
> > + gen_load_gpr(t1, 0);
> > + tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rt], t1, t0);
> > + opn = "snei";
> > + break;
> > + }
> > +}
> > +#endif
> > /* Logic with immediate operand */
> > static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs,
> > int16_t imm)
> > {
> > @@ -1583,13 +1650,196 @@ static void gen_shift_imm(CPUState *env,
> > DisasContext *ctx, uint32_t opc,
> > MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt],
> > regnames[rs], uimm);
> > tcg_temp_free(t0);
> > }
> > +#if defined(TARGET_MIPS64)
> > +/* Addition and carry detection*/
> > +static void gen_addc (TCGv arg1, TCGv arg2, TCGv res, TCGv c)
> > +{
> > + tcg_gen_add_tl(res, arg1, arg2);
> > + tcg_gen_setcond_tl(TCG_COND_LTU, c, res, arg1);
> > +}
> > +static void gen_LMI (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
> > + int rs, int rt, int rd)
> > +{
> > + const char *opn = "LMI";
> > + TCGv t0, t1;
> > + int nomul = env->CvmCtlRegister.cvmctl & 0x8000000;
> > + if (!nomul) {
> > + switch (opc) {
> > + case OPC_MTM0:
> > + tcg_gen_mov_tl(mpl0, cpu_gpr[rs]);
> > + tcg_gen_movi_tl(p0, 0);
> > + tcg_gen_movi_tl(p1, 0);
> > + tcg_gen_movi_tl(p2, 0);
> > + opn = "mtm0";
> > + break;
> > + case OPC_MTM1:
> > + tcg_gen_mov_tl(mpl1, cpu_gpr[rs]);
> > + tcg_gen_movi_tl(p0, 0);
> > + tcg_gen_movi_tl(p1, 0);
> > + tcg_gen_movi_tl(p2, 0);
> > + opn = "mtm1";
> > + break;
> > + case OPC_MTM2:
> > + tcg_gen_mov_tl(mpl2, cpu_gpr[rs]);
> > + tcg_gen_movi_tl(p0, 0);
> > + tcg_gen_movi_tl(p1, 0);
> > + tcg_gen_movi_tl(p2, 0);
> > + opn = "mtm2";
> > + break;
> > + case OPC_MTP0:
> > + tcg_gen_mov_tl(p0, cpu_gpr[rs]);
> > + opn = "mtp0";
> > + break;
> > + case OPC_MTP1:
> > + tcg_gen_mov_tl(p1, cpu_gpr[rs]);
> > + opn = "mtp1";
> > + break;
> > + case OPC_MTP2:
> > + tcg_gen_mov_tl(p2, cpu_gpr[rs]);
> > + opn = "mtp2";
> > + break;
> > + case OPC_VMM0:
> > + t0 = tcg_temp_new();
> > + t1 = tcg_temp_new();
> > + gen_load_gpr(t1, rs);
> > + gen_helper_dmultu(t1, mpl0);
> > + gen_load_gpr(t0, rt);
> > + tcg_gen_add_tl(t0, t0, cpu_LO[0]);
> > + tcg_gen_add_tl(t0, t0, p0);
> > + gen_store_gpr(t0, rd);
> > + tcg_gen_mov_tl(mpl0, cpu_gpr[rd]);
> > + tcg_gen_movi_tl(p0, 0);
> > + tcg_gen_movi_tl(p1, 0);
> > + tcg_gen_movi_tl(p2, 0);
> > + tcg_temp_free(t0);
> > + tcg_temp_free(t1);
> > + opn = "vmm0";
> > + break;
> > + case OPC_VMULU:
> > + {
> > + TCGv t2, c;
> > + t0 = tcg_temp_new();
> > + t1 = tcg_temp_new();
> > + t2 = tcg_temp_new();
> > + c = tcg_temp_new();
> > + gen_load_gpr(t1, rs);
> > + gen_load_gpr(t2, rt);
> > + gen_helper_dmultu(t1, mpl0);
> > + tcg_gen_mov_tl(t0, cpu_LO[0]);
> > + /*if carry comes due to addition of rt and LO register,
> > + * this carry should be added to HI register.
> > + */
> > + gen_addc(t0, t2, t1, c);
> >
> > + tcg_gen_add_tl(cpu_HI[0], cpu_HI[0], c);
> > + /* t0 = t1 + p0 where t1 = LO+rt*/
> > + gen_addc(t1, p0, t0, c);
> > + tcg_gen_add_tl(cpu_HI[0], cpu_HI[0], c);
> > +
> > + tcg_gen_mov_tl(cpu_gpr[rd], t0);
> > + tcg_gen_mov_tl(p0, cpu_HI[0]);
> > + tcg_temp_free(t0);
> > + tcg_temp_free(t1);
> > + tcg_temp_free(t2);
> > + opn = "vmulu";
> > + break;
> > + }
> > + case OPC_V3MULU:
> > + {
> > + TCGv temp[4];
> > + TCGv c;
> > + TCGv trs, trt, tc1, tc2, tc3;
> > + temp[0] = tcg_temp_new();
> > + temp[1] = tcg_temp_new();
> > + temp[2] = tcg_temp_new();
> > + temp[3] = tcg_temp_new();
> > + trs = tcg_temp_new();
> > + trt = tcg_temp_new();
> > + tc1 = tcg_temp_new();
> > + tc2 = tcg_temp_new();
> > + tc3 = tcg_temp_new();
> > + c = tcg_temp_new();
> > + gen_load_gpr(trs, rs);
> > + gen_load_gpr(trt, rt);
> > + /* rs × (MPL2 || MPL1 || MPL0) (192X64 bit
> multiplication)
> > */
> > + gen_helper_dmultu(trs, mpl0);
> > + tcg_gen_mov_tl(temp[0], cpu_LO[0]);
> > + tcg_gen_mov_tl(temp[1], cpu_HI[0]);
> > +
> > + gen_helper_dmultu(trs, mpl1);
> > + tcg_gen_mov_tl(temp[2], cpu_HI[0]);
> > + gen_addc(cpu_LO[0], temp[1], tc1, tc2);
> > + gen_addc(temp[2], tc2, tc3, c);
> > + tcg_gen_mov_tl(temp[1], tc1);
> > + tcg_gen_mov_tl(temp[2], tc3);
> > + tcg_gen_mov_tl(temp[3], c);
> > +
> > + gen_helper_dmultu(trs, mpl2);
> > + tcg_gen_add_tl(temp[3], temp[3], cpu_HI[0]);
> > + gen_addc(cpu_LO[0], temp[2], tc1, tc2);
> > + tcg_gen_mov_tl(temp[2], tc1);
> > + tcg_gen_add_tl(temp[3], temp[3], tc2);
> > + /* Addition of rt in 256 bit result
> > + (t3 t2 t1 t0 contain result) */
> > + gen_addc(temp[0], trt, tc1, c);
> > + tcg_gen_mov_tl(temp[0], tc1);
> > + gen_addc(temp[1], c, tc1, tc2);
> > + tcg_gen_mov_tl(temp[1], tc1);
> > + gen_addc(temp[2], tc2, tc1, c);
> > + tcg_gen_mov_tl(temp[2], tc1);
> > + tcg_gen_add_tl(temp[3], temp[3], c);
> > + /* Addition of p2 p1 p0 in 256 bit result */
> > + gen_addc(temp[0], p0, tc1, c);
> > + tcg_gen_mov_tl(temp[0], tc1);
> > + gen_addc(temp[1], c, tc1, tc2);
> > + tcg_gen_mov_tl(temp[1], tc1);
> > + gen_addc(temp[2], tc2, tc1, c);
> > + tcg_gen_mov_tl(temp[2], tc1);
> > + tcg_gen_add_tl(temp[3], temp[3], c);
> > +
> > + gen_addc(temp[1], p1, tc1, c);
> > + tcg_gen_mov_tl(temp[1], tc1);
> > + gen_addc(temp[2], c, tc1, tc2);
> > + tcg_gen_mov_tl(temp[2], tc1);
> > + tcg_gen_add_tl(temp[3], temp[3], tc2);
> > +
> > + gen_addc(temp[2], p2, tc1, c);
> > + tcg_gen_mov_tl(temp[2], tc1);
> > + tcg_gen_add_tl(temp[3], temp[3], c);
> > + /* final step */
> > + tcg_gen_mov_tl(cpu_gpr[rd], temp[0]);
> > + tcg_gen_mov_tl(p0, temp[1]);
> > + tcg_gen_mov_tl(p1, temp[2]);
> > + tcg_gen_mov_tl(p2, temp[3]);
> > + tcg_temp_free(temp[0]);
> > + tcg_temp_free(temp[1]);
> > + tcg_temp_free(temp[2]);
> > + tcg_temp_free(temp[3]);
> > + tcg_temp_free(trs);
> > + tcg_temp_free(trt);
> > + tcg_temp_free(tc1);
> > + tcg_temp_free(tc2);
> > + tcg_temp_free(tc3);
> > + tcg_temp_free(c);
> > + opn = "v3mulu";
> > + break;
> > + }
> > + }
> > +
> > + } else {
> > + generate_exception(ctx, EXCP_RI);
> > + }
> > +}
> > +
> > +
> > +#endif
> > /* Arithmetic */
> > static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
> > int rd, int rs, int rt)
> > {
> > const char *opn = "arith";
> >
> > + target_ulong mask = 0xFF;
> > if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
> > && opc != OPC_DADD && opc != OPC_DSUB) {
> > /* If no destination, treat it as a NOP.
> > @@ -1637,6 +1887,22 @@ static void gen_arith (CPUState *env, DisasContext
> > *ctx, uint32_t opc,
> > }
> > opn = "addu";
> > break;
> > + case OPC_BADDU:
> > + {
> > + TCGv t0 = tcg_temp_new();
> > + TCGv t1 = tcg_temp_new();
> > + TCGv t2 = tcg_temp_new();
> > + gen_load_gpr(t1, rs);
> > + gen_load_gpr(t2, rt);
> > + tcg_gen_andi_tl(t1, t1, mask);
> > + tcg_gen_andi_tl(t2, t2, mask);
> > + tcg_gen_add_tl(t0, t1, t2);
> > + tcg_gen_andi_tl(t0, t0, mask);
> > + gen_store_gpr(t0, rd);
> > + }
> > +
> > + opn = "baddu";
> > + break;
> > case OPC_SUB:
> > {
> > TCGv t0 = tcg_temp_local_new();
> > @@ -2013,7 +2279,74 @@ static void gen_HILO (DisasContext *ctx, uint32_t
> > opc, int reg)
> > (void)opn; /* avoid a compiler warning */
> > MIPS_DEBUG("%s %s", opn, regnames[reg]);
> > }
> > +#if defined(TARGET_MIPS64)
> > +static void gen_seqsne (DisasContext *ctx, uint32_t opc,
> > + int rd, int rs, int rt)
> > +{
> > + const char *opn = "seq/sne";
> > + TCGv t0, t1;
> > + t0 = tcg_temp_new();
> > + t1 = tcg_temp_new();
> > + switch (opc) {
> > + case OPC_SEQ:
> > + {
> > + tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
> > + gen_load_gpr(t0, rd);
> > + tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rd], t0, 1);
> > + }
> > + opn = "seq";
> > + break;
> > + case OPC_SNE:
> > + {
> > + tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
> > + gen_load_gpr(t0, rd);
> > + gen_load_gpr(t1, 0);
> > + tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t1, t0);
> > + }
> > + opn = "sne";
> > + break;
> > + default:
> > + MIPS_INVAL(opn);
> > + generate_exception(ctx, EXCP_RI);
> > + goto out;
> > + }
> > +out:
> > + tcg_temp_free(t0);
> > + tcg_temp_free(t1);
> >
> > +}
> > +
> > +static void gen_saa (CPUState *env, DisasContext *ctx, uint32_t opc,
> > + int rt, int base)
> > +{
> > + const char *opn = "saa";
> > + TCGv t0, t1, temp;
> > + t0 = tcg_temp_new();
> > + t1 = tcg_temp_new();
> > + temp = tcg_temp_new();
> > + gen_load_gpr(t1, rt);
> > + gen_base_offset_addr(ctx, t0, base, 0);
> > + switch (opc) {
> > + case OPC_SAA:
> > + save_cpu_state(ctx, 1);
> > + op_ld_lw(temp, t0, ctx);
> > + tcg_gen_add_tl(temp, temp, t1);
> > + op_st_sw(temp, t0, ctx);
> > + opn = "saa";
> > + break;
> > + case OPC_SAAD:
> > + save_cpu_state(ctx, 0);
> > + op_ld_ld(temp, t0, ctx);
> > + tcg_gen_add_tl(temp, temp, t1);
> > + op_st_sd(temp, t0, ctx);
> > + opn = "saad";
> > + break;
> > + }
> > +
> > + tcg_temp_free(t0);
> > + tcg_temp_free(t1);
> > +}
> > +#endif
> > static void gen_muldiv (DisasContext *ctx, uint32_t opc,
> > int rs, int rt)
> > {
> > @@ -2149,6 +2482,10 @@ static void gen_muldiv (DisasContext *ctx,
> uint32_t
> > opc,
> > gen_helper_dmult(t0, t1);
> > opn = "dmult";
> > break;
> > + case OPC_DMUL:
> > + gen_helper_dmult(t0, t1);
> > + opn = "dmul";
> > + break;
> > case OPC_DMULTU:
> > gen_helper_dmultu(t0, t1);
> > opn = "dmultu";
> > @@ -2368,7 +2705,49 @@ static void gen_cl (DisasContext *ctx, uint32_t
> opc,
> > MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
> > tcg_temp_free(t0);
> > }
> > +#if defined(TARGET_MIPS64)
> > +static void insn_opc_pop (DisasContext *ctx, CPUState *env, uint32_t
> opc,
> > + int rd, int rs, int rt)
> > +{
> > + TCGv num = tcg_temp_new();
> > + TCGv res = tcg_temp_new();
> > + target_ulong maskb = 1;
> > + gen_load_gpr(num, rs);
> > + TCGv ones=tcg_temp_new();
> > + gen_load_gpr(ones, 0);
> > + int x=1;
> > + tcg_gen_andi_tl(res, num, maskb);
> > + tcg_gen_add_tl(ones,ones, res);
> > + while (x <= 31) {
> > + tcg_gen_shri_i64(num, num, 1);
> > + tcg_gen_andi_tl(res, num, maskb);
> > + tcg_gen_add_tl(ones, ones, res);
> > + x++;
> > + }
> > + gen_store_gpr(ones, rd);
> > +}
> > +static void insn_opc_dpop (DisasContext *ctx, CPUState *env, uint32_t
> opc,
> > + int rd, int rs, int rt)
> > +{
> > + TCGv num, res, ones;
> > + num = tcg_temp_new();
> > + res = tcg_temp_new();
> > + ones = tcg_temp_new();
> > + target_ulong maskb = 1;
> > + gen_load_gpr(num, rs);
> > + int x = 1;
> > + tcg_gen_andi_tl(res, num, maskb);
> > + tcg_gen_mov_tl(ones, res);
> >
> > + while (x <= 63) {
> > + tcg_gen_shri_i64(num, num, 1);
> > + tcg_gen_andi_tl(res, num, maskb);
> > + tcg_gen_add_tl(ones, ones, res);
> > + x++;
> > + }
> > + gen_store_gpr(ones, rd);
> > +}
> > +#endif
> > /* Godson integer instructions */
> > static void gen_loongson_integer (DisasContext *ctx, uint32_t opc,
> > int rd, int rs, int rt)
> > @@ -2705,6 +3084,7 @@ static void gen_compute_branch (DisasContext *ctx,
> > uint32_t opc,
> > target_ulong btgt = -1;
> > int blink = 0;
> > int bcond_compute = 0;
> > + target_ulong maskb; /* Used in BBIT0 and BBIT1*/
> > TCGv t0 = tcg_temp_new();
> > TCGv t1 = tcg_temp_new();
> >
> > @@ -2730,6 +3110,39 @@ static void gen_compute_branch (DisasContext *ctx,
> > uint32_t opc,
> > }
> > btgt = ctx->pc + insn_bytes + offset;
> > break;
> > + case OPC_BBIT1:
> > + gen_load_gpr(t0, rs);
> > + gen_load_gpr(t1, 0);
> > + maskb = 1ULL << rt;
> > + tcg_gen_andi_tl(t0, t0, maskb);
> > + bcond_compute = 1;
> > + btgt = ctx->pc + insn_bytes + offset;
> > + break;
> > + case OPC_BBIT132:
> > + gen_load_gpr(t0, rs);
> > + gen_load_gpr(t1, 0);
> > + maskb = 1ULL << (rt + 32);
> > + tcg_gen_andi_tl(t0, t0, maskb);
> > + bcond_compute = 1;
> > + btgt = ctx->pc + insn_bytes + offset;
> > + break;
> > + case OPC_BBIT0:
> > + gen_load_gpr(t0, rs);
> > + gen_load_gpr(t1, 0);
> > + maskb = 1ULL << rt;
> > + tcg_gen_andi_tl(t0, t0, maskb);
> > + bcond_compute = 1;
> > + btgt = ctx->pc + insn_bytes + offset;
> > + break;
> > + case OPC_BBIT032:
> > + gen_load_gpr(t0, rs);
> > + gen_load_gpr(t1, 0);
> > + maskb = 1ULL << (rt + 32);
> > + tcg_gen_andi_tl(t0, t0, maskb);
> > + bcond_compute = 1;
> > + btgt = ctx->pc + insn_bytes + offset;
> > + break;
> > +
> > case OPC_BGEZ:
> > case OPC_BGEZAL:
> > case OPC_BGEZALS:
> > @@ -2888,6 +3301,18 @@ static void gen_compute_branch (DisasContext *ctx,
> > uint32_t opc,
> > MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
> > regnames[rs], regnames[rt], btgt);
> > goto not_likely;
> > + case OPC_BBIT1:
> > + tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
> > + goto not_likely;
> > + case OPC_BBIT132:
> > + tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
> > + goto not_likely;
> > + case OPC_BBIT0:
> > + tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
> > + goto not_likely;
> > + case OPC_BBIT032:
> > + tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
> > + goto not_likely;
> > case OPC_BNEL:
> > tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
> > MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
> > @@ -2983,7 +3408,44 @@ static void gen_compute_branch (DisasContext *ctx,
> > uint32_t opc,
> > tcg_temp_free(t0);
> > tcg_temp_free(t1);
> > }
> > +/*For cavium specific extract instructions*/
> > +#if defined(TARGET_MIPS64)
> > +static void gen_exts (CPUState *env,DisasContext *ctx, uint32_t opc, int
> > rt,
> > + int rs, int lsb, int msb)
> > +{
> > + TCGv t0 = tcg_temp_new();
> > + TCGv t1 = tcg_temp_new();
> > + target_ulong mask;
> > + gen_load_gpr(t1, rs);
> > + switch (opc) {
> > + case OPC_EXTS:
> > + tcg_gen_shri_tl(t0, t1, lsb);
> > + tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
> > + /* To sign extened the remaining bits according to
> > + the msb of the bit field */
> > + mask = 1ULL << msb;
> > + tcg_gen_andi_tl(t1, t0, mask);
> > + tcg_gen_addi_tl(t1, t1, -1);
> > + tcg_gen_not_i64(t1, t1);
> > + tcg_gen_or_tl(t0, t0, t1);
> > + gen_store_gpr(t0, rt);
> > + break;
> > + case OPC_EXTS32:
> > + tcg_gen_shri_tl(t0, t1, lsb + 32);
> > + tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
> > + mask = 1ULL << msb;
> > + tcg_gen_andi_tl(t1, t0, mask);
> > + tcg_gen_addi_tl(t1, t1, -1);
> > + tcg_gen_not_i64(t1, t1);
> > + tcg_gen_or_tl(t0, t0, t1);
> > + gen_store_gpr(t0, rt);
> > + break;
> >
> > + }
> > + tcg_temp_free(t0);
> > + tcg_temp_free(t1);
> > +}
> > +#endif
> > /* special3 bitfield operations */
> > static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
> > int rs, int lsb, int msb)
> > @@ -3063,6 +3525,22 @@ static void gen_bitops (DisasContext *ctx,
> uint32_t
> > opc, int rt,
> > tcg_gen_andi_tl(t1, t1, mask);
> > tcg_gen_or_tl(t0, t0, t1);
> > break;
> > + case OPC_CINS:
> > + mask = (1ULL << (msb+1))-1;
> > + gen_load_gpr(t0, rt);
> > + tcg_gen_andi_tl(t0, t0, 0);
> > + tcg_gen_andi_tl(t1, t1, mask);
> > + tcg_gen_shli_tl(t1, t1, lsb);
> > + tcg_gen_or_tl(t0, t0, t1);
> > + break;
> > + case OPC_CINS32:
> > + mask = (1ULL << (msb+1))-1;
> > + gen_load_gpr(t0, rt);
> > + tcg_gen_andi_tl(t0, t0, 0);
> > + tcg_gen_andi_tl(t1, t1, mask);
> > + tcg_gen_shli_tl(t1, t1, (lsb+32));
> > + tcg_gen_or_tl(t0, t0, t1);
> > + break;
> > #endif
> > default:
> > fail:
> > @@ -11605,7 +12083,7 @@ static void decode_opc (CPUState *env,
> DisasContext
> > *ctx, int *is_branch)
> > int32_t offset;
> > int rs, rt, rd, sa;
> > uint32_t op, op1, op2;
> > - int16_t imm;
> > + int16_t imm, imm10;
> >
> > /* make sure instructions are on a word boundary */
> > if (ctx->pc & 0x3) {
> > @@ -11634,6 +12112,9 @@ static void decode_opc (CPUState *env,
> DisasContext
> > *ctx, int *is_branch)
> > rd = (ctx->opcode >> 11) & 0x1f;
> > sa = (ctx->opcode >> 6) & 0x1f;
> > imm = (int16_t)ctx->opcode;
> > + /* 10 bit Immediate value For SEQI,SNEI */
> > + imm10 = (ctx->opcode >> 6) & 0x3ff;
> > +
> > switch (op) {
> > case OPC_SPECIAL:
> > op1 = MASK_SPECIAL(ctx->opcode);
> > @@ -11859,6 +12340,71 @@ static void decode_opc (CPUState *env,
> DisasContext
> > *ctx, int *is_branch)
> > case OPC_MUL:
> > gen_arith(env, ctx, op1, rd, rs, rt);
> > break;
> > +#if defined(TARGET_MIPS64)
> > +
> > +
> > + case OPC_DMUL:
> > + check_insn(env, ctx, ISA_MIPS3);
> > + check_mips_64(ctx);
> > + gen_muldiv(ctx, op1, rs, rt);
> > + tcg_gen_mov_tl(cpu_gpr[rd], cpu_LO[0]);
> > + break;
> > + case OPC_CINS:
> > + check_insn(env, ctx, ISA_MIPS64R2);
> > + check_mips_64(ctx);
> > + gen_bitops(ctx, op1, rt, rs, sa, rd);
> > + break;
> > + case OPC_CINS32:
> > + check_mips_64(ctx);
> > + gen_bitops(ctx, op1, rt, rs, sa, rd);
> > + break;
> > + case OPC_MTM0:
> > + check_mips_64(ctx);
> > + gen_LMI(env, ctx, op1, rs, rt, rd);
> > + break;
> > + case OPC_MTM1:
> > + check_mips_64(ctx);
> > + gen_LMI(env, ctx, op1, rs, rt, rd);
> > + break;
> > + case OPC_MTM2:
> > + check_mips_64(ctx);
> > + gen_LMI(env, ctx, op1, rs, rt, rd);
> > + break;
> > + case OPC_MTP0:
> > + check_mips_64(ctx);
> > + gen_LMI(env, ctx, op1, rs, rt, rd);
> > + break;
> > + case OPC_MTP1:
> > + check_mips_64(ctx);
> > + gen_LMI(env, ctx, op1, rs, rt, rd);
> > + break;
> > + case OPC_MTP2:
> > + check_mips_64(ctx);
> > + gen_LMI(env, ctx, op1, rs, rt, rd);
> > + break;
> > + case OPC_VMULU:
> > + check_mips_64(ctx);
> > + gen_LMI(env, ctx, op1, rs, rt, rd);
> > + break;
> > + case OPC_BADDU:
> > + gen_arith(env, ctx, op1, rd, rs, rt);
> > + break;
> > + case OPC_EXTS:
> > + check_mips_64(ctx);
> > + gen_exts(env, ctx, op1, rt, rs, sa, rd);
> > + break;
> > + case OPC_EXTS32:
> > + check_mips_64(ctx);
> > + gen_exts(env, ctx, op1, rt, rs, sa, rd);
> > + break;
> > + case OPC_SAA:
> > + gen_saa(env, ctx, op1, rt, rs);
> > + break;
> > + case OPC_SAAD:
> > + check_mips_64(ctx);
> > + gen_saa(env, ctx, op1, rt, rs);
> > + break;
> > +#endif
> > case OPC_CLO:
> > case OPC_CLZ:
> > check_insn(env, ctx, ISA_MIPS32);
> > @@ -11878,13 +12424,24 @@ static void decode_opc (CPUState *env,
> > DisasContext *ctx, int *is_branch)
> > break;
> > case OPC_DIV_G_2F:
> > case OPC_DIVU_G_2F:
> > - case OPC_MULT_G_2F:
> > case OPC_MULTU_G_2F:
> > case OPC_MOD_G_2F:
> > case OPC_MODU_G_2F:
> > check_insn(env, ctx, INSN_LOONGSON2F);
> > gen_loongson_integer(ctx, op1, rd, rs, rt);
> > break;
> > + case OPC_MULT_G_2F:
> > + if (!TARGET_OCTEON) {
> > + check_insn(env, ctx, INSN_LOONGSON2F);
> > + gen_loongson_integer(ctx, op1, rd, rs, rt);
> > + } else {
> > +#if defined(TARGET_MIPS64)
> > + /* Cavium Specific vmm0 */
> > + check_mips_64(ctx);
> > + gen_LMI(env, ctx, op1, rs, rt, rd);
> > +#endif
> > + }
> > + break;
> > #if defined(TARGET_MIPS64)
> > case OPC_DCLO:
> > case OPC_DCLZ:
> > @@ -11892,7 +12449,6 @@ static void decode_opc (CPUState *env,
> DisasContext
> > *ctx, int *is_branch)
> > check_mips_64(ctx);
> > gen_cl(ctx, op1, rd, rs);
> > break;
> > - case OPC_DMULT_G_2F:
> > case OPC_DMULTU_G_2F:
> > case OPC_DDIV_G_2F:
> > case OPC_DDIVU_G_2F:
> > @@ -11901,6 +12457,39 @@ static void decode_opc (CPUState *env,
> DisasContext
> > *ctx, int *is_branch)
> > check_insn(env, ctx, INSN_LOONGSON2F);
> > gen_loongson_integer(ctx, op1, rd, rs, rt);
> > break;
> > + case OPC_DMULT_G_2F:
> > + if (!TARGET_OCTEON) {
> > + check_insn(env, ctx, INSN_LOONGSON2F);
> > + gen_loongson_integer(ctx, op1, rd, rs, rt);
> > + } else {
> > + /* Cavium Specific instruction v3mulu */
> > + check_mips_64(ctx);
> > + gen_LMI(env, ctx, op1, rs, rt, rd);
> > + }
> > + break;
> > + case OPC_SEQ:
> > + check_mips_64(ctx);
> > + gen_seqsne(ctx, op1, rd, rs, rt);
> > + break;
> > + case OPC_SNE:
> > + check_mips_64(ctx);
> > + gen_seqsne(ctx, op1, rd, rs, rt);
> > + break;
> > + case OPC_SEQI:
> > + check_mips_64(ctx);
> > + gen_set_imm(env, op1, rt, rs, imm10);
> > + break;
> > + case OPC_SNEI:
> > + check_mips_64(ctx);
> > + gen_set_imm(env, op1, rt, rs, imm10);
> > + break;
> > + case OPC_POP:
> > + insn_opc_pop(ctx, env, op1, rd, rs, rt);
> > + break;
> > + case OPC_DPOP:
> > + check_mips_64(ctx);
> > + insn_opc_dpop(ctx, env, op1, rd, rs, rt);
> > + break;
> > #endif
> > default: /* Invalid */
> > MIPS_INVAL("special2");
> > @@ -12192,10 +12781,32 @@ static void decode_opc (CPUState *env,
> > DisasContext *ctx, int *is_branch)
> > break;
> >
> > /* COP2. */
> > - case OPC_LWC2:
> > - case OPC_LDC2:
> > - case OPC_SWC2:
> > - case OPC_SDC2:
> > + /* Conflicting opcodes with Cavium specific branch instructions
> > + if TARGET_OCTEON is set these opcodes will belong to Cavium */
> > + case OPC_LWC2: /*BBIT0*/
> > + if(TARGET_OCTEON) {
> > + gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
> > + *is_branch = 1;
> > + break;
> > + }
> > + case OPC_LDC2: /*BBIT032*/
> > + if(TARGET_OCTEON) {
> > + gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
> > + *is_branch = 1;
> > + break;
> > + }
> > + case OPC_SWC2: /*BBIT1*/
> > + if(TARGET_OCTEON) {
> > + gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
> > + *is_branch = 1;
> > + break;
> > + }
> > + case OPC_SDC2: /*BBIT132*/
> > + if(TARGET_OCTEON) {
> > + gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
> > + *is_branch = 1;
> > + break;
> > + }
> > case OPC_CP2:
> > /* COP2: Not implemented. */
> > generate_exception_err(ctx, EXCP_CpU, 2);
> > @@ -12584,6 +13195,18 @@ static void mips_tcg_init(void)
> > cpu_dspctrl = tcg_global_mem_new(TCG_AREG0,
> > offsetof(CPUState,
> > active_tc.DSPControl),
> > "DSPControl");
> > + mpl0 = tcg_global_mem_new(TCG_AREG0,
> > + offsetof(CPUState, Reg.MPL0), "MPL0");
> > + mpl1 = tcg_global_mem_new(TCG_AREG0,
> > + offsetof(CPUState, Reg.MPL1), "MPL1");
> > + mpl2 = tcg_global_mem_new(TCG_AREG0,
> > + offsetof(CPUState, Reg.MPL2), "MPL2");
> > + p0 = tcg_global_mem_new(TCG_AREG0,
> > + offsetof(CPUState, Reg.P0), "P0");
> > + p1 = tcg_global_mem_new(TCG_AREG0,
> > + offsetof(CPUState, Reg.P1), "P1");
> > + p2 = tcg_global_mem_new(TCG_AREG0,
> > + offsetof(CPUState, Reg.P2), "P2");
> > bcond = tcg_global_mem_new(TCG_AREG0,
> > offsetof(CPUState, bcond), "bcond");
> > btarget = tcg_global_mem_new(TCG_AREG0,
> > @@ -12607,6 +13230,18 @@ static void mips_tcg_init(void)
> >
> > #include "translate_init.c"
> >
> > +#if defined(TARGET_MIPS64)
> > +
> > +static void set_cvmctl_register(CPUMIPSState *env)
> > +{
> > + env->CvmCtlRegister.cvmctl = env->CvmCtlRegister.cvmctl
> > + ^ env->CvmCtlRegister.cvmctl;
> > + env->CvmCtlRegister.cvmctl =
> > FUSE_START_BIT(env->CvmCtlRegister.cvmctl);
> > + env->CvmCtlRegister.cvmctl = KASUMI(env->CvmCtlRegister.cvmctl);
> > + env->CvmCtlRegister.cvmctl = IPPCI(env->CvmCtlRegister.cvmctl);
> > + env->CvmCtlRegister.cvmctl = IPTI(env->CvmCtlRegister.cvmctl);
> > +}
> > +#endif
> > CPUMIPSState *cpu_mips_init (const char *cpu_model)
> > {
> > CPUMIPSState *env;
> > @@ -12619,6 +13254,10 @@ CPUMIPSState *cpu_mips_init (const char
> *cpu_model)
> > env->cpu_model = def;
> > env->cpu_model_str = cpu_model;
> >
> > +#if defined(TARGET_MIPS64)
> > + /*Function for setting cvmctl register*/
> > + set_cvmctl_register(env);
> > +#endif
> > cpu_exec_init(env);
> > #ifndef CONFIG_USER_ONLY
> > mmu_init(env, def);
> > --
> > 1.7.3.4
>
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^ permalink raw reply
* Re: Enabling/disabling the GPS part of a Huawei EM770W
From: roeland @ 2011-04-09 8:37 UTC (permalink / raw)
To: ofono
In-Reply-To: <4C6566DF.1020404@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 339 bytes --]
Denis Kenzior <denkenz@...> writes:
> I've added a task for this to the oFono TODO list. As Marcel mentioned,
> if you wish to have a crack at it, feel free to assign yourself the Owner.
>
> Regards,
> -Denis
>
i've found the method of how to enable it.. but the method to disable it eludes
me..
Regards
Roeland
^ permalink raw reply
* [Qemu-devel] Re: [PATCH] ioapic: when switches to level trigger mode, interrupts raised repeatedly.
From: Jan Kiszka @ 2011-04-09 8:38 UTC (permalink / raw)
To: Isaku Yamahata; +Cc: qemu-devel, Aurelien Jarno
In-Reply-To: <20110404021511.GF11748@valinux.co.jp>
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On 2011-04-04 04:15, Isaku Yamahata wrote:
> On Mon, Apr 04, 2011 at 08:42:07AM +0900, Isaku Yamahata wrote:
>> > Thank you for applying. But I found that the patch is wrong and
>> > I'm preparing the new one. Can you please revert it?
> Here is the corrected patch. The first wrong patch clears the interrupts
> bit unconditionally. Which caused losing interrupt.
>
> From 5ed177d35ab14f3b070a0eba2c49400279a3a14b Mon Sep 17 00:00:00 2001
> Message-Id: <5ed177d35ab14f3b070a0eba2c49400279a3a14b.1301883258.git.yamahata@valinux.co.jp>
> In-Reply-To: <cover.1301883258.git.yamahata@valinux.co.jp>
> References: <cover.1301883258.git.yamahata@valinux.co.jp>
> From: Isaku Yamahata <yamahata@valinux.co.jp>
> Date: Wed, 16 Mar 2011 14:00:13 +0900
> Subject: [PATCH 01/30] ioapic: when switches to level trigger mode, interrupts raised repeatedly.
>
> - the trigger mode is edge at first by reset.
> - During initializatoin, the interrupt is raised as edge which is masked.
> The corresponding bit of irr is set.
...and that is the actual problem. The spec says: "Interrupt Mask—R/W.
When this bit is 1, the interrupt signal is masked. Edge-sensitive
interrupts signaled on a masked interrupt pin are ignored (i.e., not
delivered or held pending)."
So this should do the trick in a correct way (untested, please
validate):
diff --git a/hw/ioapic.c b/hw/ioapic.c
index 569327d..6663f41 100644
--- a/hw/ioapic.c
+++ b/hw/ioapic.c
@@ -161,7 +161,7 @@ static void ioapic_set_irq(void *opaque, int vector, int level)
}
} else {
/* edge triggered */
- if (level) {
+ if (level && !(entry & IOAPIC_LVT_MASKED)) {
s->irr |= mask;
ioapic_service(s);
}
Jan
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* Re: A question of grant table version
From: Ian Campbell @ 2011-04-09 8:43 UTC (permalink / raw)
To: hotmaim; +Cc: xen-devel@lists.xensource.com
In-Reply-To: <BLU0-SMTP117A7A1DBE55736C2667910DAA60@phx.gbl>
On Sat, 2011-04-09 at 02:28 +0100, hotmaim wrote:
> Hi
>
> I have a question on grant table version.
> In 2.6.31 pvops kernel, there is a gnttab_request_version to request using version 2.
> But this cannot be found in 2.6.3236 pvops kernel, that is it uses version 1.
>
> So, the fact is newer kernel use older grant table version, it doesn,t make sense to me.
> Could someone comfirm it is on purpose?
Unless you specifically need the new functionality of grant table v2
(transitive grants or sub page grants) there is no difference/benefit
between v1 and v2.
The only user of that new functionality was netchannel2, which has not
been carried forward from 2.6.31 and hence current kernels still use v1
grant tables with no loss of functionality.
People are working on introducing the interesting features of
netchannel2 as protocol extensions to netchannel1 and it is likely that
this will also involve reintroducing the use of grant table v2 in newer
kernels.
Ian.
^ permalink raw reply
* Re: switching "balance" into background
From: Hugo Mills @ 2011-04-09 8:44 UTC (permalink / raw)
To: helmut; +Cc: linux-btrfs
In-Reply-To: <BjW+ECVD1uB@helmut.hullen.de>
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On Sat, Apr 09, 2011 at 07:57:00AM +0200, Helmut Hullen wrote:
> Hallo, linux-btrfs,
>
> I can't switch a running "btrfs filesystem balance ..." via
>
> ctrl z
> bg
>
> into the background, with other jobs this way works.
>
> The stopping command "ctrl z" doesn't work.
>
> (may be on other keyboards it's "ctrl y")
>
> What goes wrong?
A balance is a single long-lived ioctl call, so the userspace
process is living in D state (uninterruptible sleep) until the kernel
finishes.
I've got a patch that forks the process, and runs the ioctl in the
background, returning immediately. I should be able to get it to the
list this weekend as part of the userspace side of the balance
management patches.
Hugo.
--
=== Hugo Mills: hugo@... carfax.org.uk | darksatanic.net | lug.org.uk ===
PGP key: 515C238D from wwwkeys.eu.pgp.net or http://www.carfax.org.uk
--- There are three things you should never see being made: laws, ---
standards, and sausages.
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^ permalink raw reply
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