* Re: [PATCH] net/fm10k/base: add a break statement
From: Chen, Jing D @ 2016-12-22 5:22 UTC (permalink / raw)
To: Chenghu Yao; +Cc: dev@dpdk.org
In-Reply-To: <1482289505-47591-1-git-send-email-yao.chenghu@zte.com.cn>
Hi, Chenghu,
> -----Original Message-----
> From: Chenghu Yao [mailto:yao.chenghu@zte.com.cn]
> Sent: Wednesday, December 21, 2016 11:05 AM
> To: Chen, Jing D <jing.d.chen@intel.com>
> Cc: dev@dpdk.org; Chenghu Yao <yao.chenghu@zte.com.cn>
> Subject: [PATCH] net/fm10k/base: add a break statement
>
> In function fm10k_mbx_create_reply(), the last case branch
> has no break statement.
>
> Signed-off-by: Chenghu Yao <yao.chenghu@zte.com.cn>
> ---
> drivers/net/fm10k/base/fm10k_mbx.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/net/fm10k/base/fm10k_mbx.c
> b/drivers/net/fm10k/base/fm10k_mbx.c
> index 2e70434..45d6ddb 100644
> --- a/drivers/net/fm10k/base/fm10k_mbx.c
> +++ b/drivers/net/fm10k/base/fm10k_mbx.c
> @@ -1084,6 +1084,7 @@ STATIC s32 fm10k_mbx_create_reply(struct fm10k_hw
> *hw,
> case FM10K_STATE_CLOSED:
> /* generate new header based on data */
> fm10k_mbx_create_disconnect_hdr(mbx);
> + break;
> default:
> break;
> }
Thanks for contributing code. But there are 2 problems here.
1. You are modifying base code under 'base' directory. It assumed READ ONLY because
there is another Intel team are maintaining it.
2. Without your change, the code won't have any negative effect. Yes, I appreciate your
change to make it stronger.
So, I'd to say 'NAC' for this patch.
^ permalink raw reply
* [PATCH 3/3] sixaxis: Set created devices trusted by default
From: Juha Kuikka @ 2016-12-22 5:20 UTC (permalink / raw)
To: linux-bluetooth; +Cc: Juha Kuikka
In-Reply-To: <1482384054-59718-1-git-send-email-juha.kuikka@synapse.com>
If user has enabled the sixaxis plugin and plugs a controller in,
it can be assumed they also want the controllers to be able to connect
automatically.
---
plugins/sixaxis.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/plugins/sixaxis.c b/plugins/sixaxis.c
index 1fb2091..ba96b54 100644
--- a/plugins/sixaxis.c
+++ b/plugins/sixaxis.c
@@ -349,6 +349,7 @@ static bool setup_device(int fd, int index, struct btd_adapter *adapter)
btd_device_set_pnpid(device, devices[index].source, devices[index].vid,
devices[index].pid, devices[index].version);
btd_device_set_temporary(device, false);
+ btd_device_set_trusted(device, true);
return true;
}
--
1.9.1
^ permalink raw reply related
* [PATCH 2/3] sixaxis: Add support for pairing DS4 over USB
From: Juha Kuikka @ 2016-12-22 5:20 UTC (permalink / raw)
To: linux-bluetooth; +Cc: Juha Kuikka
In-Reply-To: <1482384054-59718-1-git-send-email-juha.kuikka@synapse.com>
This patch adds support for "pairing" a Dualshock4 controller over USB
into the sixaxis plugin.
Pairing is in quotes because we cannot do real bonding due to lack of
API of setting link keys from the plugin so instead we just tell the
controller that we are the master and to connect to us.
Actual bonding happens on first connection per usual.
This patch is based on information from sixpair tool.
---
plugins/sixaxis.c | 86 ++++++++++++++++++++++++++++++++++++++++++-------------
1 file changed, 66 insertions(+), 20 deletions(-)
diff --git a/plugins/sixaxis.c b/plugins/sixaxis.c
index fcc93bc..1fb2091 100644
--- a/plugins/sixaxis.c
+++ b/plugins/sixaxis.c
@@ -69,6 +69,20 @@ static const struct {
.pid = 0x042f,
.version = 0x0000,
},
+ {
+ .name = "Wireless Controller",
+ .source = 0x0002,
+ .vid = 0x054c,
+ .pid = 0x05c4,
+ .version = 0x0001,
+ },
+ {
+ .name = "Wireless Controller",
+ .source = 0x0002,
+ .vid = 0x054c,
+ .pid = 0x09cc,
+ .version = 0x0001,
+ },
};
struct leds_data {
@@ -86,57 +100,89 @@ static struct udev *ctx = NULL;
static struct udev_monitor *monitor = NULL;
static guint watch_id = 0;
-static int get_device_bdaddr(int fd, bdaddr_t *bdaddr)
+static bool is_dualshock4(int index)
+{
+ return devices[index].pid == 0x05c4 || devices[index].pid == 0x09cc;
+}
+
+static int get_device_bdaddr(int fd, int index, bdaddr_t *bdaddr)
{
uint8_t buf[18];
- int ret;
+ int ret, report_length;
memset(buf, 0, sizeof(buf));
- buf[0] = 0xf2;
+ if (is_dualshock4(index)) {
+ report_length = 7;
+ buf[0] = 0x81;
+ } else {
+ report_length = 18;
+ buf[0] = 0xf2;
+ }
- ret = ioctl(fd, HIDIOCGFEATURE(sizeof(buf)), buf);
+ ret = ioctl(fd, HIDIOCGFEATURE(report_length), buf);
if (ret < 0) {
error("sixaxis: failed to read device address (%s)",
strerror(errno));
return ret;
}
- baswap(bdaddr, (bdaddr_t *) (buf + 4));
+ if (is_dualshock4(index))
+ memcpy(bdaddr->b, buf + 1, 6); // little-endian on DS4
+ else
+ baswap(bdaddr, (bdaddr_t *) (buf + 4));
return 0;
}
-static int get_master_bdaddr(int fd, bdaddr_t *bdaddr)
+static int get_master_bdaddr(int fd, int index, bdaddr_t *bdaddr)
{
- uint8_t buf[8];
- int ret;
+ uint8_t buf[16];
+ int ret, report_length;
memset(buf, 0, sizeof(buf));
- buf[0] = 0xf5;
+ if (is_dualshock4(index)) {
+ report_length = 16;
+ buf[0] = 0x12;
+ } else {
+ report_length = 8;
+ buf[0] = 0xf5;
+ }
- ret = ioctl(fd, HIDIOCGFEATURE(sizeof(buf)), buf);
+ ret = ioctl(fd, HIDIOCGFEATURE(report_length), buf);
if (ret < 0) {
error("sixaxis: failed to read master address (%s)",
strerror(errno));
return ret;
}
- baswap(bdaddr, (bdaddr_t *) (buf + 2));
+ if (is_dualshock4(index))
+ memcpy(bdaddr->b, buf + 10, 6); // little-endian on DS4
+ else
+ baswap(bdaddr, (bdaddr_t *) (buf + 2));
return 0;
}
-static int set_master_bdaddr(int fd, const bdaddr_t *bdaddr)
+static int set_master_bdaddr(int fd, int index, const bdaddr_t *bdaddr)
{
- uint8_t buf[8];
- int ret;
+ uint8_t buf[23];
+ int ret, report_length;
- buf[0] = 0xf5;
- buf[1] = 0x01;
+ if (is_dualshock4(index)) {
+ report_length = 23;
- baswap((bdaddr_t *) (buf + 2), bdaddr);
+ buf[0] = 0x13;
+ memcpy(buf + 1, bdaddr->b, 6);
+ memset(buf + 7, 0, 16); /* TODO: we could put the key here but there is no way to force a re-loading of link keys to the kernel */
+ } else {
+ report_length = 8;
+
+ buf[0] = 0xf5;
+ buf[1] = 0x01;
+ baswap((bdaddr_t *) (buf + 2), bdaddr);
+ }
ret = ioctl(fd, HIDIOCSFEATURE(sizeof(buf)), buf);
if (ret < 0)
@@ -262,10 +308,10 @@ static bool setup_device(int fd, int index, struct btd_adapter *adapter)
const bdaddr_t *adapter_bdaddr;
struct btd_device *device;
- if (get_device_bdaddr(fd, &device_bdaddr) < 0)
+ if (get_device_bdaddr(fd, index, &device_bdaddr) < 0)
return false;
- if (get_master_bdaddr(fd, &master_bdaddr) < 0)
+ if (get_master_bdaddr(fd, index, &master_bdaddr) < 0)
return false;
/* This can happen if controller was plugged while already connected
@@ -279,7 +325,7 @@ static bool setup_device(int fd, int index, struct btd_adapter *adapter)
adapter_bdaddr = btd_adapter_get_address(adapter);
if (bacmp(adapter_bdaddr, &master_bdaddr)) {
- if (set_master_bdaddr(fd, adapter_bdaddr) < 0)
+ if (set_master_bdaddr(fd, index, adapter_bdaddr) < 0)
return false;
}
--
1.9.1
^ permalink raw reply related
* [PATCH 1/3] Add new DS4 controller PID into special case handler
From: Juha Kuikka @ 2016-12-22 5:20 UTC (permalink / raw)
To: linux-bluetooth; +Cc: Juha Kuikka
In-Reply-To: <1482384054-59718-1-git-send-email-juha.kuikka@synapse.com>
There is a special path for various game controllers where they connect
to the hid service before bluetoothd knows what they are.
This patch adds another PID for the Dualshock4 controller.
---
profiles/input/server.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/profiles/input/server.c b/profiles/input/server.c
index eb3fcf8..61f084a 100644
--- a/profiles/input/server.c
+++ b/profiles/input/server.c
@@ -136,7 +136,7 @@ static bool dev_is_sixaxis(const bdaddr_t *src, const bdaddr_t *dst)
return true;
/* DualShock 4 */
- if (vid == 0x054c && pid == 0x05c4)
+ if (vid == 0x054c && (pid == 0x05c4 || pid == 0x09cc))
return true;
/* Navigation Controller */
--
1.9.1
^ permalink raw reply related
* [PATCH 0/3] Dualshock4 controller enhancements
From: Juha Kuikka @ 2016-12-22 5:20 UTC (permalink / raw)
To: linux-bluetooth; +Cc: Juha Kuikka
This patch set contains enhancements for the Dualshock4 controller.
There are now two Dualshock4 PIDs out there, add second one to
special case handler.
Modify sixaxis plugin to add support for pairing DS4 controllers over USB.
The HID report also allows for the link key to be set but since there is
currently no API to set it from the plugins, this has not been implemented.
Because of this the DS4 will connect to the bluez host automatically but
the bonding still has to happen over the bluetooth connection as normal.
Also set connected controllers "paired" by default. This allows for hands-free
connection to bluez host.
Juha Kuikka (3):
Add new DS4 controller PID into special case handler
sixaxis: Add support for pairing DS4 over USB
sixaxis: Set created devices trusted by default
plugins/sixaxis.c | 87 +++++++++++++++++++++++++++++++++++++------------
profiles/input/server.c | 2 +-
2 files changed, 68 insertions(+), 21 deletions(-)
--
1.9.1
^ permalink raw reply
* Re: [PATCH 2/2] net: wireless: fix to uses struct
From: kbuild test robot @ 2016-12-22 5:18 UTC (permalink / raw)
To: Ozgur Karatas
Cc: kbuild-all, johannes, David Miller, linux-wireless, netdev,
linux-kernel
In-Reply-To: <608881482358981@web17g.yandex.ru>
[-- Attachment #1: Type: text/plain, Size: 2098 bytes --]
Hi Ozgur,
[auto build test ERROR on mac80211-next/master]
[also build test ERROR on v4.9 next-20161221]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Ozgur-Karatas/net-wireless-fixed-to-checkpatch-errors/20161222-125128
base: https://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git master
config: i386-randconfig-x006-201651 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
net/wireless/reg.c: In function 'regulatory_hint_core':
>> net/wireless/reg.c:2294:28: error: 'regulatory_request' undeclared (first use in this function)
request = kzalloc(sizeof(*regulatory_request), GFP_KERNEL);
^~~~~~~~~~~~~~~~~~
net/wireless/reg.c:2294:28: note: each undeclared identifier is reported only once for each function it appears in
net/wireless/reg.c: In function 'regulatory_hint_user':
net/wireless/reg.c:2316:28: error: 'regulatory_request' undeclared (first use in this function)
request = kzalloc(sizeof(*regulatory_request), GFP_KERNEL);
^~~~~~~~~~~~~~~~~~
net/wireless/reg.c: In function 'regulatory_hint':
net/wireless/reg.c:2388:28: error: 'regulatory_request' undeclared (first use in this function)
request = kzalloc(sizeof(*regulatory_request), GFP_KERNEL);
^~~~~~~~~~~~~~~~~~
vim +/regulatory_request +2294 net/wireless/reg.c
2288 * and when we restore regulatory settings.
2289 */
2290 static int regulatory_hint_core(const char *alpha2)
2291 {
2292 struct regulatory_request *request;
2293
> 2294 request = kzalloc(sizeof(*regulatory_request), GFP_KERNEL);
2295 if (!request)
2296 return -ENOMEM;
2297
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 23376 bytes --]
^ permalink raw reply
* Re: x86: warning in unwind_get_return_address
From: Josh Poimboeuf @ 2016-12-22 5:17 UTC (permalink / raw)
To: Andrey Konovalov
Cc: syzkaller, Andrey Ryabinin, Alexander Potapenko, Dmitry Vyukov,
kasan-dev, linux-mm, LKML, Thomas Gleixner, Ingo Molnar,
H. Peter Anvin, x86, Kostya Serebryany
In-Reply-To: <CAAeHK+yPSeO2PWQtsQs_7FQ0PeGzs4PgK_89UM8G=hFJrVzH1g@mail.gmail.com>
On Wed, Dec 21, 2016 at 01:46:36PM +0100, Andrey Konovalov wrote:
> On Wed, Dec 21, 2016 at 12:36 AM, Josh Poimboeuf <jpoimboe@redhat.com> wrote:
> >
> > Thanks. Looking at the stack trace, my guess is that an interrupt hit
> > while running in generated BPF code, and the unwinder got confused
> > because regs->ip points to the generated code. I may need to disable
> > that warning until we figure out a better solution.
> >
> > Can you share your .config file?
>
> Sure, attached.
Ok, I was able to recreate with your config. The culprit was generated
code, as I suspected, though it wasn't BPF, it was a kprobe (created by
dccpprobe_init()).
I'll make a patch to disable the warning.
--
Josh
^ permalink raw reply
* Re: x86: warning in unwind_get_return_address
From: Josh Poimboeuf @ 2016-12-22 5:17 UTC (permalink / raw)
To: Andrey Konovalov
Cc: syzkaller, Andrey Ryabinin, Alexander Potapenko, Dmitry Vyukov,
kasan-dev, linux-mm, LKML, Thomas Gleixner, Ingo Molnar,
H. Peter Anvin, x86, Kostya Serebryany
In-Reply-To: <CAAeHK+yPSeO2PWQtsQs_7FQ0PeGzs4PgK_89UM8G=hFJrVzH1g@mail.gmail.com>
On Wed, Dec 21, 2016 at 01:46:36PM +0100, Andrey Konovalov wrote:
> On Wed, Dec 21, 2016 at 12:36 AM, Josh Poimboeuf <jpoimboe@redhat.com> wrote:
> >
> > Thanks. Looking at the stack trace, my guess is that an interrupt hit
> > while running in generated BPF code, and the unwinder got confused
> > because regs->ip points to the generated code. I may need to disable
> > that warning until we figure out a better solution.
> >
> > Can you share your .config file?
>
> Sure, attached.
Ok, I was able to recreate with your config. The culprit was generated
code, as I suspected, though it wasn't BPF, it was a kprobe (created by
dccpprobe_init()).
I'll make a patch to disable the warning.
--
Josh
--
To unsubscribe, send a message with 'unsubscribe linux-mm' in
the body to majordomo@kvack.org. For more info on Linux MM,
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^ permalink raw reply
* Re: [4.10, panic, regression] iscsi: null pointer deref at iscsi_tcp_segment_done+0x20d/0x2e0
From: Dave Chinner @ 2016-12-22 5:13 UTC (permalink / raw)
To: Chris Leech, Linus Torvalds, Linux Kernel Mailing List,
Lee Duncan, open-iscsi, Linux SCSI List, linux-block,
Christoph Hellwig
In-Reply-To: <20161222001303.nvrtm22szn3hgxar@straylight.hirudinean.org>
On Wed, Dec 21, 2016 at 04:13:03PM -0800, Chris Leech wrote:
> On Wed, Dec 21, 2016 at 03:19:15PM -0800, Linus Torvalds wrote:
> > Hi,
> >
> > On Wed, Dec 21, 2016 at 2:16 PM, Dave Chinner <david@fromorbit.com> wrote:
> > > On Fri, Dec 16, 2016 at 10:59:06AM -0800, Chris Leech wrote:
> > >> Thanks Dave,
> > >>
> > >> I'm hitting a bug at scatterlist.h:140 before I even get any iSCSI
> > >> modules loaded (virtio block) so there's something else going on in the
> > >> current merge window. I'll keep an eye on it and make sure there's
> > >> nothing iSCSI needs fixing for.
> > >
> > > OK, so before this slips through the cracks.....
> > >
> > > Linus - your tree as of a few minutes ago still panics immediately
> > > when starting xfstests on iscsi devices. It appears to be a
> > > scatterlist corruption and not an iscsi problem, so the iscsi guys
> > > seem to have bounced it and no-one is looking at it.
> >
> > Hmm. There's not much to go by.
> >
> > Can somebody in iscsi-land please try to just bisect it - I'm not
> > seeing a lot of clues to where this comes from otherwise.
>
> Yeah, my hopes of this being quickly resolved by someone else didn't
> work out and whatever is going on in that test VM is looking like a
> different kind of odd. I'm saving that off for later, and seeing if I
> can't be a bisect on the iSCSI issue.
There may be deeper issues. I just started running scalability tests
(e.g. 16-way fsmark create tests) and about a minute in I got a
directory corruption reported - something I hadn't seen in the dev
cycle at all. I unmounted the fs, mkfs'd it again, ran the
workload again and about a minute in this fired:
[628867.607417] ------------[ cut here ]------------
[628867.608603] WARNING: CPU: 2 PID: 16925 at mm/workingset.c:461 shadow_lru_isolate+0x171/0x220
[628867.610702] Modules linked in:
[628867.611375] CPU: 2 PID: 16925 Comm: kworker/2:97 Tainted: G W 4.9.0-dgc #18
[628867.613382] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Debian-1.8.2-1 04/01/2014
[628867.616179] Workqueue: events rht_deferred_worker
[628867.632422] Call Trace:
[628867.634691] dump_stack+0x63/0x83
[628867.637937] __warn+0xcb/0xf0
[628867.641359] warn_slowpath_null+0x1d/0x20
[628867.643362] shadow_lru_isolate+0x171/0x220
[628867.644627] __list_lru_walk_one.isra.11+0x79/0x110
[628867.645780] ? __list_lru_init+0x70/0x70
[628867.646628] list_lru_walk_one+0x17/0x20
[628867.647488] scan_shadow_nodes+0x34/0x50
[628867.648358] shrink_slab.part.65.constprop.86+0x1dc/0x410
[628867.649506] shrink_node+0x57/0x90
[628867.650233] do_try_to_free_pages+0xdd/0x230
[628867.651157] try_to_free_pages+0xce/0x1a0
[628867.652342] __alloc_pages_slowpath+0x2df/0x960
[628867.653332] ? __might_sleep+0x4a/0x80
[628867.654148] __alloc_pages_nodemask+0x24b/0x290
[628867.655237] kmalloc_order+0x21/0x50
[628867.656016] kmalloc_order_trace+0x24/0xc0
[628867.656878] __kmalloc+0x17d/0x1d0
[628867.657644] bucket_table_alloc+0x195/0x1d0
[628867.658564] ? __might_sleep+0x4a/0x80
[628867.659449] rht_deferred_worker+0x287/0x3c0
[628867.660366] ? _raw_spin_unlock_irq+0xe/0x30
[628867.661294] process_one_work+0x1de/0x4d0
[628867.662208] worker_thread+0x4b/0x4f0
[628867.662990] kthread+0x10c/0x140
[628867.663687] ? process_one_work+0x4d0/0x4d0
[628867.664564] ? kthread_create_on_node+0x40/0x40
[628867.665523] ret_from_fork+0x25/0x30
[628867.666317] ---[ end trace 7c38634006a9955e ]---
Now, this workload does not touch the page cache at all - it's
entirely an XFS metadata workload, so it should not really be
affecting the working set code.
And worse, on that last error, the /host/ is now going into meltdown
(running 4.7.5) with 32 CPUs all burning down in ACPI code:
PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND
35074 root -2 0 0 0 0 R 99.0 0.0 12:38.92 acpi_pad/12
35079 root -2 0 0 0 0 R 99.0 0.0 12:39.40 acpi_pad/16
35080 root -2 0 0 0 0 R 99.0 0.0 12:39.29 acpi_pad/17
35085 root -2 0 0 0 0 R 99.0 0.0 12:39.35 acpi_pad/22
35087 root -2 0 0 0 0 R 99.0 0.0 12:39.13 acpi_pad/24
35090 root -2 0 0 0 0 R 99.0 0.0 12:38.89 acpi_pad/27
35093 root -2 0 0 0 0 R 99.0 0.0 12:38.88 acpi_pad/30
35063 root -2 0 0 0 0 R 98.1 0.0 12:40.64 acpi_pad/1
35065 root -2 0 0 0 0 R 98.1 0.0 12:40.38 acpi_pad/3
35066 root -2 0 0 0 0 R 98.1 0.0 12:40.30 acpi_pad/4
35067 root -2 0 0 0 0 R 98.1 0.0 12:40.82 acpi_pad/5
35077 root -2 0 0 0 0 R 98.1 0.0 12:39.65 acpi_pad/14
35078 root -2 0 0 0 0 R 98.1 0.0 12:39.58 acpi_pad/15
35081 root -2 0 0 0 0 R 98.1 0.0 12:39.32 acpi_pad/18
35072 root -2 0 0 0 0 R 96.2 0.0 12:40.14 acpi_pad/10
35073 root -2 0 0 0 0 R 96.2 0.0 12:39.39 acpi_pad/11
35076 root -2 0 0 0 0 R 96.2 0.0 12:39.39 acpi_pad/13
35084 root -2 0 0 0 0 R 96.2 0.0 12:39.06 acpi_pad/21
35092 root -2 0 0 0 0 R 96.2 0.0 12:39.14 acpi_pad/29
35069 root -2 0 0 0 0 R 95.2 0.0 12:40.71 acpi_pad/7
35068 root -2 0 0 0 0 R 94.2 0.0 12:40.29 acpi_pad/6
35062 root -2 0 0 0 0 D 93.3 0.0 12:40.56 acpi_pad/0
35064 root -2 0 0 0 0 D 92.3 0.0 12:40.18 acpi_pad/2
35082 root -2 0 0 0 0 R 92.3 0.0 12:39.64 acpi_pad/19
35083 root -2 0 0 0 0 R 92.3 0.0 12:38.98 acpi_pad/20
35086 root -2 0 0 0 0 R 92.3 0.0 12:40.11 acpi_pad/23
35088 root -2 0 0 0 0 R 92.3 0.0 12:39.45 acpi_pad/25
35089 root -2 0 0 0 0 R 92.3 0.0 12:39.11 acpi_pad/26
35070 root -2 0 0 0 0 D 91.3 0.0 12:40.21 acpi_pad/8
35071 root -2 0 0 0 0 D 91.3 0.0 12:39.98 acpi_pad/9
35091 root -2 0 0 0 0 D 91.3 0.0 12:39.33 acpi_pad/28
perf top says:
65.98% [kernel] [k] power_saving_thread
3.27% [kernel] [k] native_queued_spin_lock_slowpath
1.61% [kernel] [k] native_write_msr
1.39% [kernel] [k] update_curr_rt
1.20% [kernel] [k] intel_pstate_update_util
1.01% [kernel] [k] __do_softirq
1.01% [kernel] [k] ktime_get
0.99% [kernel] [k] ktime_get_update_offsets_now
0.93% [kernel] [k] rcu_check_callbacks
0.90% [kernel] [k] _raw_spin_lock
0.88% [kernel] [k] perf_event_task_tick
0.82% [kernel] [k] native_irq_return_iret
0.81% [kernel] [k] run_timer_softirq
0.75% [kernel] [k] trigger_load_balance
No idea how to recover this, so I'm just going to reboot it. Back in
a bit.
Cheers,
Dave.
--
Dave Chinner
david@fromorbit.com
^ permalink raw reply
* [linux-4.1 test] 103784: regressions - trouble: broken/fail/pass
From: osstest service owner @ 2016-12-22 5:12 UTC (permalink / raw)
To: xen-devel, osstest-admin
[-- Attachment #1: Type: text/plain, Size: 22277 bytes --]
flight 103784 linux-4.1 real [real]
http://logs.test-lab.xenproject.org/osstest/logs/103784/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-xl 6 xen-boot fail REGR. vs. 101737
test-amd64-amd64-qemuu-nested-intel 6 xen-boot fail REGR. vs. 101737
test-amd64-i386-pair 9 xen-boot/src_host fail REGR. vs. 101737
test-amd64-i386-pair 10 xen-boot/dst_host fail REGR. vs. 101737
test-amd64-i386-xl-qemuu-debianhvm-amd64-xsm 6 xen-boot fail REGR. vs. 101737
test-amd64-amd64-xl-qemuu-winxpsp3 6 xen-boot fail REGR. vs. 101737
test-amd64-amd64-xl-qemut-debianhvm-amd64-xsm 6 xen-boot fail REGR. vs. 101737
test-amd64-i386-freebsd10-amd64 6 xen-boot fail REGR. vs. 101737
test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 6 xen-boot fail REGR. vs. 101737
build-armhf-pvops 5 kernel-build fail in 102733 REGR. vs. 101737
test-amd64-i386-xl-qemut-win7-amd64 6 xen-boot fail in 103749 REGR. vs. 101737
test-amd64-amd64-xl-pvh-intel 6 xen-boot fail in 103749 REGR. vs. 101737
test-amd64-amd64-xl-multivcpu 6 xen-boot fail in 103749 REGR. vs. 101737
Tests which are failing intermittently (not blocking):
test-amd64-i386-xl-qemut-winxpsp3 3 host-install(3) broken in 103011 pass in 103784
test-amd64-i386-xl 3 host-install(3) broken in 103011 pass in 103784
test-amd64-amd64-xl-qemut-win7-amd64 3 host-install(3) broken in 103011 pass in 103784
test-amd64-amd64-xl-qemuu-win7-amd64 3 host-install(3) broken in 103011 pass in 103784
test-amd64-i386-xl-qemut-winxpsp3-vcpus1 3 host-install(3) broken in 103011 pass in 103784
test-amd64-i386-xl-qemut-stubdom-debianhvm-amd64-xsm 3 host-install(3) broken in 103740 pass in 103784
test-amd64-i386-xl-qemuu-ovmf-amd64 3 host-install(3) broken in 103740 pass in 103784
test-amd64-amd64-xl-qcow2 3 host-install(3) broken in 103740 pass in 103784
test-amd64-i386-xl-qemuu-winxpsp3 3 host-install(3) broken in 103749 pass in 103784
test-amd64-i386-qemut-rhel6hvm-amd 3 host-install(3) broken in 103749 pass in 103784
test-amd64-i386-libvirt-xsm 3 host-install(3) broken pass in 103749
test-amd64-i386-xl-qemut-win7-amd64 3 host-install(3) broken pass in 103749
test-amd64-i386-freebsd10-i386 3 host-install(3) broken pass in 103749
test-amd64-amd64-xl-xsm 3 host-install(3) broken pass in 103764
test-amd64-amd64-xl-pvh-intel 3 host-install(3) broken pass in 103764
test-amd64-amd64-pygrub 3 host-install(3) broken pass in 103764
test-amd64-amd64-i386-pvgrub 3 host-install(3) broken pass in 103764
test-amd64-amd64-xl-multivcpu 3 host-install(3) broken pass in 103764
test-amd64-amd64-libvirt-vhd 9 debian-di-install fail in 102733 pass in 102886
test-amd64-amd64-xl-xsm 19 guest-start/debian.repeat fail in 102755 pass in 103089
test-armhf-armhf-libvirt-xsm 14 guest-stop fail in 102755 pass in 103764
test-amd64-i386-xl-xsm 6 xen-boot fail in 102886 pass in 103784
test-amd64-amd64-qemuu-nested-amd 9 debian-hvm-install fail in 102886 pass in 103784
test-amd64-i386-xl-qemuu-winxpsp3-vcpus1 9 windows-install fail in 102886 pass in 103784
test-amd64-i386-xl-qemut-debianhvm-amd64 9 debian-hvm-install fail in 103011 pass in 103784
test-armhf-armhf-xl-arndale 15 guest-start/debian.repeat fail in 103089 pass in 103784
test-armhf-armhf-libvirt-xsm 6 xen-boot fail in 103451 pass in 103784
test-amd64-i386-libvirt-xsm 6 xen-boot fail in 103749 pass in 102755
test-amd64-i386-freebsd10-i386 6 xen-boot fail in 103749 pass in 103011
test-amd64-amd64-xl-xsm 6 xen-boot fail in 103749 pass in 103089
test-amd64-amd64-i386-pvgrub 6 xen-boot fail in 103749 pass in 103352
test-armhf-armhf-xl-credit2 6 xen-boot fail in 103749 pass in 103784
test-amd64-i386-xl-qemuu-win7-amd64 9 windows-install fail in 103749 pass in 103784
test-armhf-armhf-xl-arndale 5 xen-install fail in 103749 pass in 103784
test-amd64-i386-xl-xsm 11 guest-start fail in 103764 pass in 103784
test-armhf-armhf-xl-arndale 4 host-ping-check-native fail in 103764 pass in 103784
test-amd64-i386-qemuu-rhel6hvm-intel 6 xen-boot fail pass in 102733
test-amd64-i386-xl-raw 6 xen-boot fail pass in 102733
test-amd64-amd64-libvirt 6 xen-boot fail pass in 102733
test-amd64-amd64-xl-qemut-winxpsp3 6 xen-boot fail pass in 102755
test-amd64-i386-qemut-rhel6hvm-intel 6 xen-boot fail pass in 102829
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 6 xen-boot fail pass in 102886
test-amd64-amd64-libvirt-vhd 6 xen-boot fail pass in 102886
test-amd64-amd64-xl-rtds 6 xen-boot fail pass in 103089
test-amd64-amd64-xl-qemuu-debianhvm-amd64-xsm 6 xen-boot fail pass in 103089
test-amd64-amd64-libvirt-pair 9 xen-boot/src_host fail pass in 103089
test-amd64-amd64-libvirt-pair 10 xen-boot/dst_host fail pass in 103089
test-amd64-amd64-pair 9 xen-boot/src_host fail pass in 103165
test-amd64-amd64-pair 10 xen-boot/dst_host fail pass in 103165
test-amd64-amd64-libvirt-xsm 6 xen-boot fail pass in 103165
test-amd64-i386-libvirt-pair 9 xen-boot/src_host fail pass in 103451
test-amd64-i386-libvirt-pair 10 xen-boot/dst_host fail pass in 103451
test-armhf-armhf-xl-multivcpu 11 guest-start fail pass in 103740
test-amd64-amd64-xl-credit2 6 xen-boot fail pass in 103749
test-armhf-armhf-libvirt 11 guest-start fail pass in 103764
test-armhf-armhf-libvirt-xsm 11 guest-start fail pass in 103764
test-armhf-armhf-xl-rtds 9 debian-install fail pass in 103764
Regressions which are regarded as allowable (not blocking):
test-amd64-amd64-rumprun-amd64 3 host-install(3) broken blocked in 101737
test-armhf-armhf-libvirt 15 guest-start/debian.repeat fail in 102755 like 101672
test-armhf-armhf-xl-credit2 11 guest-start fail in 102755 like 101737
test-armhf-armhf-xl-multivcpu 15 guest-start/debian.repeat fail in 102755 like 101737
test-armhf-armhf-xl-xsm 11 guest-start fail in 102829 like 101737
test-armhf-armhf-xl-rtds 16 guest-start.2 fail in 102886 blocked in 101737
test-amd64-i386-rumprun-i386 16 rumprun-demo-xenstorels/xenstorels.repeat fail in 102886 blocked in 101737
test-armhf-armhf-xl-credit2 15 guest-start/debian.repeat fail in 102886 like 101687
test-armhf-armhf-xl-cubietruck 11 guest-start fail in 103451 like 101737
test-amd64-amd64-rumprun-amd64 6 xen-boot fail in 103749 blocked in 101737
test-armhf-armhf-xl 11 guest-start fail in 103749 like 101672
test-armhf-armhf-xl-rtds 15 guest-start/debian.repeat fail in 103749 like 101715
test-armhf-armhf-libvirt 13 saverestore-support-check fail in 103749 like 101737
test-armhf-armhf-libvirt-xsm 13 saverestore-support-check fail in 103749 like 101737
test-armhf-armhf-libvirt-xsm 15 guest-start/debian.repeat fail in 103749 like 101737
test-armhf-armhf-xl-cubietruck 15 guest-start/debian.repeat fail like 101715
test-armhf-armhf-xl-xsm 15 guest-start/debian.repeat fail like 101715
test-armhf-armhf-xl 15 guest-start/debian.repeat fail like 101737
test-amd64-amd64-xl-qemut-win7-amd64 16 guest-stop fail like 101737
test-amd64-amd64-xl-qemuu-win7-amd64 16 guest-stop fail like 101737
test-amd64-i386-xl-qemuu-win7-amd64 16 guest-stop fail like 101737
test-armhf-armhf-xl-vhd 9 debian-di-install fail like 101737
test-armhf-armhf-libvirt-qcow2 9 debian-di-install fail like 101737
Tests which did not succeed, but are not blocking:
test-armhf-armhf-xl-multivcpu 1 build-check(1) blocked in 102733 n/a
test-armhf-armhf-libvirt 1 build-check(1) blocked in 102733 n/a
test-armhf-armhf-libvirt-qcow2 1 build-check(1) blocked in 102733 n/a
test-armhf-armhf-libvirt-raw 1 build-check(1) blocked in 102733 n/a
test-armhf-armhf-xl 1 build-check(1) blocked in 102733 n/a
test-armhf-armhf-xl-vhd 1 build-check(1) blocked in 102733 n/a
test-armhf-armhf-xl-credit2 1 build-check(1) blocked in 102733 n/a
test-armhf-armhf-xl-cubietruck 1 build-check(1) blocked in 102733 n/a
test-armhf-armhf-xl-rtds 1 build-check(1) blocked in 102733 n/a
test-armhf-armhf-xl-arndale 1 build-check(1) blocked in 102733 n/a
test-armhf-armhf-libvirt-xsm 1 build-check(1) blocked in 102733 n/a
test-armhf-armhf-xl-xsm 1 build-check(1) blocked in 102733 n/a
test-amd64-amd64-libvirt 12 migrate-support-check fail in 102733 never pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 10 migrate-support-check fail in 102755 never pass
test-amd64-amd64-libvirt-vhd 11 migrate-support-check fail in 102755 never pass
test-amd64-i386-libvirt-xsm 12 migrate-support-check fail in 102755 never pass
test-amd64-amd64-libvirt-xsm 12 migrate-support-check fail in 102755 never pass
test-armhf-armhf-xl-multivcpu 12 migrate-support-check fail in 102755 never pass
test-armhf-armhf-xl-multivcpu 13 saverestore-support-check fail in 102755 never pass
test-armhf-armhf-libvirt 12 migrate-support-check fail in 103749 never pass
test-armhf-armhf-libvirt-xsm 12 migrate-support-check fail in 103749 never pass
test-armhf-armhf-xl-rtds 12 migrate-support-check fail in 103749 never pass
test-armhf-armhf-xl-rtds 13 saverestore-support-check fail in 103749 never pass
test-amd64-amd64-xl-pvh-amd 11 guest-start fail never pass
test-amd64-i386-libvirt 12 migrate-support-check fail never pass
test-armhf-armhf-xl 12 migrate-support-check fail never pass
test-armhf-armhf-xl 13 saverestore-support-check fail never pass
test-armhf-armhf-xl-cubietruck 12 migrate-support-check fail never pass
test-armhf-armhf-xl-cubietruck 13 saverestore-support-check fail never pass
test-armhf-armhf-xl-credit2 12 migrate-support-check fail never pass
test-armhf-armhf-xl-credit2 13 saverestore-support-check fail never pass
test-armhf-armhf-xl-xsm 12 migrate-support-check fail never pass
test-armhf-armhf-xl-xsm 13 saverestore-support-check fail never pass
test-amd64-amd64-qemuu-nested-amd 16 debian-hvm-install/l1/l2 fail never pass
test-armhf-armhf-xl-arndale 12 migrate-support-check fail never pass
test-armhf-armhf-xl-arndale 13 saverestore-support-check fail never pass
test-armhf-armhf-libvirt-raw 9 debian-di-install fail never pass
version targeted for testing:
linux 8576fa45c10e665bb72931a31461c7310f3c5494
baseline version:
linux 9ca365c0c8bdd8552ec064f0e696600cf7ea66dd
Last test of basis 101737 2016-10-28 04:21:54 Z 55 days
Testing same since 102733 2016-11-30 09:50:09 Z 21 days 20 attempts
------------------------------------------------------------
People who touched revisions under test:
Adrian Hunter <adrian.hunter@intel.com>
Alan Stern <stern@rowland.harvard.edu>
Alex Deucher <alexander.deucher@amd.com>
Alexander Polakov <apolyakov@beget.ru>
Alexander Usyskin <alexander.usyskin@intel.com>
Andrew Morton <akpm@linux-foundation.org>
Arve Hjønnevåg <arve@android.com>
Bryan Paluch <bryanpaluch@gmail.com>
Carlos Santa <carlos.santa@intel.com>
Carlos Santa <carlos.santa@intel.com> (v1)
Ching Huang <ching2048@areca.com.tw>
Chris Mason <clm@fb.com>
Dan Carpenter <dan.carpenter@oracle.com>
Daniel Vetter <daniel.vetter@ffwll.ch>
Darrick J. Wong <darrick.wong@oracle.com>
Dave Airlie <airlied@redhat.com>
Dave Chinner <david@fromorbit.com>
David Howells <dhowells@redhat.com>
Dinesh Israni <ddi@datera.io>
Dmitry Torokhov <dmitry.torokhov@gmail.com>
Dmitry Vyukov <dvyukov@google.com>
Ewan D. Milne <emilne@redhat.com>
Felipe Balbi <felipe.balbi@linux.intel.com>
Frank Haverkamp <haver@linux.vnet.ibm.com>
Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Gerald Schaefer <gerald.schaefer@de.ibm.com>
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Haibo Chen <haibo.chen@nxp.com>
Helge Deller <deller@gmx.de>
Ian Munsie <imunsie@au1.ibm.com>
Ilya Dryomov <idryomov@gmail.com>
Ingo Molnar <mingo@kernel.org>
James Hogan <james.hogan@imgtec.com>
James Morris <james.l.morris@oracle.com>
Jan Kara <jack@suse.cz>
Jiri Slaby <jslaby@suse.cz>
Johan Hovold <johan@kernel.org>
Johannes Berg <johannes.berg@intel.com>
John David Anglin <dave.anglin@bell.net>
K. Y. Srinivasan <kys@microsoft.com>
Kashyap Desai <kashyap.desai@broadcom.com>
Kirill A. Shutemov <kirill@shutemov.name>
Kirill A. Shutemov <kirill@shutemov.name> (v1)
Linus Torvalds <torvalds@linux-foundation.org>
Long Li <longli@microsoft.com>
Lucas Stach <dev@lynxeye.de>
Marc Zyngier <marc.zyngier@arm.com>
Marcel Hasler <mahasler@gmail.com>
Mark Rutland <mark.rutland@arm.com>
Martijn Coenen <maco@android.com>
Martin K. Petersen <martin.petersen@oracle.com>
Mathias Nyman <mathias.nyman@linux.intel.com>
Matt Redfearn <matt.redfearn@imgtec.com>
Michael Ellerman <mpe@ellerman.id.au>
Michael S. Tsirkin <mst@redhat.com>
Michal Marek <mmarek@suse.com>
Michel Dänzer <michel.daenzer@amd.com>
Mike Snitzer <snitzer@redhat.com>
Miklos Szeredi <mszeredi@redhat.com>
Ming Lei <tom.leiming@gmail.com>
NeilBrown <neilb@suse.com>
Nicholas Bellinger <nab@linux-iscsi.org>
Nikolay Borisov <kernel@kyup.com>
Nixon Vincent <nixon.vincent@calsoftinc.com>
Ondrej Kozina <okozina@redhat.com>
Paolo Bonzini <pbonzini@redhat.com>
Patrick Scheuring <patrick.scheuring.dev@gmail.com>
Peter Rosin <peda@axentia.se>
Radim KrÄmář <rkrcmar@redhat.com>
Ralph Sennhauser <ralph.sennhauser@gmail.com>
Richard Weinberger <richard@nod.at>
Ritesh Raj Sarraf <rrs@researchut.com>
Sasha Levin <alexander.levin@verizon.com>
Scot Doyle <lkml14@scotdoyle.com>
Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Segher Boessenkool <segher@kernel.crashing.org>
Shaohua Li <shli@fb.com>
Sonny Jiang <sonny.jiang@amd.com>
Stefan Richter <stefanr@s5r6.in-berlin.de>
Stefan Tauner <stefan.tauner@technikum-wien.at>
Sudeep Holla <sudeep.holla@arm.com>
Sumit Saxena <sumit.saxena@broadcom.com>
Taesoo Kim <tsgatesv@gmail.com>
Takashi Iwai <tiwai@suse.de>
tang.junhui <tang.junhui@zte.com.cn>
Theodore Ts'o <tytso@mit.edu>
Thomas Gleixner <tglx@linutronix.de>
Tom St Denis <tom.stdenis@amd.com>
Tomas Winkler <tomas.winkler@intel.com>
Tony Luck <tony.luck@intel.com>
Ulf Hansson <ulf.hansson@linaro.org>
Vaibhav Tandon <vst@datera.io>
Ville Syrjälä <ville.syrjala@linux.intel.com>
Vladimir Davydov <vdavydov.dev@gmail.com>
Vladimir Murzin <vladimir.murzin@arm.com>
Will Deacon <will.deacon@arm.com>
jobs:
build-amd64-xsm pass
build-armhf-xsm pass
build-i386-xsm pass
build-amd64 pass
build-armhf pass
build-i386 pass
build-amd64-libvirt pass
build-armhf-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-armhf-pvops pass
build-i386-pvops pass
build-amd64-rumprun pass
build-i386-rumprun pass
test-amd64-amd64-xl fail
test-armhf-armhf-xl fail
test-amd64-i386-xl pass
test-amd64-amd64-xl-qemut-debianhvm-amd64-xsm fail
test-amd64-i386-xl-qemut-debianhvm-amd64-xsm pass
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm fail
test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm fail
test-amd64-amd64-xl-qemuu-debianhvm-amd64-xsm fail
test-amd64-i386-xl-qemuu-debianhvm-amd64-xsm fail
test-amd64-amd64-xl-qemut-stubdom-debianhvm-amd64-xsm pass
test-amd64-i386-xl-qemut-stubdom-debianhvm-amd64-xsm pass
test-amd64-amd64-libvirt-xsm fail
test-armhf-armhf-libvirt-xsm fail
test-amd64-i386-libvirt-xsm broken
test-amd64-amd64-xl-xsm broken
test-armhf-armhf-xl-xsm fail
test-amd64-i386-xl-xsm pass
test-amd64-amd64-qemuu-nested-amd fail
test-amd64-amd64-xl-pvh-amd fail
test-amd64-i386-qemut-rhel6hvm-amd pass
test-amd64-i386-qemuu-rhel6hvm-amd pass
test-amd64-amd64-xl-qemut-debianhvm-amd64 pass
test-amd64-i386-xl-qemut-debianhvm-amd64 pass
test-amd64-amd64-xl-qemuu-debianhvm-amd64 pass
test-amd64-i386-xl-qemuu-debianhvm-amd64 pass
test-amd64-i386-freebsd10-amd64 fail
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-i386-xl-qemuu-ovmf-amd64 pass
test-amd64-amd64-rumprun-amd64 broken
test-amd64-amd64-xl-qemut-win7-amd64 fail
test-amd64-i386-xl-qemut-win7-amd64 broken
test-amd64-amd64-xl-qemuu-win7-amd64 fail
test-amd64-i386-xl-qemuu-win7-amd64 fail
test-armhf-armhf-xl-arndale pass
test-amd64-amd64-xl-credit2 fail
test-armhf-armhf-xl-credit2 pass
test-armhf-armhf-xl-cubietruck fail
test-amd64-i386-freebsd10-i386 broken
test-amd64-i386-rumprun-i386 pass
test-amd64-amd64-qemuu-nested-intel fail
test-amd64-amd64-xl-pvh-intel broken
test-amd64-i386-qemut-rhel6hvm-intel fail
test-amd64-i386-qemuu-rhel6hvm-intel fail
test-amd64-amd64-libvirt fail
test-armhf-armhf-libvirt fail
test-amd64-i386-libvirt pass
test-amd64-amd64-xl-multivcpu broken
test-armhf-armhf-xl-multivcpu fail
test-amd64-amd64-pair fail
test-amd64-i386-pair fail
test-amd64-amd64-libvirt-pair fail
test-amd64-i386-libvirt-pair fail
test-amd64-amd64-amd64-pvgrub pass
test-amd64-amd64-i386-pvgrub broken
test-amd64-amd64-pygrub broken
test-armhf-armhf-libvirt-qcow2 fail
test-amd64-amd64-xl-qcow2 pass
test-armhf-armhf-libvirt-raw fail
test-amd64-i386-xl-raw fail
test-amd64-amd64-xl-rtds fail
test-armhf-armhf-xl-rtds fail
test-amd64-i386-xl-qemut-winxpsp3-vcpus1 pass
test-amd64-i386-xl-qemuu-winxpsp3-vcpus1 pass
test-amd64-amd64-libvirt-vhd fail
test-armhf-armhf-xl-vhd fail
test-amd64-amd64-xl-qemut-winxpsp3 fail
test-amd64-i386-xl-qemut-winxpsp3 pass
test-amd64-amd64-xl-qemuu-winxpsp3 fail
test-amd64-i386-xl-qemuu-winxpsp3 pass
------------------------------------------------------------
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
broken-step test-amd64-i386-libvirt-xsm host-install(3)
broken-step test-amd64-i386-xl-qemut-win7-amd64 host-install(3)
broken-step test-amd64-amd64-xl-xsm host-install(3)
broken-step test-amd64-amd64-xl-pvh-intel host-install(3)
broken-step test-amd64-i386-freebsd10-i386 host-install(3)
broken-step test-amd64-amd64-rumprun-amd64 host-install(3)
broken-step test-amd64-amd64-pygrub host-install(3)
broken-step test-amd64-amd64-i386-pvgrub host-install(3)
broken-step test-amd64-amd64-xl-multivcpu host-install(3)
Not pushing.
(No revision log; it would be 1907 lines long.)
[-- Attachment #2: Type: text/plain, Size: 127 bytes --]
_______________________________________________
Xen-devel mailing list
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^ permalink raw reply
* Re: [PATCH v3 02/12] eal/bus: introduce bus abstraction
From: Shreyansh Jain @ 2016-12-22 5:12 UTC (permalink / raw)
To: Stephen Hemminger, Jan Blunck
Cc: dev, David Marchand, Thomas Monjalon, Ferruh Yigit, jianbo.liu
In-Reply-To: <20161221153334.2b04f732@xeon-e3>
On Thursday 22 December 2016 05:03 AM, Stephen Hemminger wrote:
> On Wed, 21 Dec 2016 16:38:42 +0100
> Jan Blunck <jblunck@infradead.org> wrote:
>
>> On Tue, Dec 20, 2016 at 6:11 PM, Stephen Hemminger
>> <stephen@networkplumber.org> wrote:
>>> On Tue, 20 Dec 2016 14:17:14 +0100
>>> Jan Blunck <jblunck@infradead.org> wrote:
>>>
>>>> On Fri, Dec 16, 2016 at 2:10 PM, Shreyansh Jain <shreyansh.jain@nxp.com> wrote:
>>>>> This patch introduces the rte_bus abstraction for devices and drivers in
>>>>> EAL framework. The model is:
>>>>> - One or more buses are connected to a CPU (or core)
>>>>> - One or more devices are conneted to a Bus
>>>>> - Drivers are running instances which manage one or more devices
>>>>> - Bus is responsible for identifying devices (and interrupt propogation)
>>>>> - Driver is responsible for initializing the device
>>>>>
>>>>> This patch adds a 'rte_bus' class which rte_driver and rte_device refer.
>>>>> This way, each device (rte_xxx_device) would have reference to the bus
>>>>> it is based on. As well as, each driver (rte_xxx_driver) would have link
>>>>> to the bus and devices on it for servicing.
>>>>>
>>>>> __ rte_bus_list
>>>>> /
>>>>> +----------'---+
>>>>> |rte_bus |
>>>>> | driver_list------> List of rte_bus specific
>>>>> | device_list---- devices
>>>>> | | `-> List of rte_bus associated
>>>>> | | drivers
>>>>> +--|------|----+
>>>>> _________/ \_________
>>>>> +--------/----+ +-\---------------+
>>>>> |rte_device | |rte_driver |
>>>>> | rte_bus | | rte_bus |
>>>>> | rte_driver | | ... |
>>>>> | ... | +---------...-----+
>>>>> | | |||
>>>>> +---||--------+ |||
>>>>> || |||
>>>>> | \ \\\
>>>>> | \_____________ \\\
>>>>> | \ |||
>>>>> +------|---------+ +----|----------+ |||
>>>>> |rte_pci_device | |rte_xxx_device | |||
>>>>> | .... | | .... | |||
>>>>> +----------------+ +---------------+ / | \
>>>>> / | \
>>>>> _____________________/ / \
>>>>> / ___/ \
>>>>> +-------------'--+ +------------'---+ +--'------------+
>>>>> |rte_pci_driver | |rte_vdev_driver | |rte_xxx_driver |
>>>>> | .... | | .... | | .... |
>>>>> +----------------+ +----------------+ +---------------+
>>>>>
>>>>> This patch only enables the bus references on rte_driver and rte_driver.
>>>>> EAL wide global device and driver list continue to exist until an instance
>>>>> of bus is added in subsequent patches.
>>>>>
>>>>> This patch also introduces RTE_REGISTER_BUS macro on the lines of
>>>>> RTE_PMD_REGISTER_XXX. Key difference is that the constructor priority has
>>>>> been explicitly set to 101 so as to execute bus registration before PMD.
>>>>>
>>>>> Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
>>>>>
>>>
>>> Ok, but let's keep this as bus type not bus. It gets really hard and complex
>>> to enumerate all layers of PCI bus and bridges.
>>
>> As far as I understand it this isn't the intention to replicate the
>> hierarchy of buses we have in the kernel. The PCI bus in this case
>> becomes a list of PCI devices.
>
> One of the motivations seems to be "lets be able to handle lots of devices",
> but the current model with an array of ports is not going to scale well for that.
>
> It is time to make rte_eth_devices into rb-tree and get rid of MAX_PORTS config
> option.
>
That is a nice idea. Probably once we get the EAL compatible for 'lots
of devices', this would be next good change.
-
Shreyansh
^ permalink raw reply
* Re: kmod: provide wrappers for kmod_concurrent inc/dec
From: Jessica Yu @ 2016-12-22 5:07 UTC (permalink / raw)
To: Luis R. Rodriguez
Cc: shuah, rusty, ebiederm, dmitry.torokhov, acme, corbet,
martin.wilck, mmarek, pmladek, hare, rwright, jeffm, DSterba,
fdmanana, neilb, linux, rgoldwyn, subashab, xypron.glpk, keescook,
atomlin, mbenes, paulmck, dan.j.williams, jpoimboe, davem, mingo,
akpm, torvalds, linux-kselftest, linux-doc, linux-kernel
In-Reply-To: <20161208194824.2532-1-mcgrof@kernel.org>
+++ Luis R. Rodriguez [08/12/16 11:48 -0800]:
>kmod_concurrent is used as an atomic counter for enabling
>the allowed limit of modprobe calls, provide wrappers for it
>to enable this to be expanded on more easily. This will be done
>later.
>
>Signed-off-by: Luis R. Rodriguez <mcgrof@kernel.org>
>---
> kernel/kmod.c | 27 +++++++++++++++++++++------
> 1 file changed, 21 insertions(+), 6 deletions(-)
>
>diff --git a/kernel/kmod.c b/kernel/kmod.c
>index cb6f7ca7b8a5..049d7eabda38 100644
>--- a/kernel/kmod.c
>+++ b/kernel/kmod.c
>@@ -44,6 +44,9 @@
> #include <trace/events/module.h>
>
> extern int max_threads;
>+
>+static atomic_t kmod_concurrent = ATOMIC_INIT(0);
>+
> unsigned int max_modprobes;
> module_param(max_modprobes, uint, 0644);
> MODULE_PARM_DESC(max_modprobes, "Max number of allowed concurrent modprobes");
>@@ -108,6 +111,20 @@ static int call_modprobe(char *module_name, int wait)
> return -ENOMEM;
> }
>
>+static int kmod_umh_threads_get(void)
>+{
>+ atomic_inc(&kmod_concurrent);
>+ if (atomic_read(&kmod_concurrent) < max_modprobes)
Should this not be <=? I think this only allows up to max_modprobes-1 concurrent threads.
>+ return 0;
>+ atomic_dec(&kmod_concurrent);
>+ return -ENOMEM;
>+}
>+
>+static void kmod_umh_threads_put(void)
>+{
>+ atomic_dec(&kmod_concurrent);
>+}
>+
> /**
> * __request_module - try to load a kernel module
> * @wait: wait (or not) for the operation to complete
>@@ -129,7 +146,6 @@ int __request_module(bool wait, const char *fmt, ...)
> va_list args;
> char module_name[MODULE_NAME_LEN];
> int ret;
>- static atomic_t kmod_concurrent = ATOMIC_INIT(0);
> static int kmod_loop_msg;
>
> /*
>@@ -153,8 +169,8 @@ int __request_module(bool wait, const char *fmt, ...)
> if (ret)
> return ret;
>
>- atomic_inc(&kmod_concurrent);
>- if (atomic_read(&kmod_concurrent) > max_modprobes) {
>+ ret = kmod_umh_threads_get();
>+ if (ret) {
> /* We may be blaming an innocent here, but unlikely */
> if (kmod_loop_msg < 5) {
> printk(KERN_ERR
>@@ -162,15 +178,14 @@ int __request_module(bool wait, const char *fmt, ...)
> module_name);
> kmod_loop_msg++;
> }
>- atomic_dec(&kmod_concurrent);
>- return -ENOMEM;
>+ return ret;
> }
>
> trace_module_request(module_name, wait, _RET_IP_);
>
> ret = call_modprobe(module_name, wait ? UMH_WAIT_PROC : UMH_WAIT_EXEC);
>
>- atomic_dec(&kmod_concurrent);
>+ kmod_umh_threads_put();
> return ret;
> }
> EXPORT_SYMBOL(__request_module);
>--
>2.10.1
>
^ permalink raw reply
* Re: George's crazy full state idea (Re: HalfSipHash Acceptable Usage)
From: George Spelvin @ 2016-12-22 5:01 UTC (permalink / raw)
To: linux, luto
Cc: ak, davem, David.Laight, djb, ebiggers3, eric.dumazet, hannes,
Jason, jeanphilippe.aumasson, kernel-hardening, linux-crypto,
linux-kernel, netdev, tom, torvalds, tytso, vegard.nossum
In-Reply-To: <CALCETrVn1tWBQx-RCSqCQ2ZcB6hPdioaV52q8vY+Mz1fRKsUXA@mail.gmail.com>
Andy Lutomirski wrote:
> I don't even think it needs that. This is just adding a
> non-destructive final operation, right?
It is, but the problem is that SipHash is intended for *small* inputs,
so the standard implementations aren't broken into init/update/final
functions.
There's just one big function that keeps the state variables in
registers and never stores them anywhere.
If we *had* init/update/final functions, then it would be trivial.
> Just to clarify, if we replace SipHash with a black box, I think this
> effectively means, where "entropy" is random_get_entropy() || jiffies
> || current->pid:
> The first call returns H(random seed || entropy_0 || secret). The
> second call returns H(random seed || entropy_0 || secret || entropy_1
> || secret). Etc.
Basically, yes. I was skipping the padding byte and keying the
finalization rounds on the grounds of "can't hurt and might help",
but we could do it a more standard way.
> If not, then I have a fairly strong preference to keep whatever
> construction we come up with consistent with something that could
> actually happen with invocations of unmodified SipHash -- then all the
> security analysis on SipHash goes through.
Okay. I don't think it makes a difference, but it's not a *big* waste
of time. If we have finalization rounds, we can reduce the secret
to 128 bits.
If we include the padding byte, we can do one of two things:
1) Make the secret 184 bits, to fill up the final partial word as
much as possible, or
2) Make the entropy 1 byte smaller and conceptually misalign the
secret. What we'd actually do is remove the last byte of
the secret and include it in the entropy words, but that's
just a rotation of the secret between storage and hashing.
Also, I assume you'd like SipHash-2-4, since you want to rely
on a security analysis.
(Regarding the padding byte, getting it right might be annoying
to do exactly. All of the security analysis depends *only* on
its low 3 bits indicating how much of the final block is used.
As it says in the SipHash paper, they included 8 bits just because
it was easy. But if you want it exact, it's just one more byte of
state.)
> The one thing I don't like is
> that I don't see how to prove that you can't run it backwards if you
> manage to acquire a memory dump. In fact, I that that there exist, at
> least in theory, hash functions that are secure in the random oracle
> model but that *can* be run backwards given the full state. From
> memory, SHA-3 has exactly that property, and it would be a bit sad for
> a CSPRNG to be reversible.
Er... get_random_int() is specifically *not* designed to be resistant
to state capture, and I didn't try. Remember, what it's used for
is ASLR, what we're worried about is somene learning the layouts
of still-running processes, and and if you get a memory dump, you have
the memory layout!
If you want anti-backtracking, though, it's easy to add. What we
hash is:
entropy_0 || secret || output_0 || entropy_1 || secret || output_1 || ...
You mix the output word right back in to the (unfinalized) state after
generating it. This is still equivalent to unmodified back-box SipHash,
you're just using a (conceptually independent) SipHash invocation to
produce some of its input.
Each output is produced by copying the state, padding & finalizing after the
secret.
In fact, to make our lives easier, let's define the secret to end with
a counter byte that happens to be equal to the padding byte. The input
stream will be:
Previous output: 8 (or 4 for HalfSipHash) bytes
Entropy: 15 bytes (8 bytes timer, 4 bytes jiffies, 3 bytes pid)
Secret: 16 bytes
Counter: 1 byte
...repeat...
> We could also periodically mix in a big (128-bit?) chunk of fresh
> urandom output to keep the bad guys guessing.
Simpler and faster to just update the global master secret.
The state is per-CPU, so mixing in has to be repeated per CPU.
With these changes, I'm satisifed that it's secure, cheap, has a
sufficiently wide state size, *and* all standard SipHash analysis applies.
The only remaining issues are:
1) How many rounds, and
2) May we use HalfSipHash?
I'd *like* to persuade you that skipping the padding byte wouldn't
invalidate any security proofs, because it's true and would simplify
the code. But if you want 100% stock, I'm willing to cater to that.
Ted, what do you think?
^ permalink raw reply
* [kernel-hardening] Re: George's crazy full state idea (Re: HalfSipHash Acceptable Usage)
From: George Spelvin @ 2016-12-22 5:01 UTC (permalink / raw)
To: linux, luto
Cc: ak, davem, David.Laight, djb, ebiggers3, eric.dumazet, hannes,
Jason, jeanphilippe.aumasson, kernel-hardening, linux-crypto,
linux-kernel, netdev, tom, torvalds, tytso, vegard.nossum
In-Reply-To: <CALCETrVn1tWBQx-RCSqCQ2ZcB6hPdioaV52q8vY+Mz1fRKsUXA@mail.gmail.com>
Andy Lutomirski wrote:
> I don't even think it needs that. This is just adding a
> non-destructive final operation, right?
It is, but the problem is that SipHash is intended for *small* inputs,
so the standard implementations aren't broken into init/update/final
functions.
There's just one big function that keeps the state variables in
registers and never stores them anywhere.
If we *had* init/update/final functions, then it would be trivial.
> Just to clarify, if we replace SipHash with a black box, I think this
> effectively means, where "entropy" is random_get_entropy() || jiffies
> || current->pid:
> The first call returns H(random seed || entropy_0 || secret). The
> second call returns H(random seed || entropy_0 || secret || entropy_1
> || secret). Etc.
Basically, yes. I was skipping the padding byte and keying the
finalization rounds on the grounds of "can't hurt and might help",
but we could do it a more standard way.
> If not, then I have a fairly strong preference to keep whatever
> construction we come up with consistent with something that could
> actually happen with invocations of unmodified SipHash -- then all the
> security analysis on SipHash goes through.
Okay. I don't think it makes a difference, but it's not a *big* waste
of time. If we have finalization rounds, we can reduce the secret
to 128 bits.
If we include the padding byte, we can do one of two things:
1) Make the secret 184 bits, to fill up the final partial word as
much as possible, or
2) Make the entropy 1 byte smaller and conceptually misalign the
secret. What we'd actually do is remove the last byte of
the secret and include it in the entropy words, but that's
just a rotation of the secret between storage and hashing.
Also, I assume you'd like SipHash-2-4, since you want to rely
on a security analysis.
(Regarding the padding byte, getting it right might be annoying
to do exactly. All of the security analysis depends *only* on
its low 3 bits indicating how much of the final block is used.
As it says in the SipHash paper, they included 8 bits just because
it was easy. But if you want it exact, it's just one more byte of
state.)
> The one thing I don't like is
> that I don't see how to prove that you can't run it backwards if you
> manage to acquire a memory dump. In fact, I that that there exist, at
> least in theory, hash functions that are secure in the random oracle
> model but that *can* be run backwards given the full state. From
> memory, SHA-3 has exactly that property, and it would be a bit sad for
> a CSPRNG to be reversible.
Er... get_random_int() is specifically *not* designed to be resistant
to state capture, and I didn't try. Remember, what it's used for
is ASLR, what we're worried about is somene learning the layouts
of still-running processes, and and if you get a memory dump, you have
the memory layout!
If you want anti-backtracking, though, it's easy to add. What we
hash is:
entropy_0 || secret || output_0 || entropy_1 || secret || output_1 || ...
You mix the output word right back in to the (unfinalized) state after
generating it. This is still equivalent to unmodified back-box SipHash,
you're just using a (conceptually independent) SipHash invocation to
produce some of its input.
Each output is produced by copying the state, padding & finalizing after the
secret.
In fact, to make our lives easier, let's define the secret to end with
a counter byte that happens to be equal to the padding byte. The input
stream will be:
Previous output: 8 (or 4 for HalfSipHash) bytes
Entropy: 15 bytes (8 bytes timer, 4 bytes jiffies, 3 bytes pid)
Secret: 16 bytes
Counter: 1 byte
...repeat...
> We could also periodically mix in a big (128-bit?) chunk of fresh
> urandom output to keep the bad guys guessing.
Simpler and faster to just update the global master secret.
The state is per-CPU, so mixing in has to be repeated per CPU.
With these changes, I'm satisifed that it's secure, cheap, has a
sufficiently wide state size, *and* all standard SipHash analysis applies.
The only remaining issues are:
1) How many rounds, and
2) May we use HalfSipHash?
I'd *like* to persuade you that skipping the padding byte wouldn't
invalidate any security proofs, because it's true and would simplify
the code. But if you want 100% stock, I'm willing to cater to that.
Ted, what do you think?
^ permalink raw reply
* [PATCH v8 4/5] mmc: dt-bindings: add ZTE ZX296718 MMC bindings
From: Jun Nie @ 2016-12-22 4:57 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawn.guo, xie.baoyou, devicetree
Cc: ulf.hansson, jh80.chung, jason.liu, chen.chaokai, lai.binz,
linux-mmc, Jun Nie
In-Reply-To: <1482382657-16681-1-git-send-email-jun.nie@linaro.org>
Document the device-tree binding of ZTE MMC host on
ZX296718 SoC.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
.../devicetree/bindings/mmc/zx-dw-mshc.txt | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
diff --git a/Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
new file mode 100644
index 0000000..eaade0e
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
@@ -0,0 +1,33 @@
+* ZTE specific extensions to the Synopsys Designware Mobile Storage
+ Host Controller
+
+The Synopsys designware mobile storage host controller is used to interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
+differences between the core Synopsys dw mshc controller properties described
+by synopsys-dw-mshc.txt and the properties used by the ZTE specific
+extensions to the Synopsys Designware Mobile Storage Host Controller.
+
+Required Properties:
+
+* compatible: should be
+ - "zte,zx296718-dw-mshc": for ZX SoCs
+
+Example:
+
+ mmc1: mmc@1110000 {
+ compatible = "zte,zx296718-dw-mshc";
+ reg = <0x01110000 0x1000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ fifo-depth = <32>;
+ data-addr = <0x200>;
+ fifo-watermark-aligned;
+ bus-width = <4>;
+ clock-frequency = <50000000>;
+ clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
+ clock-names = "biu", "ciu";
+ num-slots = <1>;
+ max-frequency = <50000000>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ status = "disabled";
+ };
--
1.9.1
^ permalink raw reply related
* [PATCH v8 3/5] mmc: dw: Add fifo watermark alignment property
From: Jun Nie @ 2016-12-22 4:57 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawn.guo, xie.baoyou, devicetree
Cc: ulf.hansson, jh80.chung, jason.liu, chen.chaokai, lai.binz,
linux-mmc, Jun Nie
In-Reply-To: <1482382657-16681-1-git-send-email-jun.nie@linaro.org>
Data done irq is expected if data length is less than
watermark in PIO mode. But fifo watermark is requested
to be aligned with data length in some SoC so that TX/RX
irq can be generated with data done irq. Add the
watermark alignment to mark this requirement and force
fifo watermark setting accordingly.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/mmc/host/dw_mmc.c | 11 +++++++++--
include/linux/mmc/dw_mmc.h | 3 +++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index b600170..e890a45 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1113,11 +1113,15 @@ static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
mci_writel(host, CTRL, temp);
/*
- * Use the initial fifoth_val for PIO mode.
+ * Use the initial fifoth_val for PIO mode. If wm_algined
+ * is set, we set watermark same as data size.
* If next issued data may be transfered by DMA mode,
* prev_blksz should be invalidated.
*/
- mci_writel(host, FIFOTH, host->fifoth_val);
+ if (host->wm_aligned)
+ dw_mci_adjust_fifoth(host, data);
+ else
+ mci_writel(host, FIFOTH, host->fifoth_val);
host->prev_blksz = 0;
} else {
/*
@@ -2979,6 +2983,9 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
of_property_read_u32(np, "data-addr", &host->data_addr_override);
+ if (of_get_property(np, "fifo-watermark-aligned", NULL))
+ host->wm_aligned = true;
+
if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
pdata->bus_hz = clock_frequency;
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index 1c09cca..cc7da85 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -114,6 +114,8 @@ struct dw_mci_dma_slave {
* @slot: Slots sharing this MMC controller.
* @fifo_depth: depth of FIFO.
* @data_addr_override: override fifo reg offset with this value.
+ * @wm_aligned: force fifo watermark equal with data length in PIO mode.
+ * Set as true if alignment is needed.
* @data_shift: log2 of FIFO item size.
* @part_buf_start: Start index in part_buf.
* @part_buf_count: Bytes of partial data in part_buf.
@@ -162,6 +164,7 @@ struct dw_mci {
void __iomem *regs;
void __iomem *fifo_reg;
u32 data_addr_override;
+ bool wm_aligned;
struct scatterlist *sg;
struct sg_mapping_iter sg_miter;
--
1.9.1
^ permalink raw reply related
* [PATCH v8 2/5] mmc: dw: Add fifo address property
From: Jun Nie @ 2016-12-22 4:57 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawn.guo, xie.baoyou, devicetree
Cc: ulf.hansson, jh80.chung, jason.liu, chen.chaokai, lai.binz,
linux-mmc, Jun Nie
In-Reply-To: <1482382657-16681-1-git-send-email-jun.nie@linaro.org>
The FIFO address may break default address assumption of 0x100
(version < 0x240A) and 0x200(version >= 0x240A) in current driver.
The new property is introduced to override fifo address via DT
node information.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/mmc/host/dw_mmc.c | 6 +++++-
include/linux/mmc/dw_mmc.h | 2 ++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index b44306b..b600170 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2977,6 +2977,8 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
+ of_property_read_u32(np, "data-addr", &host->data_addr_override);
+
if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
pdata->bus_hz = clock_frequency;
@@ -3180,7 +3182,9 @@ int dw_mci_probe(struct dw_mci *host)
host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
dev_info(host->dev, "Version ID is %04x\n", host->verid);
- if (host->verid < DW_MMC_240A)
+ if (host->data_addr_override)
+ host->fifo_reg = host->regs + host->data_addr_override;
+ else if (host->verid < DW_MMC_240A)
host->fifo_reg = host->regs + DATA_OFFSET;
else
host->fifo_reg = host->regs + DATA_240A_OFFSET;
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
index 15db6f8..1c09cca 100644
--- a/include/linux/mmc/dw_mmc.h
+++ b/include/linux/mmc/dw_mmc.h
@@ -113,6 +113,7 @@ struct dw_mci_dma_slave {
* @ciu_clk: Pointer to card interface unit clock instance.
* @slot: Slots sharing this MMC controller.
* @fifo_depth: depth of FIFO.
+ * @data_addr_override: override fifo reg offset with this value.
* @data_shift: log2 of FIFO item size.
* @part_buf_start: Start index in part_buf.
* @part_buf_count: Bytes of partial data in part_buf.
@@ -160,6 +161,7 @@ struct dw_mci {
spinlock_t irq_lock;
void __iomem *regs;
void __iomem *fifo_reg;
+ u32 data_addr_override;
struct scatterlist *sg;
struct sg_mapping_iter sg_miter;
--
1.9.1
^ permalink raw reply related
* [PATCH v8 1/5] Documentation: synopsys-dw-mshc: add binding for fifo quirks
From: Jun Nie @ 2016-12-22 4:57 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawn.guo, xie.baoyou, devicetree
Cc: ulf.hansson, jh80.chung, jason.liu, chen.chaokai, lai.binz,
linux-mmc, Jun Nie
In-Reply-To: <1482382657-16681-1-git-send-email-jun.nie@linaro.org>
Add fifo-addr property and fifo-watermark-quirk property to
synopsys-dw-mshc bindings. It is intended to provide more
dt interface to support SoCs specific configuration.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 7fd17c3..bca30b6 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -75,6 +75,17 @@ Optional properties:
* card-detect-delay: Delay in milli-seconds before detecting card after card
insert event. The default value is 0.
+* data-addr: Override fifo address with value provided by DT. The default FIFO reg
+ offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) by
+ driver. If the controller does not follow this rule, please use this property
+ to set fifo address in device tree.
+
+* fifo-watermark-aligned: Data done irq is expected if data length is less than
+ watermark in PIO mode. But fifo watermark is requested to be aligned with data
+ length in some SoC so that TX/RX irq can be generated with data done irq. Add this
+ watermark quirk to mark this requirement and force fifo watermark setting
+ accordingly.
+
* vmmc-supply: The phandle to the regulator to use for vmmc. If this is
specified we'll defer probe until we can find this regulator.
@@ -102,6 +113,8 @@ board specific portions as listed below.
interrupts = <0 75 0>;
#address-cells = <1>;
#size-cells = <0>;
+ data-addr = <0x200>;
+ fifo-watermark-aligned;
resets = <&rst 20>;
reset-names = "reset";
};
--
1.9.1
^ permalink raw reply related
* Re: [PATCH v2 00/12] Add crypto PMD optimized for ARMv8
From: Jerin Jacob @ 2016-12-22 4:57 UTC (permalink / raw)
To: Declan Doherty
Cc: Zbigniew Bodek, Bruce Richardson, pablo.de.lara.guarch, dev
In-Reply-To: <898f972b-7d8a-384c-20bf-6ae3f7822136@intel.com>
On Wed, Dec 21, 2016 at 03:34:14PM +0000, Declan Doherty wrote:
> On 08/12/16 17:45, Jerin Jacob wrote:
> > On Thu, Dec 08, 2016 at 12:32:52PM +0100, Zbigniew Bodek wrote:
> > > On 08.12.2016 11:24, Bruce Richardson wrote:
> > > > On Tue, Dec 06, 2016 at 06:32:53PM -0800, zbigniew.bodek@caviumnetworks.com wrote:
> > > > > From: Zbigniew Bodek <zbigniew.bodek@caviumnetworks.com>
> > > >
> > >
> > > Hello Bruce,
> > >
> > > I don't know to be honest. I didn't know the reasoning behind not including
> > > crypto code for Intel for example. I thought it was due to licensing and
> > > code control rather than export compliance.
> > >
> > > Maybe someone from the DPDK community will know what are the constraints
> > > related to including crypto algorithms to DPDK.
> >
> > One of the primary reason why we thought of going with this approach is
> > for out of the box "distribution" enablement. We thought, if the core crypto
> > algorithm sits in some git-hub code or public hosted tarball then the
> > PMD will never be added to standard distributions and which is a setback
> > for armv8 server ecosystem.
> >
> > Having said that and as Zbigniew mentioned, We are open for revisiting
> > the crypto core algorithm and PMD split if there are community concerns
> > about export compliance. Let us know.
> >
> > Jerin
> >
> > >
> > > Kind regards
> > > Zbigniew
>
> Hey Jerin/Zbigniew,
>
>
> as Bruce said it's great to see you contributing to the crypto ecosystem in
> DPDK. I don't know if the export compliance with the core crypto code is an
> issue or not, that's definitely not my area of expertise, but I do have some
> concern which I think it relates somewhat to Thomas questions regarding
> implementing the core crypto algorithms in C rather than assembly.
>
> I wonder is there the expertise within the DPDK community to review/maintain
> the core crypto code in terms of both the assembly code itself and also the
> details of the crypto algorithm's implementations themselves. I know I
> wouldn't feel I have the knowledge/expertise to be able to review the core
> crypto algorithm's implementations and the assembly code itself and sign-off
> on them.
>
> I understand the advantage of having the code integrated directly into DPDK
> for packaging etc but this also puts the ownest on the DPDK community for
> the correctness of the underlying implementation of a particular algorithm.
> I think the approach of a separate library removes this responsibility from
> the community and places it on the distributor of the core crypto library.
OK. Taking Thomas and your feedback into account, We will move the core
crypto ARMv8 ASM code to separate library.
Jerin
>
> Declan
>
>
^ permalink raw reply
* [PATCH v8 5/5] mmc: zx: Initial support for ZX mmc controller
From: Jun Nie @ 2016-12-22 4:57 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
shawn.guo-QSEj5FYQhm4dnm+yROfE0A,
xie.baoyou-Th6q7B73Y6EnDS1+zs4M5A,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
jh80.chung-Sze3O3UU22JBDgjK7y7TUQ,
jason.liu-QSEj5FYQhm4dnm+yROfE0A,
chen.chaokai-Th6q7B73Y6EnDS1+zs4M5A,
lai.binz-Th6q7B73Y6EnDS1+zs4M5A, linux-mmc-u79uwXL29TY76Z2rM5mHXA,
Jun Nie
In-Reply-To: <1482382657-16681-1-git-send-email-jun.nie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
This platform driver adds initial support for the DW host controller
found on ZTE SoCs.
It has been tested on ZX296718 EVB board currently. More support on
timing tuning will be added when hardware is available.
Signed-off-by: Jun Nie <jun.nie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
drivers/mmc/host/Kconfig | 9 ++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/dw_mmc-zx.c | 242 +++++++++++++++++++++++++++++++++++++++++++
drivers/mmc/host/dw_mmc-zx.h | 31 ++++++
4 files changed, 283 insertions(+)
create mode 100644 drivers/mmc/host/dw_mmc-zx.c
create mode 100644 drivers/mmc/host/dw_mmc-zx.h
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 2eb9701..f08691a 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -683,6 +683,15 @@ config MMC_DW_ROCKCHIP
Synopsys DesignWare Memory Card Interface driver. Select this option
for platforms based on RK3066, RK3188 and RK3288 SoC's.
+config MMC_DW_ZX
+ tristate "ZTE specific extensions for Synopsys DW Memory Card Interface"
+ depends on MMC_DW && ARCH_ZX
+ select MMC_DW_PLTFM
+ help
+ This selects support for ZTE SoC specific extensions to the
+ Synopsys DesignWare Memory Card Interface driver. Select this option
+ for platforms based on ZX296718 SoC's.
+
config MMC_SH_MMCIF
tristate "SuperH Internal MMCIF support"
depends on HAS_DMA
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index ccc9c4c..6d548c4 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_MMC_DW_EXYNOS) += dw_mmc-exynos.o
obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
+obj-$(CONFIG_MMC_DW_ZX) += dw_mmc-zx.o
obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
obj-$(CONFIG_MMC_VUB300) += vub300.o
diff --git a/drivers/mmc/host/dw_mmc-zx.c b/drivers/mmc/host/dw_mmc-zx.c
new file mode 100644
index 0000000..11b9fc3
--- /dev/null
+++ b/drivers/mmc/host/dw_mmc-zx.c
@@ -0,0 +1,242 @@
+/*
+ * ZX Specific Extensions for Synopsys DW Multimedia Card Interface driver
+ *
+ * Copyright (C) 2016, Linaro Ltd.
+ * Copyright (C) 2016, ZTE Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mmc/dw_mmc.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/mmc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "dw_mmc.h"
+#include "dw_mmc-pltfm.h"
+#include "dw_mmc-zx.h"
+
+struct dw_mci_zx_priv_data {
+ struct regmap *sysc_base;
+};
+
+enum delay_type {
+ DELAY_TYPE_READ, /* read dqs delay */
+ DELAY_TYPE_CLK, /* clk sample delay */
+};
+
+static int dw_mci_zx_emmc_set_delay(struct dw_mci *host, unsigned int delay,
+ enum delay_type dflag)
+{
+ struct dw_mci_zx_priv_data *priv = host->priv;
+ struct regmap *sysc_base = priv->sysc_base;
+ unsigned int clksel;
+ unsigned int loop = 1000;
+ int ret;
+
+ if (!sysc_base)
+ return -EINVAL;
+
+ ret = regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0,
+ PARA_HALF_CLK_MODE | PARA_DLL_BYPASS_MODE |
+ PARA_PHASE_DET_SEL_MASK |
+ PARA_DLL_LOCK_NUM_MASK |
+ DLL_REG_SET | PARA_DLL_START_MASK,
+ PARA_DLL_START(4) | PARA_DLL_LOCK_NUM(4));
+ if (ret)
+ return ret;
+
+ ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG1, &clksel);
+ if (ret)
+ return ret;
+
+ if (dflag == DELAY_TYPE_CLK) {
+ clksel &= ~CLK_SAMP_DELAY_MASK;
+ clksel |= CLK_SAMP_DELAY(delay);
+ } else {
+ clksel &= ~READ_DQS_DELAY_MASK;
+ clksel |= READ_DQS_DELAY(delay);
+ }
+
+ regmap_write(sysc_base, LB_AON_EMMC_CFG_REG1, clksel);
+ regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0,
+ PARA_DLL_START_MASK | PARA_DLL_LOCK_NUM_MASK |
+ DLL_REG_SET,
+ PARA_DLL_START(4) | PARA_DLL_LOCK_NUM(4) |
+ DLL_REG_SET);
+
+ do {
+ ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG2, &clksel);
+ if (ret)
+ return ret;
+
+ } while (--loop && !(clksel & ZX_DLL_LOCKED));
+
+ if (!loop) {
+ dev_err(host->dev, "Error: %s dll lock fail\n", __func__);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int dw_mci_zx_emmc_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
+{
+ struct dw_mci *host = slot->host;
+ struct mmc_host *mmc = slot->mmc;
+ int ret, len, start = 0, end = 0, delay, best = 0;
+
+ for (delay = 1 ; delay < 128; delay++) {
+ ret = dw_mci_zx_emmc_set_delay(host, delay, DELAY_TYPE_CLK);
+ if (!ret && mmc_send_tuning(mmc, opcode, NULL)) {
+ if (start >= 0) {
+ end = delay - 1;
+ /* check and update longest good range */
+ if ((end - start) > len) {
+ best = (start + end) >> 1;
+ len = end - start;
+ }
+ }
+ start = -1;
+ end = 0;
+ continue;
+ }
+ if (start < 0)
+ start = delay;
+ }
+
+ if (start >= 0) {
+ end = delay - 1;
+ if ((end - start) > len) {
+ best = (start + end) >> 1;
+ len = end - start;
+ }
+ }
+ if (best < 0)
+ return -EIO;
+
+ dev_info(host->dev, "%s best range: start %d end %d\n", __func__,
+ start, end);
+ return dw_mci_zx_emmc_set_delay(host, best, DELAY_TYPE_CLK);
+}
+
+static int dw_mci_zx_prepare_hs400_tuning(struct dw_mci *host,
+ struct mmc_ios *ios)
+{
+ int ret;
+
+ /* config phase shift as 90 degree */
+ ret = dw_mci_zx_emmc_set_delay(host, 32, DELAY_TYPE_READ);
+ if (ret < 0)
+ return -EIO;
+
+ return 0;
+}
+
+static int dw_mci_zx_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
+{
+ struct dw_mci *host = slot->host;
+
+ if (host->verid == 0x290a) /* only for emmc */
+ return dw_mci_zx_emmc_execute_tuning(slot, opcode);
+ /* TODO: Add 0x210a dedicated tuning for sd/sdio */
+
+ return 0;
+}
+
+static int dw_mci_zx_parse_dt(struct dw_mci *host)
+{
+ struct device_node *np = host->dev->of_node;
+ struct device_node *node;
+ struct dw_mci_zx_priv_data *priv;
+ struct regmap *sysc_base;
+ int ret;
+
+ /* syscon is needed only by emmc */
+ node = of_parse_phandle(np, "zte,aon-syscon", 0);
+ if (node) {
+ sysc_base = syscon_node_to_regmap(node);
+ of_node_put(node);
+
+ if (IS_ERR(sysc_base)) {
+ ret = PTR_ERR(sysc_base);
+ if (ret != -EPROBE_DEFER)
+ dev_err(host->dev, "Can't get syscon: %d\n",
+ ret);
+ return ret;
+ }
+ } else {
+ return 0;
+ }
+
+ priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+ priv->sysc_base = sysc_base;
+ host->priv = priv;
+
+ return 0;
+}
+
+static unsigned long zx_dwmmc_caps[3] = {
+ MMC_CAP_CMD23,
+ MMC_CAP_CMD23,
+ MMC_CAP_CMD23,
+};
+
+static const struct dw_mci_drv_data zx_drv_data = {
+ .caps = zx_dwmmc_caps,
+ .execute_tuning = dw_mci_zx_execute_tuning,
+ .prepare_hs400_tuning = dw_mci_zx_prepare_hs400_tuning,
+ .parse_dt = dw_mci_zx_parse_dt,
+};
+
+static const struct of_device_id dw_mci_zx_match[] = {
+ { .compatible = "zte,zx296718-dw-mshc", .data = &zx_drv_data},
+ {},
+};
+MODULE_DEVICE_TABLE(of, dw_mci_zx_match);
+
+static int dw_mci_zx_probe(struct platform_device *pdev)
+{
+ const struct dw_mci_drv_data *drv_data;
+ const struct of_device_id *match;
+
+ match = of_match_node(dw_mci_zx_match, pdev->dev.of_node);
+ drv_data = match->data;
+
+ return dw_mci_pltfm_register(pdev, drv_data);
+}
+
+static const struct dev_pm_ops dw_mci_zx_dev_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+ SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
+ dw_mci_runtime_resume,
+ NULL)
+};
+
+static struct platform_driver dw_mci_zx_pltfm_driver = {
+ .probe = dw_mci_zx_probe,
+ .remove = dw_mci_pltfm_remove,
+ .driver = {
+ .name = "dwmmc_zx",
+ .of_match_table = dw_mci_zx_match,
+ .pm = &dw_mci_zx_dev_pm_ops,
+ },
+};
+
+module_platform_driver(dw_mci_zx_pltfm_driver);
+
+MODULE_DESCRIPTION("ZTE emmc/sd driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/dw_mmc-zx.h b/drivers/mmc/host/dw_mmc-zx.h
new file mode 100644
index 0000000..f369997
--- /dev/null
+++ b/drivers/mmc/host/dw_mmc-zx.h
@@ -0,0 +1,31 @@
+#ifndef _DW_MMC_ZX_H_
+#define _DW_MMC_ZX_H_
+
+/* ZX296718 SoC specific DLL register offset. */
+#define LB_AON_EMMC_CFG_REG0 0x1B0
+#define LB_AON_EMMC_CFG_REG1 0x1B4
+#define LB_AON_EMMC_CFG_REG2 0x1B8
+
+/* LB_AON_EMMC_CFG_REG0 register defines */
+#define PARA_DLL_START(x) ((x) & 0xFF)
+#define PARA_DLL_START_MASK 0xFF
+#define DLL_REG_SET BIT(8)
+#define PARA_DLL_LOCK_NUM(x) (((x) & 7) << 16)
+#define PARA_DLL_LOCK_NUM_MASK (7 << 16)
+#define PARA_PHASE_DET_SEL(x) (((x) & 7) << 20)
+#define PARA_PHASE_DET_SEL_MASK (7 << 20)
+#define PARA_DLL_BYPASS_MODE BIT(23)
+#define PARA_HALF_CLK_MODE BIT(24)
+
+/* LB_AON_EMMC_CFG_REG1 register defines */
+#define READ_DQS_DELAY(x) ((x) & 0x7F)
+#define READ_DQS_DELAY_MASK (0x7F)
+#define READ_DQS_BYPASS_MODE BIT(7)
+#define CLK_SAMP_DELAY(x) (((x) & 0x7F) << 8)
+#define CLK_SAMP_DELAY_MASK (0x7F << 8)
+#define CLK_SAMP_BYPASS_MODE BIT(15)
+
+/* LB_AON_EMMC_CFG_REG2 register defines */
+#define ZX_DLL_LOCKED BIT(2)
+
+#endif /* _DW_MMC_ZX_H_ */
--
1.9.1
--
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^ permalink raw reply related
* [PATCH v8 0/5] Add intial support to DW MMC host on ZTE SoC
From: Jun Nie @ 2016-12-22 4:57 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
shawn.guo-QSEj5FYQhm4dnm+yROfE0A,
xie.baoyou-Th6q7B73Y6EnDS1+zs4M5A,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
jh80.chung-Sze3O3UU22JBDgjK7y7TUQ,
jason.liu-QSEj5FYQhm4dnm+yROfE0A,
chen.chaokai-Th6q7B73Y6EnDS1+zs4M5A,
lai.binz-Th6q7B73Y6EnDS1+zs4M5A, linux-mmc-u79uwXL29TY76Z2rM5mHXA,
Jun Nie
Add intial support to DW MMC host on ZTE SoC. It include platform
specific wrapper driver and workarounds for fifo quirk.
Changes vs version 7:
- Re-order patches sequence so that new dts property is introduced before usage.
- Remove unecessary property in zx mmc dts.
Changes vs version 6:
- Resolve confilict when rebase to latest dw-mmc.git for-ulf branch.
- Add Shawn Lin's review tag.
Changes vs version 5:
- Add clock delay lock status check to save CPU cycle in timing tuning CMD.
Changes vs version 4:
- Fix missing empty dts compatible element in the end of compatible array.
Changes vs version 3:
- Fix brace error in document.
Changes vs version 2:
- Change dt property fifo-addr to data-addr and fifo-watermark-quirk to
fifo-watermark-aligned.
- Polish ZX MMC driver on minor coding style issues.
Changes vs version 1:
- Change fifo-addr-override to fifo-addr and remove its workaround tag in comments.
- Remove ZX DW MMC driver reset cap in driver, which can be added in dt nodes.
Jun Nie (5):
Documentation: synopsys-dw-mshc: add binding for fifo quirks
mmc: dw: Add fifo address property
mmc: dw: Add fifo watermark alignment property
mmc: dt-bindings: add ZTE ZX296718 MMC bindings
mmc: zx: Initial support for ZX mmc controller
.../devicetree/bindings/mmc/synopsys-dw-mshc.txt | 13 ++
.../devicetree/bindings/mmc/zx-dw-mshc.txt | 33 +++
drivers/mmc/host/Kconfig | 9 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/dw_mmc-zx.c | 242 +++++++++++++++++++++
drivers/mmc/host/dw_mmc-zx.h | 31 +++
drivers/mmc/host/dw_mmc.c | 17 +-
include/linux/mmc/dw_mmc.h | 5 +
8 files changed, 348 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
create mode 100644 drivers/mmc/host/dw_mmc-zx.c
create mode 100644 drivers/mmc/host/dw_mmc-zx.h
--
1.9.1
--
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^ permalink raw reply
* cron job: media_tree daily build: ERRORS
From: Hans Verkuil @ 2016-12-22 4:57 UTC (permalink / raw)
To: linux-media
This message is generated daily by a cron job that builds media_tree for
the kernels and architectures in the list below.
Results of the daily build of media_tree:
date: Thu Dec 22 05:00:17 CET 2016
media-tree git hash: c739c0a7c3c2472d7562b8f802cdce44d2597c8b
media_build git hash: 1606032398b1d79149c1507be2029e1a00d8dff0
v4l-utils git hash: c9aacef24d152007c7344b691da0cc90788395a7
gcc version: i686-linux-gcc (GCC) 6.2.0
sparse version: v0.5.0-3553-g78b2ea6
smatch version: v0.5.0-3553-g78b2ea6
host hardware: x86_64
host os: 4.8.0-164
linux-git-arm-at91: OK
linux-git-arm-davinci: OK
linux-git-arm-multi: OK
linux-git-arm-pxa: OK
linux-git-blackfin-bf561: OK
linux-git-i686: OK
linux-git-m32r: OK
linux-git-mips: OK
linux-git-powerpc64: OK
linux-git-sh: OK
linux-git-x86_64: OK
linux-2.6.36.4-i686: WARNINGS
linux-2.6.37.6-i686: WARNINGS
linux-2.6.38.8-i686: WARNINGS
linux-2.6.39.4-i686: WARNINGS
linux-3.0.60-i686: WARNINGS
linux-3.1.10-i686: WARNINGS
linux-3.2.37-i686: WARNINGS
linux-3.3.8-i686: WARNINGS
linux-3.4.27-i686: WARNINGS
linux-3.5.7-i686: WARNINGS
linux-3.6.11-i686: WARNINGS
linux-3.7.4-i686: WARNINGS
linux-3.8-i686: WARNINGS
linux-3.9.2-i686: WARNINGS
linux-3.10.1-i686: WARNINGS
linux-3.11.1-i686: OK
linux-3.12.67-i686: OK
linux-3.13.11-i686: WARNINGS
linux-3.14.9-i686: WARNINGS
linux-3.15.2-i686: WARNINGS
linux-3.16.7-i686: WARNINGS
linux-3.17.8-i686: ERRORS
linux-3.18.7-i686: ERRORS
linux-3.19-i686: ERRORS
linux-4.0.9-i686: ERRORS
linux-4.1.33-i686: ERRORS
linux-4.2.8-i686: ERRORS
linux-4.3.6-i686: ERRORS
linux-4.4.22-i686: ERRORS
linux-4.5.7-i686: ERRORS
linux-4.6.7-i686: ERRORS
linux-4.7.5-i686: ERRORS
linux-4.8-i686: OK
linux-4.9-i686: OK
linux-2.6.36.4-x86_64: WARNINGS
linux-2.6.37.6-x86_64: WARNINGS
linux-2.6.38.8-x86_64: WARNINGS
linux-2.6.39.4-x86_64: WARNINGS
linux-3.0.60-x86_64: WARNINGS
linux-3.1.10-x86_64: WARNINGS
linux-3.2.37-x86_64: WARNINGS
linux-3.3.8-x86_64: WARNINGS
linux-3.4.27-x86_64: WARNINGS
linux-3.5.7-x86_64: WARNINGS
linux-3.6.11-x86_64: WARNINGS
linux-3.7.4-x86_64: WARNINGS
linux-3.8-x86_64: WARNINGS
linux-3.9.2-x86_64: WARNINGS
linux-3.10.1-x86_64: WARNINGS
linux-3.11.1-x86_64: OK
linux-3.12.67-x86_64: OK
linux-3.13.11-x86_64: WARNINGS
linux-3.14.9-x86_64: WARNINGS
linux-3.15.2-x86_64: WARNINGS
linux-3.16.7-x86_64: WARNINGS
linux-3.17.8-x86_64: ERRORS
linux-3.18.7-x86_64: ERRORS
linux-3.19-x86_64: ERRORS
linux-4.0.9-x86_64: ERRORS
linux-4.1.33-x86_64: ERRORS
linux-4.2.8-x86_64: ERRORS
linux-4.3.6-x86_64: ERRORS
linux-4.4.22-x86_64: ERRORS
linux-4.5.7-x86_64: ERRORS
linux-4.6.7-x86_64: ERRORS
linux-4.7.5-x86_64: ERRORS
linux-4.8-x86_64: OK
linux-4.9-x86_64: OK
apps: WARNINGS
spec-git: OK
sparse: WARNINGS
Detailed results are available here:
http://www.xs4all.nl/~hverkuil/logs/Thursday.log
Full logs are available here:
http://www.xs4all.nl/~hverkuil/logs/Thursday.tar.bz2
The Media Infrastructure API from this daily build is here:
http://www.xs4all.nl/~hverkuil/spec/index.html
^ permalink raw reply
* [RFC 1/1] add TPM2 version of create_tpm2_key and libtpm2.so engine
From: James Bottomley @ 2016-12-22 4:56 UTC (permalink / raw)
To: tpmdd-devel, trousers-tech, ibmtpm20tss-users, openssl-dev
In-Reply-To: <1482382526.2350.57.camel@HansenPartnership.com>
Proof of concept patch to wrap RSA (and eventually other) keys in TPM2
format and use them to load into a TPM2 to perform signatures.
This scheme has significant limitations over TPM1.2 in that TPM2
insists on knowing and validating the signature, so it will only sign
stuff it knows the OID to. That's also why the signature has to be
parsed into an X509_SIG before signing.
Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
---
Makefile.am | 12 +-
create_tpm2_key.c | 381 ++++++++++++++++++++++++++++++++++++++++++
e_tpm2.c | 482 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
tpm2-asn.h | 35 ++++
tpm2-common.c | 172 +++++++++++++++++++
tpm2-common.h | 10 ++
6 files changed, 1090 insertions(+), 2 deletions(-)
create mode 100644 create_tpm2_key.c
create mode 100644 e_tpm2.c
create mode 100644 tpm2-asn.h
create mode 100644 tpm2-common.c
create mode 100644 tpm2-common.h
diff --git a/Makefile.am b/Makefile.am
index 4932fae..a704d8c 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -2,12 +2,20 @@ SUBDIRS=. test
EXTRA_DIST = README openssl.cnf.sample
-openssl_engine_LTLIBRARIES=libtpm.la
-bin_PROGRAMS=create_tpm_key
+openssl_engine_LTLIBRARIES=libtpm.la libtpm2.la
+bin_PROGRAMS=create_tpm_key create_tpm2_key
openssl_enginedir=@libdir@/openssl/engines
libtpm_la_LIBADD=-lcrypto -lc -ltspi
libtpm_la_SOURCES=e_tpm.c e_tpm.h e_tpm_err.c
+libtpm2_la_LIBADD=-lcrypto -lc -ltss
+libtpm2_la_SOURCES=e_tpm2.c tpm2-common.c
+libtpm2_la_CFLAGS=-g -Werror
+
create_tpm_key_SOURCES=create_tpm_key.c
create_tpm_key_LDADD=-lcrypto -ltspi
+
+create_tpm2_key_SOURCES=create_tpm2_key.c tpm2-common.c
+create_tpm2_key_LDADD=-lcrypto -ltss
+create_tpm2_key_CFLAGS=-Werror
diff --git a/create_tpm2_key.c b/create_tpm2_key.c
new file mode 100644
index 0000000..001bf1d
--- /dev/null
+++ b/create_tpm2_key.c
@@ -0,0 +1,381 @@
+/*
+ *
+ * Copyright (C) 2016 James Bottomley <James.Bottomley@HansenPartnership.com>
+ *
+ * GPLv2
+ */
+
+
+#include <stdio.h>
+#include <getopt.h>
+#include <string.h>
+#include <strings.h>
+#include <errno.h>
+
+#include <openssl/rsa.h>
+#include <openssl/pem.h>
+#include <openssl/evp.h>
+#include <openssl/err.h>
+#include <openssl/rand.h>
+
+#include <tss2/tss.h>
+#include <tss2/tssutils.h>
+#include <tss2/tssmarshal.h>
+
+#include "tpm2-asn.h"
+#include "tpm2-common.h"
+
+static struct option long_options[] = {
+ {"enc-scheme", 1, 0, 'e'},
+ {"name-scheme", 1, 0, 'n'},
+ {"key-size", 1, 0, 's'},
+ {"auth", 0, 0, 'a'},
+ {"popup", 0, 0, 'p'},
+ {"wrap", 1, 0, 'w'},
+ {"help", 0, 0, 'h'},
+ {0, 0, 0, 0}
+};
+
+static TPM_ALG_ID name_alg = TPM_ALG_SHA256;
+static int name_alg_size = SHA256_DIGEST_SIZE;
+
+void
+usage(char *argv0)
+{
+ fprintf(stderr, "\t%s: create a TPM key and write it to disk\n"
+ "\tusage: %s [options] <filename>\n\n"
+ "\tOptions:\n"
+ "\t\t-e|--enc-scheme encryption scheme to use [PKCSV15] or OAEP\n"
+ "\t\t-n|--name-scheme name algorithm to use sha1 [sha256] sha384 sha512\n"
+ "\t\t-s|--key-size key size in bits [2048]\n"
+ "\t\t-a|--auth require a password for the key [NO]\n"
+ "\t\t-p|--popup use TSS GUI popup dialogs to get the password "
+ "for the\n\t\t\t\t key [NO] (implies --auth)\n"
+ "\t\t-w|--wrap [file] wrap an existing openssl PEM key\n"
+ "\t\t-h|--help print this help message\n"
+ "\nReport bugs to %s\n",
+ argv0, argv0, PACKAGE_BUGREPORT);
+ exit(-1);
+}
+
+void
+openssl_print_errors()
+{
+ ERR_load_ERR_strings();
+ ERR_load_crypto_strings();
+ ERR_print_errors_fp(stderr);
+}
+
+int
+openssl_write_tpmfile(const char *file, BYTE *pubkey, int pubkey_len,
+ BYTE *privkey, int privkey_len)
+{
+ TSSLOADABLE tssl;
+ BIO *outb;
+
+ if ((outb = BIO_new_file(file, "w")) == NULL) {
+ fprintf(stderr, "Error opening file for write: %s\n", file);
+ return 1;
+ }
+ tssl.pubkey = ASN1_OCTET_STRING_new();
+ tssl.privkey = ASN1_OCTET_STRING_new();
+ printf("setting pubkey len %d\n", pubkey_len);
+ ASN1_STRING_set(tssl.pubkey, pubkey, pubkey_len);
+ printf("setting privkey len %d\n", privkey_len);
+ ASN1_STRING_set(tssl.privkey, privkey, privkey_len);
+
+ PEM_write_bio_TSSLOADABLE(outb, &tssl);
+ BIO_free(outb);
+ return 0;
+}
+
+EVP_PKEY *
+openssl_read_key(char *filename)
+{
+ BIO *b = NULL;
+ EVP_PKEY *pkey;
+
+ b = BIO_new_file(filename, "r");
+ if (b == NULL) {
+ fprintf(stderr, "Error opening file for read: %s\n", filename);
+ return NULL;
+ }
+
+ if ((pkey = PEM_read_bio_PrivateKey(b, NULL, PEM_def_callback, NULL)) == NULL) {
+ fprintf(stderr, "Reading key %s from disk failed.\n", filename);
+ openssl_print_errors();
+ }
+ BIO_free(b);
+
+ return pkey;
+}
+
+TPM_RC openssl_to_tpm_public_rsa(TPMT_PUBLIC *pub, EVP_PKEY *pkey)
+{
+ RSA *rsa = EVP_PKEY_get1_RSA(pkey);
+ BIGNUM *n, *e;
+ int size = RSA_size(rsa);
+ unsigned long exp;
+
+ if (size > MAX_RSA_KEY_BYTES)
+ return TPM_RC_KEY_SIZE;
+
+#if OPENSSL_VERSION_NUMBER < 0x10100000
+ n = rsa->n;
+ e = rsa->e;
+#else
+ RSA_get0_key(&n, &e, NULL);
+#endif
+ exp = BN_get_word(e);
+ /* TPM limitations means exponents must be under a word in size */
+ if (exp == 0xffffffffL)
+ return TPM_RC_KEY_SIZE;
+
+ pub->type = TPM_ALG_RSA;
+ pub->nameAlg = name_alg;
+ pub->objectAttributes.val = TPMA_OBJECT_NODA |
+ TPMA_OBJECT_SIGN |
+ TPMA_OBJECT_DECRYPT |
+ TPMA_OBJECT_USERWITHAUTH;
+ pub->authPolicy.t.size = 0;
+ pub->parameters.rsaDetail.symmetric.algorithm = TPM_ALG_NULL;
+ pub->parameters.rsaDetail.scheme.scheme = TPM_ALG_NULL;
+ pub->parameters.rsaDetail.keyBits = size*8;
+ if (exp == 0x10001)
+ pub->parameters.rsaDetail.exponent = 0;
+ else
+ pub->parameters.rsaDetail.exponent = exp;
+
+ pub->unique.rsa.t.size = BN_bn2bin(n, pub->unique.rsa.t.buffer);
+
+ return 0;
+}
+
+TPM_RC openssl_to_tpm_public(TPM2B_PUBLIC *pub, EVP_PKEY *pkey)
+{
+ TPMT_PUBLIC *tpub = &pub->publicArea;
+ pub->size = sizeof(*pub);
+
+ switch (EVP_PKEY_type(pkey->type)) {
+ case EVP_PKEY_RSA:
+ return openssl_to_tpm_public_rsa(tpub, pkey);
+ default:
+ break;
+ }
+ return TPM_RC_ASYMMETRIC;
+}
+
+TPM_RC openssl_to_tpm_private_rsa(TPMT_SENSITIVE *s, EVP_PKEY *pkey)
+{
+ BIGNUM *q;
+ TPM2B_PRIVATE_KEY_RSA *t2brsa = &s->sensitive.rsa;
+ RSA *rsa = EVP_PKEY_get1_RSA(pkey);
+
+#if OPENSSL_VERSION_NUMBER < 0x10100000
+ q = rsa->q;
+#else
+ BIGNUM *p;
+
+ RSA_get0_factors(rsa, &p, &q);
+#endif
+
+ if (!q)
+ return TPM_RC_ASYMMETRIC;
+
+ s->sensitiveType = TPM_ALG_RSA;
+ s->seedValue.b.size = 0;
+
+ t2brsa->t.size = BN_bn2bin(q, t2brsa->t.buffer);
+ return 0;
+}
+
+TPM_RC openssl_to_tpm_private(TPMT_SENSITIVE *priv, EVP_PKEY *pkey)
+{
+ switch (EVP_PKEY_type(pkey->type)) {
+ case EVP_PKEY_RSA:
+ return openssl_to_tpm_private_rsa(priv, pkey);
+ default:
+ break;
+ }
+ return TPM_RC_ASYMMETRIC;
+}
+
+TPM_RC wrap_key(TPM2B_PRIVATE *priv, const char *password, EVP_PKEY *pkey)
+{
+ TPMT_SENSITIVE s;
+ TPM2B_SENSITIVE b;
+ BYTE *buf;
+ int32_t size;
+ TPM_RC rc;
+
+ memset(&b, 0, sizeof(b));
+ memset(&s, 0, sizeof(s));
+
+ openssl_to_tpm_private(&s, pkey);
+
+ if (password) {
+ int len = strlen(password);
+
+ memcpy(s.authValue.b.buffer, password, len);
+ s.authValue.b.size = len;
+ } else {
+ s.authValue.b.size = 0;
+ }
+ size = sizeof(s);
+ buf = b.b.buffer;
+ rc = TSS_TPMT_SENSITIVE_Marshal(&s, &b.b.size, &buf, &size);
+ if (rc)
+ tpm2_error(rc, "TSS_TPMT_SENSITIVE_Marshal");
+
+ size = sizeof(*priv);
+ buf = priv->b.buffer;
+ priv->b.size = 0;
+ /* no encryption means innerIntegrity and outerIntegrity are
+ * absent, so the TPM2B_PRIVATE is a TPMT_SENSITIVE*/
+ rc = TSS_TPM2B_PRIVATE_Marshal((TPM2B_PRIVATE *)&b, &priv->b.size, &buf, &size);
+ if (rc)
+ tpm2_error(rc, "TSS_TPM2B_PRIVATE_Marshal");
+
+ return TPM_RC_ASYMMETRIC;
+}
+
+int main(int argc, char **argv)
+{
+ char *filename, c, *wrap = NULL, *auth = NULL;
+ int option_index;
+ const char *reason;
+ TSS_CONTEXT *tssContext = NULL;
+ TPM_HANDLE parent = 0;
+ TPM_RC rc = 0;
+ BYTE pubkey[sizeof(TPM2B_PUBLIC)],privkey[sizeof(TPM2B_PRIVATE)], *buffer;
+ uint16_t pubkey_len, privkey_len;
+ int32_t size;
+
+
+ while (1) {
+ option_index = 0;
+ c = getopt_long(argc, argv, "n:ahw:",
+ long_options, &option_index);
+ if (c == -1)
+ break;
+
+ switch (c) {
+ case 'a':
+ auth = malloc(128);
+ break;
+ case 'h':
+ usage(argv[0]);
+ break;
+ case 'n':
+ if (!strcasecmp("sha1", optarg)) {
+ name_alg = TPM_ALG_SHA1;
+ name_alg_size = SHA1_DIGEST_SIZE;
+ } else if (strcasecmp("sha256", optarg)) {
+ /* default, do nothing */
+ } else if (strcasecmp("sha384", optarg)) {
+ name_alg = TPM_ALG_SHA384;
+ name_alg_size = SHA384_DIGEST_SIZE;
+#ifdef TPM_ALG_SHA512
+ } else if (strcasecmp("sha512", optarg)) {
+ name_alg = TPM_ALG_SHA512;
+ name_alg_size = SHA512_DIGEST_SIZE;
+#endif
+ } else {
+ usage(argv[0]);
+ }
+ break;
+ case 'w':
+ wrap = optarg;
+ break;
+ default:
+ usage(argv[0]);
+ break;
+ }
+ }
+
+ filename = argv[argc - 1];
+
+ if (argc < 2)
+ usage(argv[0]);
+
+ if (auth) {
+ if (EVP_read_pw_string(auth, 128, "Enter TPM key authority: ", 1)) {
+ fprintf(stderr, "Passwords do not match\n");
+ exit(1);
+ }
+ }
+
+ rc = TSS_Create(&tssContext);
+ if (rc) {
+ reason = "TSS_Create";
+ goto out_err;
+ }
+
+ if (wrap) {
+ Import_In iin;
+ Import_Out iout;
+ EVP_PKEY *pkey;
+
+ /* may be needed to decrypt the key */
+ OpenSSL_add_all_ciphers();
+ pkey = openssl_read_key(wrap);
+ if (!pkey) {
+ reason = "unable to read key";
+ goto out_delete;
+ }
+
+ rc = tpm2_load_srk(tssContext, &parent, NULL, NULL);
+ if (rc) {
+ reason = "tpm2_load_srk";
+ goto out_delete;
+ }
+ iin.parentHandle = parent;
+ iin.encryptionKey.t.size = 0;
+ openssl_to_tpm_public(&iin.objectPublic, pkey);
+ /* set random iin.symSeed */
+ iin.inSymSeed.t.size = 0;
+ iin.symmetricAlg.algorithm = TPM_ALG_NULL;
+ wrap_key(&iin.duplicate, auth, pkey);
+ openssl_to_tpm_public(&iin.objectPublic, pkey);
+ rc = TSS_Execute(tssContext,
+ (RESPONSE_PARAMETERS *)&iout,
+ (COMMAND_PARAMETERS *)&iin,
+ NULL,
+ TPM_CC_Import,
+ TPM_RS_PW, NULL, 0,
+ TPM_RH_NULL, NULL, 0,
+ TPM_RH_NULL, NULL, 0,
+ TPM_RH_NULL, NULL, 0);
+ if (rc) {
+ reason = "TPM2_Import";
+ goto out_flush;
+ }
+ tpm2_flush_handle(tssContext, parent);
+ buffer = pubkey;
+ pubkey_len = 0;
+ size = sizeof(pubkey);
+ TSS_TPM2B_PUBLIC_Marshal(&iin.objectPublic, &pubkey_len, &buffer, &size);
+ printf("MARSHAL to %d of %ld\n", (pubkey[0]*256) + pubkey[1],
+ sizeof(pubkey));
+ buffer = privkey;
+ privkey_len = 0;
+ size = sizeof(privkey);
+ TSS_TPM2B_PRIVATE_Marshal(&iout.outPrivate, &privkey_len, &buffer, &size);
+ printf("MARSHAL to %d of %ld\n", (privkey[0]*256) + privkey[1],
+ sizeof(privkey));
+ } else {
+ pubkey_len = 0;
+ privkey_len = 0;
+ }
+ openssl_write_tpmfile(filename, pubkey, pubkey_len, privkey, privkey_len);
+ exit(0);
+
+ out_flush:
+ tpm2_flush_handle(tssContext, parent);
+ out_delete:
+ TSS_Delete(tssContext);
+ out_err:
+ tpm2_error(rc, reason);
+
+ exit(1);
+}
diff --git a/e_tpm2.c b/e_tpm2.c
new file mode 100644
index 0000000..298282c
--- /dev/null
+++ b/e_tpm2.c
@@ -0,0 +1,482 @@
+
+/*
+ * Copyright (C) 2016 James.Bottomley@HansenPartnership.com
+ *
+ * GPLv2
+ *
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include <openssl/crypto.h>
+#include <openssl/dso.h>
+#include <openssl/engine.h>
+#include <openssl/evp.h>
+#include <openssl/objects.h>
+#include <openssl/sha.h>
+#include <openssl/bn.h>
+#include <openssl/pem.h>
+#include <openssl/x509.h>
+
+#include <tss2/tss.h>
+#include <tss2/tssutils.h>
+#include <tss2/tssmarshal.h>
+#include <tss2/tssresponsecode.h>
+#include <tss2/Unmarshal_fp.h>
+
+#include "tpm2-asn.h"
+#include "tpm2-common.h"
+
+#define TPM2_ENGINE_EX_DATA_UNINIT -1
+
+/* structure pointed to by the RSA object's app_data pointer */
+struct rsa_app_data
+{
+ TPM_HANDLE hKey;
+};
+
+static TSS_CONTEXT *tssContext;
+static char *srk_auth;
+
+static int tpm2_engine_init(ENGINE * e)
+{
+ TPM_RC rc;
+
+ rc = TSS_Create(&tssContext);
+ if (!rc)
+ return 1;
+
+ tpm2_error(rc, "TSS_Create");
+ return 0;
+}
+
+static int tpm2_engine_finish(ENGINE * e)
+{
+ tpm2_flush_srk(tssContext);
+ if (tssContext)
+ TSS_Delete(tssContext);
+
+ return 1;
+}
+
+static int tpm2_create_srk_policy(char *secret)
+{
+ int len;
+
+ if (!secret) {
+ OPENSSL_free(srk_auth);
+ srk_auth = NULL;
+ } else {
+ len = strlen(secret);
+ srk_auth = OPENSSL_malloc(len);
+ strcpy(srk_auth, secret);
+ }
+ return 1;
+}
+
+#define TPM_CMD_PIN ENGINE_CMD_BASE
+
+static int tpm2_engine_ctrl(ENGINE * e, int cmd, long i, void *p, void (*f) ())
+{
+ if (!tssContext) {
+ fprintf(stderr, "tpm2: engine not initialized\n");
+ return 0;
+ }
+
+
+ switch (cmd) {
+ case TPM_CMD_PIN:
+ return tpm2_create_srk_policy(p);
+ default:
+ break;
+ }
+ fprintf(stderr, "tpm2: engine command not implemented\n");
+
+ return 0;
+}
+
+
+#ifndef OPENSSL_NO_RSA
+/* rsa functions */
+static int tpm2_rsa_init(RSA *rsa);
+static int tpm2_rsa_finish(RSA *rsa);
+static int tpm2_rsa_pub_dec(int, const unsigned char *, unsigned char *, RSA *, int);
+static int tpm2_rsa_pub_enc(int, const unsigned char *, unsigned char *, RSA *, int);
+static int tpm2_rsa_priv_dec(int, const unsigned char *, unsigned char *, RSA *, int);
+static int tpm2_rsa_priv_enc(int, const unsigned char *, unsigned char *, RSA *, int);
+//static int tpm2_rsa_sign(int, const unsigned char *, unsigned int, unsigned char *, unsigned int *, const RSA *);
+#endif
+
+/* The definitions for control commands specific to this engine */
+#define TPM2_CMD_PIN ENGINE_CMD_BASE
+static const ENGINE_CMD_DEFN tpm2_cmd_defns[] = {
+ {TPM2_CMD_PIN,
+ "PIN",
+ "Specifies the secret for the SRK (default is plaintext, else set SECRET_MODE)",
+ ENGINE_CMD_FLAG_STRING},
+ /* end */
+ {0, NULL, NULL, 0}
+};
+
+#ifndef OPENSSL_NO_RSA
+static RSA_METHOD tpm2_rsa = {
+ "TPM RSA method",
+ tpm2_rsa_pub_enc,
+ tpm2_rsa_pub_dec,
+ tpm2_rsa_priv_enc,
+ tpm2_rsa_priv_dec,
+ NULL, /* set in tpm2_engine_init */
+ BN_mod_exp_mont,
+ tpm2_rsa_init,
+ tpm2_rsa_finish,
+ (RSA_FLAG_SIGN_VER | RSA_FLAG_NO_BLINDING),
+ NULL,
+ NULL, /* sign */
+ NULL, /* verify */
+ NULL, /* keygen */
+};
+#endif
+
+/* varibles used to get/set CRYPTO_EX_DATA values */
+static int ex_app_data = TPM2_ENGINE_EX_DATA_UNINIT;
+
+static EVP_PKEY *tpm2_engine_load_key(ENGINE *e, const char *key_id,
+ UI_METHOD *ui, void *cb_data)
+{
+ TPM_HANDLE key,srk;
+ TPM_RC rc;
+ EVP_PKEY *pkey;
+ RSA *rsa;
+ BIO *bf;
+ TSSLOADABLE *tssl;
+ Load_In in;
+ Load_Out out;
+ struct rsa_app_data *app_data;
+ BYTE *buffer;
+ INT32 size;
+
+ if (!key_id) {
+ fprintf(stderr, "key_id is NULL\n");
+ return NULL;
+ }
+
+ rc = tpm2_load_srk(tssContext, &srk, srk_auth, NULL);
+ if (rc) {
+ tpm2_error(rc, "tpm2_load_srk");
+ return NULL;
+ }
+
+ bf = BIO_new_file(key_id, "r");
+ if (!bf) {
+ fprintf(stderr, "File %s does not exist or cannot be read\n", key_id);
+ goto err;
+ }
+
+ tssl = PEM_read_bio_TSSLOADABLE(bf, NULL, NULL, NULL);
+ if (!tssl) {
+ fprintf(stderr, "Failed to parse file %s\n", key_id);
+ BIO_free(bf);
+ goto err;
+ }
+
+ BIO_free(bf);
+
+ in.parentHandle = srk;
+ buffer = tssl->privkey->data;
+ size = tssl->privkey->length;
+ TPM2B_PRIVATE_Unmarshal(&in.inPrivate, &buffer, &size);
+ buffer = tssl->pubkey->data;
+ size = tssl->pubkey->length;
+ TPM2B_PUBLIC_Unmarshal(&in.inPublic, &buffer, &size, FALSE);
+
+ rc = TSS_Execute(tssContext,
+ (RESPONSE_PARAMETERS *)&out,
+ (COMMAND_PARAMETERS *)&in,
+ NULL,
+ TPM_CC_Load,
+ TPM_RS_PW, NULL, 0,
+ TPM_RH_NULL, NULL, 0,
+ TPM_RH_NULL, NULL, 0,
+ TPM_RH_NULL, NULL, 0);
+ TSSLOADABLE_free(tssl);
+ if (rc) {
+ tpm2_error(rc, "TPM2_Load");
+ goto err;
+ }
+ key = out.objectHandle;
+
+ app_data = OPENSSL_malloc(sizeof(struct rsa_app_data));
+ if (!app_data) {
+ fprintf(stderr, "Failed to allocate app_data\n");
+ goto err_key;
+ }
+ /* create the new objects to return */
+ pkey = tpm2_to_openssl_public(&in.inPublic.publicArea);
+ if (!pkey) {
+ fprintf(stderr, "Failed to allocate a new EVP_KEY\n");
+ goto err_key;
+ }
+ app_data->hKey = key;
+
+ rsa = EVP_PKEY_get1_RSA(pkey);
+ RSA_set_ex_data(rsa, ex_app_data, app_data);
+ rsa->meth = &tpm2_rsa;
+ /* call our local init function here */
+ rsa->meth->init(rsa);
+
+ /* release the reference EVP_PKEY_get1_RSA obtained */
+ RSA_free(rsa);
+ return pkey;
+ err_key:
+ tpm2_flush_handle(tssContext, key);
+ err:
+ tpm2_flush_handle(tssContext, srk);
+
+ return NULL;
+}
+
+/* Constants used when creating the ENGINE */
+static const char *engine_tpm2_id = "tpm2";
+static const char *engine_tpm2_name = "TPM2 hardware engine support";
+
+/* This internal function is used by ENGINE_tpm() and possibly by the
+ * "dynamic" ENGINE support too */
+static int tpm2_bind_helper(ENGINE * e)
+{
+ if (!ENGINE_set_id(e, engine_tpm2_id) ||
+ !ENGINE_set_name(e, engine_tpm2_name) ||
+#ifndef OPENSSL_NO_RSA
+ !ENGINE_set_RSA(e, &tpm2_rsa) ||
+#endif
+ !ENGINE_set_init_function(e, tpm2_engine_init) ||
+ !ENGINE_set_finish_function(e, tpm2_engine_finish) ||
+ !ENGINE_set_ctrl_function(e, tpm2_engine_ctrl) ||
+ !ENGINE_set_load_pubkey_function(e, tpm2_engine_load_key) ||
+ !ENGINE_set_load_privkey_function(e, tpm2_engine_load_key) ||
+ !ENGINE_set_cmd_defns(e, tpm2_cmd_defns))
+ return 0;
+
+ return 1;
+}
+
+
+#ifndef OPENSSL_NO_RSA
+static int tpm2_rsa_init(RSA *rsa)
+{
+ if (ex_app_data == TPM2_ENGINE_EX_DATA_UNINIT)
+ ex_app_data = RSA_get_ex_new_index(0, NULL, NULL, NULL, NULL);
+
+ if (ex_app_data == TPM2_ENGINE_EX_DATA_UNINIT) {
+ fprintf(stderr, "Failed to get memory for external data\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+static int tpm2_rsa_finish(RSA *rsa)
+{
+ struct rsa_app_data *app_data = RSA_get_ex_data(rsa, ex_app_data);
+
+ if (!app_data)
+ return 1;
+
+ if (app_data->hKey) {
+ tpm2_flush_handle(tssContext, app_data->hKey);
+ tpm2_flush_srk(tssContext);
+ app_data->hKey = 0;
+ }
+
+ OPENSSL_free(app_data);
+
+ return 1;
+}
+
+static int tpm2_rsa_pub_dec(int flen,
+ const unsigned char *from,
+ unsigned char *to,
+ RSA *rsa,
+ int padding)
+{
+ int rv;
+
+ rv = RSA_PKCS1_SSLeay()->rsa_pub_dec(flen, from, to, rsa,
+ padding);
+ if (rv < 0) {
+ fprintf(stderr, "rsa_pub_dec failed\n");
+ return 0;
+ }
+
+ return rv;
+}
+
+static int tpm2_rsa_priv_dec(int flen,
+ const unsigned char *from,
+ unsigned char *to,
+ RSA *rsa,
+ int padding)
+{
+ struct rsa_app_data *app_data = RSA_get_ex_data(rsa, ex_app_data);
+ int rv;
+
+ if (!app_data) {
+ rv = RSA_PKCS1_SSLeay()->rsa_priv_dec(flen, from, to, rsa,
+ padding);
+ if (rv < 0)
+ fprintf(stderr, "rsa_priv_dec failed\n");
+
+ return rv;
+ }
+
+ if (!app_data->hKey) {
+ fprintf(stderr, "No TPM key defined\n");
+ return 0;
+ }
+
+ fprintf(stderr, "rsa_priv_dec currently unimplemented\n");
+ return 0;
+}
+
+static int tpm2_rsa_pub_enc(int flen,
+ const unsigned char *from,
+ unsigned char *to,
+ RSA *rsa,
+ int padding)
+{
+ struct rsa_app_data *app_data = RSA_get_ex_data(rsa, ex_app_data);
+ int rv;
+
+ if (!app_data) {
+ rv = RSA_PKCS1_SSLeay()->rsa_pub_enc(flen, from, to, rsa,
+ padding);
+ if (rv < 0)
+ fprintf(stderr, "rsa_pub_enc failed\n");
+
+ return rv;
+ }
+ fprintf(stderr, "rsa_pub_enc not implemented");
+ return 0;
+}
+
+static int tpm2_rsa_priv_enc(int flen,
+ const unsigned char *from,
+ unsigned char *to,
+ RSA *rsa,
+ int padding)
+{
+ struct rsa_app_data *app_data = RSA_get_ex_data(rsa, ex_app_data);
+ TPM_RC rc;
+ int rv;
+ Sign_In in;
+ Sign_Out out;
+ X509_SIG *x509_sig;
+ const unsigned char *buf = from;
+ TPM_ALG_ID hash_alg;
+
+ if (!app_data) {
+ rv = RSA_PKCS1_SSLeay()->rsa_priv_enc(flen, from, to, rsa,
+ padding);
+ if (rv < 0)
+ fprintf(stderr, "pass through signing failed\n");
+
+ return rv;
+ }
+
+ rv = -1;
+ if (padding != RSA_PKCS1_PADDING) {
+ fprintf(stderr, "Non PKCS1 padding asked for\n");
+ return rv;
+ }
+
+ if (!app_data->hKey) {
+ fprintf(stderr, "No RSA key set for signature\n");
+ return rv;
+ }
+
+ x509_sig = d2i_X509_SIG(NULL, &buf, flen);
+ if (!x509_sig) {
+ fprintf(stderr, "buffer for signing is not an X509_SIG type\n");
+ return rv;
+ }
+
+ switch (OBJ_obj2nid(x509_sig->algor->algorithm)) {
+ case NID_sha1:
+ hash_alg = TPM_ALG_SHA1;
+ break;
+ case NID_sha256:
+ hash_alg = TPM_ALG_SHA256;
+ break;
+ case NID_sha384:
+ hash_alg = TPM_ALG_SHA384;
+ break;
+#ifdef TPM_ALG_SHA512
+ case NID_sha512:
+ hash_alg = TPM_ALG_SHA512;
+ break;
+#endif
+ default: {
+ char buf[512];
+ OBJ_obj2txt(buf, sizeof(buf), x509_sig->algor->algorithm, 0);
+ fprintf(stderr, "unrecognised signature algorithm %s\n", buf);
+ goto out_free;
+ }
+ }
+
+ in.keyHandle = app_data->hKey;
+ in.digest.t.size = x509_sig->digest->length;
+ memcpy(&in.digest.t.buffer, x509_sig->digest->data,
+ x509_sig->digest->length);
+ in.inScheme.scheme = TPM_ALG_RSASSA;
+ in.inScheme.details.any.hashAlg = hash_alg;
+ /* no proof means NULL validation ticket */
+ in.validation.tag = TPM_ST_HASHCHECK;
+ in.validation.hierarchy = TPM_RH_NULL;
+ in.validation.digest.t.size = 0;
+
+ rc = TSS_Execute(tssContext,
+ (RESPONSE_PARAMETERS *)&out,
+ (COMMAND_PARAMETERS *)&in,
+ NULL,
+ TPM_CC_Sign,
+ TPM_RS_PW, NULL, 0,
+ TPM_RH_NULL, NULL, 0,
+ TPM_RH_NULL, NULL, 0,
+ TPM_RH_NULL, NULL, 0);
+
+ if (rc) {
+ tpm2_error(rc, "TPM2_Sign");
+ goto out_free;
+ }
+
+
+ memcpy(to, out.signature.signature.rsassa.sig.t.buffer,
+ out.signature.signature.rsassa.sig.t.size);
+
+ rv = out.signature.signature.rsassa.sig.t.size;
+
+ out_free:
+ X509_SIG_free(x509_sig);
+ return rv;
+}
+
+#endif
+
+/* This stuff is needed if this ENGINE is being compiled into a self-contained
+ * shared-library. */
+static int tpm2_bind_fn(ENGINE * e, const char *id)
+{
+ if (id && (strcmp(id, engine_tpm2_id) != 0)) {
+ fprintf(stderr, "Called for id %s != my id %s\n",
+ id, engine_tpm2_id);
+ return 0;
+ }
+ if (!tpm2_bind_helper(e)) {
+ fprintf(stderr, "tpm2_bind_helper failed\n");
+ return 0;
+ }
+ return 1;
+}
+
+IMPLEMENT_DYNAMIC_CHECK_FN()
+IMPLEMENT_DYNAMIC_BIND_FN(tpm2_bind_fn)
diff --git a/tpm2-asn.h b/tpm2-asn.h
new file mode 100644
index 0000000..abbe294
--- /dev/null
+++ b/tpm2-asn.h
@@ -0,0 +1,35 @@
+/* Copyright (C) 2016 James Bottomley <James.Bottomley@HansenPartnership.com>
+ *
+ * GPLv2
+ */
+#ifndef _TPM2_ASN_H
+#define _TPM2_ASN_H
+
+#include <openssl/asn1t.h>
+
+/*
+ * Define the format of a TSS2 key file. The current format is a
+ * symmetrically encrypted private key produced by TSS2_Import and
+ * the TPM2 format public key which contains things like the policy but
+ * which is cryptographically tied to the private key
+ */
+
+typedef struct {
+ ASN1_OCTET_STRING *pubkey;
+ ASN1_OCTET_STRING *privkey;
+} TSSLOADABLE;
+
+ASN1_SEQUENCE(TSSLOADABLE) = {
+ ASN1_SIMPLE(TSSLOADABLE, pubkey, ASN1_OCTET_STRING),
+ ASN1_SIMPLE(TSSLOADABLE, privkey, ASN1_OCTET_STRING)
+} ASN1_SEQUENCE_END(TSSLOADABLE)
+
+IMPLEMENT_ASN1_FUNCTIONS(TSSLOADABLE);
+
+/* This is the PEM guard tag */
+#define TSSLOADABLE_PEM_STRING "TSS2 KEY BLOB"
+
+static IMPLEMENT_PEM_write_bio(TSSLOADABLE, TSSLOADABLE, TSSLOADABLE_PEM_STRING, TSSLOADABLE)
+static IMPLEMENT_PEM_read_bio(TSSLOADABLE, TSSLOADABLE, TSSLOADABLE_PEM_STRING, TSSLOADABLE)
+
+#endif
diff --git a/tpm2-common.c b/tpm2-common.c
new file mode 100644
index 0000000..b544f2f
--- /dev/null
+++ b/tpm2-common.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2016 James Bottomley <James.Bottomley@HansenPartnership.com>
+ *
+ * GPLv2
+ */
+
+#include <stdio.h>
+
+#include <openssl/evp.h>
+#include <openssl/rsa.h>
+
+#include <tss2/tss.h>
+#include <tss2/tssresponsecode.h>
+
+#include "tpm2-common.h"
+
+void tpm2_error(TPM_RC rc, const char *reason)
+{
+ const char *msg, *submsg, *num;
+
+ fprintf(stderr, "%s failed with %d\n", reason, rc);
+ TSS_ResponseCode_toString(&msg, &submsg, &num, rc);
+ fprintf(stderr, "%s%s%s\n", msg, submsg, num);
+}
+
+
+static TPM_HANDLE hSRK = 0;
+
+TPM_HANDLE tpm2_load_srk(TSS_CONTEXT *tssContext, TPM_HANDLE *h, const char *auth,TPM2B_PUBLIC *pub)
+{
+ static TPM2B_PUBLIC srk_pub;
+ TPM_RC rc;
+ CreatePrimary_In in;
+ CreatePrimary_Out out;
+
+ if (hSRK)
+ goto out;
+
+ /* SPS owner */
+ in.primaryHandle = TPM_RH_OWNER;
+ /* assume no owner password */
+ in.inSensitive.sensitive.userAuth.t.size = 0;
+ /* no sensitive date for storage keys */
+ in.inSensitive.sensitive.data.t.size = 0;
+ /* no outside info */
+ in.outsideInfo.t.size = 0;
+ /* no PCR state */
+ in.creationPCR.count = 0;
+
+ /* public parameters for an RSA2048 key */
+ in.inPublic.publicArea.type = TPM_ALG_RSA;
+ in.inPublic.publicArea.nameAlg = TPM_ALG_SHA256;
+ in.inPublic.publicArea.objectAttributes.val =
+ TPMA_OBJECT_NODA |
+ TPMA_OBJECT_SENSITIVEDATAORIGIN |
+ TPMA_OBJECT_USERWITHAUTH |
+ TPMA_OBJECT_DECRYPT |
+ TPMA_OBJECT_RESTRICTED;
+ in.inPublic.publicArea.parameters.rsaDetail.symmetric.algorithm = TPM_ALG_AES;
+ in.inPublic.publicArea.parameters.rsaDetail.symmetric.keyBits.aes = 128;
+ in.inPublic.publicArea.parameters.rsaDetail.symmetric.mode.aes = TPM_ALG_CFB;
+ in.inPublic.publicArea.parameters.rsaDetail.scheme.scheme = TPM_ALG_NULL;
+ in.inPublic.publicArea.parameters.rsaDetail.keyBits = 2048;
+ /* means conventional 2^16+1 */
+ in.inPublic.publicArea.parameters.rsaDetail.exponent = 0;
+ in.inPublic.publicArea.unique.rsa.t.size = 0;
+ in.inPublic.publicArea.authPolicy.t.size = 0;
+
+ rc = TSS_Execute(tssContext,
+ (RESPONSE_PARAMETERS *)&out,
+ (COMMAND_PARAMETERS *)&in,
+ NULL,
+ TPM_CC_CreatePrimary,
+ TPM_RS_PW, NULL, 0,
+ TPM_RH_NULL, NULL, 0,
+ TPM_RH_NULL, NULL, 0,
+ TPM_RH_NULL, NULL, 0);
+ if (rc)
+ return rc;
+
+ hSRK = out.objectHandle;
+ srk_pub = out.outPublic;
+ out:
+ *h = hSRK;
+ if (pub)
+ *pub = srk_pub;
+
+ return 0;
+}
+
+void tpm2_flush_srk(TSS_CONTEXT *tssContext)
+{
+ if (hSRK)
+ tpm2_flush_handle(tssContext, hSRK);
+ hSRK = 0;
+}
+
+void tpm2_flush_handle(TSS_CONTEXT *tssContext, TPM_HANDLE h)
+{
+ FlushContext_In in;
+
+ if (!h)
+ return;
+
+ in.flushHandle = h;
+ TSS_Execute(tssContext, NULL,
+ (COMMAND_PARAMETERS *)&in,
+ NULL,
+ TPM_CC_FlushContext,
+ TPM_RH_NULL, NULL, 0);
+}
+
+static EVP_PKEY *tpm2_to_openssl_public_rsa(TPMT_PUBLIC *pub)
+{
+ RSA *rsa = RSA_new();
+ EVP_PKEY *pkey;
+ unsigned long exp;
+ BIGNUM *n, *e;
+
+ if (!rsa)
+ return NULL;
+ pkey = EVP_PKEY_new();
+ if (!pkey)
+ goto err_free_rsa;
+ e = BN_new();
+ if (!e)
+ goto err_free_pkey;
+ n = BN_new();
+ if (!n)
+ goto err_free_e;
+ if (pub->parameters.rsaDetail.exponent == 0)
+ exp = 0x10001;
+ else
+ exp = pub->parameters.rsaDetail.exponent;
+ if (!BN_set_word(e, exp))
+ goto err_free;
+ if (!BN_bin2bn(pub->unique.rsa.t.buffer, pub->unique.rsa.t.size, n))
+ goto err_free;
+#if OPENSSL_VERSION_NUMBER < 0x10100000
+ rsa->n = n;
+ rsa->e = e;
+#else
+ RSA_set0_key(rsa, n, e, NULL);
+#endif
+ if (!EVP_PKEY_assign_RSA(pkey, rsa))
+ goto err_free;
+
+ return pkey;
+
+ err_free:
+ BN_free(n);
+ err_free_e:
+ BN_free(e);
+ err_free_pkey:
+ EVP_PKEY_free(pkey);
+ err_free_rsa:
+ RSA_free(rsa);
+
+ return NULL;
+}
+
+EVP_PKEY *tpm2_to_openssl_public(TPMT_PUBLIC *pub)
+{
+ switch (pub->type) {
+ case TPM_ALG_RSA:
+ return tpm2_to_openssl_public_rsa(pub);
+ default:
+ break;
+ }
+ return NULL;
+}
+
diff --git a/tpm2-common.h b/tpm2-common.h
new file mode 100644
index 0000000..197e552
--- /dev/null
+++ b/tpm2-common.h
@@ -0,0 +1,10 @@
+#ifndef _TPM2_COMMON_H
+#define _TPM2_COMMON_H
+
+void tpm2_error(TPM_RC rc, const char *reason);
+TPM_HANDLE tpm2_load_srk(TSS_CONTEXT *tssContext, TPM_HANDLE *h, const char *auth, TPM2B_PUBLIC *pub);
+void tpm2_flush_handle(TSS_CONTEXT *tssContext, TPM_HANDLE h);
+EVP_PKEY *tpm2_to_openssl_public(TPMT_PUBLIC *pub);
+void tpm2_flush_srk(TSS_CONTEXT *tssContext);
+
+#endif
--
2.6.6
--
openssl-dev mailing list
To unsubscribe: https://mta.openssl.org/mailman/listinfo/openssl-dev
^ permalink raw reply related
* [RFC 0/1] TPM2 engine support for openssl
From: James Bottomley @ 2016-12-22 4:55 UTC (permalink / raw)
To: tpmdd-devel, trousers-tech, ibmtpm20tss-users, openssl-dev
This is a basic RFC to show that it's possible to get TPM2 to act as an
engine for openssl as well as TPM1.2. The format follows as closely as
possible what happens in TPM1.2. The file format is full blown ASN.1
because we have to include both a public and private key blob. I chose
to use TSS2 KEY BLOB as the guards to distinguish it from the TPM1.2
file.
TPM2 has significant limitations over TPM1.2 in what it will sign:
basically it must recognise the signature algorithm (that's why all the
signature parsing in the rsa_priv_enc() routine). There's also another
problem in that a primary asymmetric key of the SPS must be provisioned
every time we perform this operation (which is time consuming and
annoying). I think we need to do something about this under Linux, but
I'll take that off the openssl list because they likely won't be
interested.
The authority handling is missing at the moment, but I'll add that
shortly. We should probably discuss how policy based authorisation
should be handled: I think as extensions to the key ASN.1 file.
Because of the signature recognition problem, you have to test this out
with x509 certificates:
openssl genrsa 2048 > tmp.key
create_tpm2_key -w tmp.key tmp.bin
openssl req -new -engine tpm2 -key tmp.bin -keyform e > tmp.csr
openssl x509 -req -engine tpm2 -in tmp.csr -signkey tmp.bin -keyform e -out tmp.crt
openssl x509 -text -in tmp.crt
The last step will validate you've got a genuine x509 self signed
certificate with the key from the TPM.
This kit is constructed using the IBM TSS2:
https://sourceforge.net/projects/ibmtpm20tss/
And, at the moment, it's only been validated on a software TPM2.
James
---
James Bottomley (1):
add TPM2 version of create_tpm2_key and libtpm2.so engine
Makefile.am | 12 +-
create_tpm2_key.c | 381 ++++++++++++++++++++++++++++++++++++++++++
e_tpm2.c | 482 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
tpm2-asn.h | 35 ++++
tpm2-common.c | 172 +++++++++++++++++++
tpm2-common.h | 10 ++
6 files changed, 1090 insertions(+), 2 deletions(-)
create mode 100644 create_tpm2_key.c
create mode 100644 e_tpm2.c
create mode 100644 tpm2-asn.h
create mode 100644 tpm2-common.c
create mode 100644 tpm2-common.h
--
2.6.6
------------------------------------------------------------------------------
Developer Access Program for Intel Xeon Phi Processors
Access to Intel Xeon Phi processor-based developer platforms.
With one year of Intel Parallel Studio XE.
Training and support from Colfax.
Order your platform today.http://sdm.link/intel
^ permalink raw reply
* [PATCH] ncurses: 6.0+20160625 -> 6.0+20161126
From: Huang Qiyu @ 2016-12-22 4:54 UTC (permalink / raw)
To: openembedded-core
Upgrade ncurses from 6.0+20160625 to 6.0+20161126.
Signed-off-by: Huang Qiyu <huangqy.fnst@cn.fujitsu.com>
---
.../ncurses/{ncurses_6.0+20160625.bb => ncurses_6.0+20161126.bb} | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
rename meta/recipes-core/ncurses/{ncurses_6.0+20160625.bb => ncurses_6.0+20161126.bb} (84%)
diff --git a/meta/recipes-core/ncurses/ncurses_6.0+20160625.bb b/meta/recipes-core/ncurses/ncurses_6.0+20161126.bb
similarity index 84%
rename from meta/recipes-core/ncurses/ncurses_6.0+20160625.bb
rename to meta/recipes-core/ncurses/ncurses_6.0+20161126.bb
index 6514613..7328e78 100644
--- a/meta/recipes-core/ncurses/ncurses_6.0+20160625.bb
+++ b/meta/recipes-core/ncurses/ncurses_6.0+20161126.bb
@@ -4,7 +4,7 @@ SRC_URI += "file://tic-hang.patch \
file://config.cache \
"
# commit id corresponds to the revision in package version
-SRCREV = "63dd558cb8e888d6fab5f00bbf7842736a2356b9"
+SRCREV = "3db0bd19cb50e3d9b4f2cf15b7a102fe11302068"
S = "${WORKDIR}/git"
EXTRA_OECONF += "--with-abi-version=5"
UPSTREAM_CHECK_GITTAGREGEX = "(?P<pver>\d+(\.\d+)+(\+\d+)*)"
--
2.7.4
^ permalink raw reply related
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