* [Patch v8 09/12] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR
From: Dapeng Mi @ 2025-10-15 6:44 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi, Kan Liang
In-Reply-To: <20251015064422.47437-1-dapeng1.mi@linux.intel.com>
Arch-PEBS introduces a new MSR IA32_PEBS_BASE to store the arch-PEBS
buffer physical address. This patch allocates arch-PEBS buffer and then
initialize IA32_PEBS_BASE MSR with the buffer physical address.
Co-developed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 11 ++++-
arch/x86/events/intel/ds.c | 82 ++++++++++++++++++++++++++++-----
arch/x86/events/perf_event.h | 11 ++++-
arch/x86/include/asm/intel_ds.h | 3 +-
4 files changed, 92 insertions(+), 15 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index cab2ce73ad09..41c4af6bd62c 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5227,7 +5227,13 @@ int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
static int intel_pmu_cpu_prepare(int cpu)
{
- return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
+ int ret;
+
+ ret = intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
+ if (ret)
+ return ret;
+
+ return alloc_arch_pebs_buf_on_cpu(cpu);
}
static void flip_smm_bit(void *data)
@@ -5457,6 +5463,7 @@ static void intel_pmu_cpu_starting(int cpu)
return;
init_debug_store_on_cpu(cpu);
+ init_arch_pebs_on_cpu(cpu);
/*
* Deal with CPUs that don't clear their LBRs on power-up, and that may
* even boot with LBRs enabled.
@@ -5554,6 +5561,7 @@ static void free_excl_cntrs(struct cpu_hw_events *cpuc)
static void intel_pmu_cpu_dying(int cpu)
{
fini_debug_store_on_cpu(cpu);
+ fini_arch_pebs_on_cpu(cpu);
}
void intel_cpuc_finish(struct cpu_hw_events *cpuc)
@@ -5574,6 +5582,7 @@ static void intel_pmu_cpu_dead(int cpu)
{
struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
+ release_arch_pebs_buf_on_cpu(cpu);
intel_cpuc_finish(cpuc);
if (is_hybrid() && cpuc->pmu)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 651f3709c260..1ec54b0a5d3c 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -625,13 +625,18 @@ static int alloc_pebs_buffer(int cpu)
int max, node = cpu_to_node(cpu);
void *buffer, *insn_buff, *cea;
- if (!x86_pmu.ds_pebs)
+ if (!intel_pmu_has_pebs())
return 0;
buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
if (unlikely(!buffer))
return -ENOMEM;
+ if (x86_pmu.arch_pebs) {
+ hwev->pebs_vaddr = buffer;
+ return 0;
+ }
+
/*
* HSW+ already provides us the eventing ip; no need to allocate this
* buffer then.
@@ -644,7 +649,7 @@ static int alloc_pebs_buffer(int cpu)
}
per_cpu(insn_buffer, cpu) = insn_buff;
}
- hwev->ds_pebs_vaddr = buffer;
+ hwev->pebs_vaddr = buffer;
/* Update the cpu entry area mapping */
cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
ds->pebs_buffer_base = (unsigned long) cea;
@@ -660,17 +665,20 @@ static void release_pebs_buffer(int cpu)
struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
void *cea;
- if (!x86_pmu.ds_pebs)
+ if (!intel_pmu_has_pebs())
return;
- kfree(per_cpu(insn_buffer, cpu));
- per_cpu(insn_buffer, cpu) = NULL;
+ if (x86_pmu.ds_pebs) {
+ kfree(per_cpu(insn_buffer, cpu));
+ per_cpu(insn_buffer, cpu) = NULL;
- /* Clear the fixmap */
- cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
- ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
- dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size);
- hwev->ds_pebs_vaddr = NULL;
+ /* Clear the fixmap */
+ cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
+ ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
+ }
+
+ dsfree_pages(hwev->pebs_vaddr, x86_pmu.pebs_buffer_size);
+ hwev->pebs_vaddr = NULL;
}
static int alloc_bts_buffer(int cpu)
@@ -823,6 +831,56 @@ void reserve_ds_buffers(void)
}
}
+inline int alloc_arch_pebs_buf_on_cpu(int cpu)
+{
+ if (!x86_pmu.arch_pebs)
+ return 0;
+
+ return alloc_pebs_buffer(cpu);
+}
+
+inline void release_arch_pebs_buf_on_cpu(int cpu)
+{
+ if (!x86_pmu.arch_pebs)
+ return;
+
+ release_pebs_buffer(cpu);
+}
+
+void init_arch_pebs_on_cpu(int cpu)
+{
+ struct cpu_hw_events *cpuc = per_cpu_ptr(&cpu_hw_events, cpu);
+ u64 arch_pebs_base;
+
+ if (!x86_pmu.arch_pebs)
+ return;
+
+ if (!cpuc->pebs_vaddr) {
+ WARN(1, "Fail to allocate PEBS buffer on CPU %d\n", cpu);
+ x86_pmu.pebs_active = 0;
+ return;
+ }
+
+ /*
+ * 4KB-aligned pointer of the output buffer
+ * (__alloc_pages_node() return page aligned address)
+ * Buffer Size = 4KB * 2^SIZE
+ * contiguous physical buffer (__alloc_pages_node() with order)
+ */
+ arch_pebs_base = virt_to_phys(cpuc->pebs_vaddr) | PEBS_BUFFER_SHIFT;
+ wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, (u32)arch_pebs_base,
+ (u32)(arch_pebs_base >> 32));
+ x86_pmu.pebs_active = 1;
+}
+
+inline void fini_arch_pebs_on_cpu(int cpu)
+{
+ if (!x86_pmu.arch_pebs)
+ return;
+
+ wrmsr_on_cpu(cpu, MSR_IA32_PEBS_BASE, 0, 0);
+}
+
/*
* BTS
*/
@@ -2905,8 +2963,8 @@ static void intel_pmu_drain_arch_pebs(struct pt_regs *iregs,
return;
}
- base = cpuc->ds_pebs_vaddr;
- top = (void *)((u64)cpuc->ds_pebs_vaddr +
+ base = cpuc->pebs_vaddr;
+ top = (void *)((u64)cpuc->pebs_vaddr +
(index.wr << ARCH_PEBS_INDEX_WR_SHIFT));
index.wr = 0;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index ca5289980b52..13f411bca6bc 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -283,8 +283,9 @@ struct cpu_hw_events {
* Intel DebugStore bits
*/
struct debug_store *ds;
- void *ds_pebs_vaddr;
void *ds_bts_vaddr;
+ /* DS based PEBS or arch-PEBS buffer address */
+ void *pebs_vaddr;
u64 pebs_enabled;
int n_pebs;
int n_large_pebs;
@@ -1617,6 +1618,14 @@ extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
int intel_pmu_init(void);
+int alloc_arch_pebs_buf_on_cpu(int cpu);
+
+void release_arch_pebs_buf_on_cpu(int cpu);
+
+void init_arch_pebs_on_cpu(int cpu);
+
+void fini_arch_pebs_on_cpu(int cpu);
+
void init_debug_store_on_cpu(int cpu);
void fini_debug_store_on_cpu(int cpu);
diff --git a/arch/x86/include/asm/intel_ds.h b/arch/x86/include/asm/intel_ds.h
index 5dbeac48a5b9..023c2883f9f3 100644
--- a/arch/x86/include/asm/intel_ds.h
+++ b/arch/x86/include/asm/intel_ds.h
@@ -4,7 +4,8 @@
#include <linux/percpu-defs.h>
#define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
-#define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
+#define PEBS_BUFFER_SHIFT 4
+#define PEBS_BUFFER_SIZE (PAGE_SIZE << PEBS_BUFFER_SHIFT)
/* The maximal number of PEBS events: */
#define MAX_PEBS_EVENTS_FMT4 8
--
2.34.1
^ permalink raw reply related
* [Patch v8 08/12] perf/x86/intel: Process arch-PEBS records or record fragments
From: Dapeng Mi @ 2025-10-15 6:44 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
In-Reply-To: <20251015064422.47437-1-dapeng1.mi@linux.intel.com>
A significant difference with adaptive PEBS is that arch-PEBS record
supports fragments which means an arch-PEBS record could be split into
several independent fragments which have its own arch-PEBS header in
each fragment.
This patch defines architectural PEBS record layout structures and add
helpers to process arch-PEBS records or fragments. Only legacy PEBS
groups like basic, GPR, XMM and LBR groups are supported in this patch,
the new added YMM/ZMM/OPMASK vector registers capturing would be
supported in the future.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 13 +++
arch/x86/events/intel/ds.c | 182 ++++++++++++++++++++++++++++++
arch/x86/include/asm/msr-index.h | 6 +
arch/x86/include/asm/perf_event.h | 96 ++++++++++++++++
4 files changed, 297 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index bfb123ff7c9a..cab2ce73ad09 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3215,6 +3215,19 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;
}
+ /*
+ * Arch PEBS sets bit 54 in the global status register
+ */
+ if (__test_and_clear_bit(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT,
+ (unsigned long *)&status)) {
+ handled++;
+ static_call(x86_pmu_drain_pebs)(regs, &data);
+
+ if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] &&
+ is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS]))
+ status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;
+ }
+
/*
* Intel PT
*/
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index d5441fca8d63..651f3709c260 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2270,6 +2270,114 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
format_group);
}
+static inline bool arch_pebs_record_continued(struct arch_pebs_header *header)
+{
+ /* Continue bit or null PEBS record indicates fragment follows. */
+ return header->cont || !(header->format & GENMASK_ULL(63, 16));
+}
+
+static void setup_arch_pebs_sample_data(struct perf_event *event,
+ struct pt_regs *iregs, void *__pebs,
+ struct perf_sample_data *data,
+ struct pt_regs *regs)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ u64 sample_type = event->attr.sample_type;
+ struct arch_pebs_header *header = NULL;
+ struct arch_pebs_aux *meminfo = NULL;
+ struct arch_pebs_gprs *gprs = NULL;
+ struct x86_perf_regs *perf_regs;
+ void *next_record;
+ void *at = __pebs;
+
+ if (at == NULL)
+ return;
+
+ perf_regs = container_of(regs, struct x86_perf_regs, regs);
+ perf_regs->xmm_regs = NULL;
+
+ __setup_perf_sample_data(event, iregs, data);
+
+ *regs = *iregs;
+
+again:
+ header = at;
+ next_record = at + sizeof(struct arch_pebs_header);
+ if (header->basic) {
+ struct arch_pebs_basic *basic = next_record;
+ u16 retire = 0;
+
+ next_record = basic + 1;
+
+ if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT)
+ retire = basic->valid ? basic->retire : 0;
+ __setup_pebs_basic_group(event, regs, data, sample_type,
+ basic->ip, basic->tsc, retire);
+ }
+
+ /*
+ * The record for MEMINFO is in front of GP
+ * But PERF_SAMPLE_TRANSACTION needs gprs->ax.
+ * Save the pointer here but process later.
+ */
+ if (header->aux) {
+ meminfo = next_record;
+ next_record = meminfo + 1;
+ }
+
+ if (header->gpr) {
+ gprs = next_record;
+ next_record = gprs + 1;
+
+ __setup_pebs_gpr_group(event, regs, (struct pebs_gprs *)gprs,
+ sample_type);
+ }
+
+ if (header->aux) {
+ u64 ax = gprs ? gprs->ax : 0;
+
+ __setup_pebs_meminfo_group(event, data, sample_type,
+ meminfo->cache_latency,
+ meminfo->instr_latency,
+ meminfo->address, meminfo->aux,
+ meminfo->tsx_tuning, ax);
+ }
+
+ if (header->xmm) {
+ struct pebs_xmm *xmm;
+
+ next_record += sizeof(struct arch_pebs_xer_header);
+
+ xmm = next_record;
+ perf_regs->xmm_regs = xmm->xmm;
+ next_record = xmm + 1;
+ }
+
+ if (header->lbr) {
+ struct arch_pebs_lbr_header *lbr_header = next_record;
+ struct lbr_entry *lbr;
+ int num_lbr;
+
+ next_record = lbr_header + 1;
+ lbr = next_record;
+
+ num_lbr = header->lbr == ARCH_PEBS_LBR_NUM_VAR ? lbr_header->depth :
+ header->lbr * ARCH_PEBS_BASE_LBR_ENTRIES;
+ next_record += num_lbr * sizeof(struct lbr_entry);
+
+ if (has_branch_stack(event)) {
+ intel_pmu_store_pebs_lbrs(lbr);
+ intel_pmu_lbr_save_brstack(data, cpuc, event);
+ }
+ }
+
+ /* Parse followed fragments if there are. */
+ if (arch_pebs_record_continued(header)) {
+ at = at + header->size;
+ goto again;
+ }
+}
+
static inline void *
get_next_pebs_record_by_bit(void *base, void *top, int bit)
{
@@ -2777,6 +2885,79 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
setup_pebs_adaptive_sample_data);
}
+static void intel_pmu_drain_arch_pebs(struct pt_regs *iregs,
+ struct perf_sample_data *data)
+{
+ struct perf_event *events[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {NULL};
+ short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
+ void *last[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS];
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ union arch_pebs_index index;
+ struct x86_perf_regs perf_regs;
+ struct pt_regs *regs = &perf_regs.regs;
+ void *base, *at, *top;
+ u64 mask;
+
+ rdmsrq(MSR_IA32_PEBS_INDEX, index.whole);
+
+ if (unlikely(!index.wr)) {
+ intel_pmu_pebs_event_update_no_drain(cpuc, X86_PMC_IDX_MAX);
+ return;
+ }
+
+ base = cpuc->ds_pebs_vaddr;
+ top = (void *)((u64)cpuc->ds_pebs_vaddr +
+ (index.wr << ARCH_PEBS_INDEX_WR_SHIFT));
+
+ index.wr = 0;
+ index.full = 0;
+ wrmsrq(MSR_IA32_PEBS_INDEX, index.whole);
+
+ mask = hybrid(cpuc->pmu, arch_pebs_cap).counters & cpuc->pebs_enabled;
+
+ if (!iregs)
+ iregs = &dummy_iregs;
+
+ /* Process all but the last event for each counter. */
+ for (at = base; at < top;) {
+ struct arch_pebs_header *header;
+ struct arch_pebs_basic *basic;
+ u64 pebs_status;
+
+ header = at;
+
+ if (WARN_ON_ONCE(!header->size))
+ break;
+
+ /* 1st fragment or single record must have basic group */
+ if (!header->basic) {
+ at += header->size;
+ continue;
+ }
+
+ basic = at + sizeof(struct arch_pebs_header);
+ pebs_status = mask & basic->applicable_counters;
+ __intel_pmu_handle_pebs_record(iregs, regs, data, at,
+ pebs_status, events, counts, last,
+ setup_arch_pebs_sample_data);
+
+ /* Skip non-last fragments */
+ while (arch_pebs_record_continued(header)) {
+ if (!header->size)
+ break;
+ at += header->size;
+ header = at;
+ }
+
+ /* Skip last fragment or the single record */
+ at += header->size;
+ }
+
+ __intel_pmu_handle_last_pebs_record(iregs, regs, data, mask, events,
+ counts, last,
+ setup_arch_pebs_sample_data);
+}
+
static void __init intel_arch_pebs_init(void)
{
/*
@@ -2786,6 +2967,7 @@ static void __init intel_arch_pebs_init(void)
*/
x86_pmu.arch_pebs = 1;
x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
+ x86_pmu.drain_pebs = intel_pmu_drain_arch_pebs;
x86_pmu.pebs_capable = ~0ULL;
x86_pmu.pebs_enable = __intel_pmu_pebs_enable;
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 9e1720d73244..fc7a4e7c718d 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -327,6 +327,12 @@
PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \
PERF_CAP_PEBS_TIMING_INFO)
+/* Arch PEBS */
+#define MSR_IA32_PEBS_BASE 0x000003f4
+#define MSR_IA32_PEBS_INDEX 0x000003f5
+#define ARCH_PEBS_OFFSET_MASK 0x7fffff
+#define ARCH_PEBS_INDEX_WR_SHIFT 4
+
#define MSR_IA32_RTIT_CTL 0x00000570
#define RTIT_CTL_TRACEEN BIT(0)
#define RTIT_CTL_CYCLEACC BIT(1)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 0dfa06722bab..3b3848f0d339 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -437,6 +437,8 @@ static inline bool is_topdown_idx(int idx)
#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT)
#define GLOBAL_STATUS_TRACE_TOPAPMI_BIT 55
#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT)
+#define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT 54
+#define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD BIT_ULL(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT)
#define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48
#define GLOBAL_CTRL_EN_PERF_METRICS BIT_ULL(48)
@@ -507,6 +509,100 @@ struct pebs_cntr_header {
#define INTEL_CNTR_METRICS 0x3
+/*
+ * Arch PEBS
+ */
+union arch_pebs_index {
+ struct {
+ u64 rsvd:4,
+ wr:23,
+ rsvd2:4,
+ full:1,
+ en:1,
+ rsvd3:3,
+ thresh:23,
+ rsvd4:5;
+ };
+ u64 whole;
+};
+
+struct arch_pebs_header {
+ union {
+ u64 format;
+ struct {
+ u64 size:16, /* Record size */
+ rsvd:14,
+ mode:1, /* 64BIT_MODE */
+ cont:1,
+ rsvd2:3,
+ cntr:5,
+ lbr:2,
+ rsvd3:7,
+ xmm:1,
+ ymmh:1,
+ rsvd4:2,
+ opmask:1,
+ zmmh:1,
+ h16zmm:1,
+ rsvd5:5,
+ gpr:1,
+ aux:1,
+ basic:1;
+ };
+ };
+ u64 rsvd6;
+};
+
+struct arch_pebs_basic {
+ u64 ip;
+ u64 applicable_counters;
+ u64 tsc;
+ u64 retire :16, /* Retire Latency */
+ valid :1,
+ rsvd :47;
+ u64 rsvd2;
+ u64 rsvd3;
+};
+
+struct arch_pebs_aux {
+ u64 address;
+ u64 rsvd;
+ u64 rsvd2;
+ u64 rsvd3;
+ u64 rsvd4;
+ u64 aux;
+ u64 instr_latency :16,
+ pad2 :16,
+ cache_latency :16,
+ pad3 :16;
+ u64 tsx_tuning;
+};
+
+struct arch_pebs_gprs {
+ u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di;
+ u64 r8, r9, r10, r11, r12, r13, r14, r15, ssp;
+ u64 rsvd;
+};
+
+struct arch_pebs_xer_header {
+ u64 xstate;
+ u64 rsvd;
+};
+
+#define ARCH_PEBS_LBR_NAN 0x0
+#define ARCH_PEBS_LBR_NUM_8 0x1
+#define ARCH_PEBS_LBR_NUM_16 0x2
+#define ARCH_PEBS_LBR_NUM_VAR 0x3
+#define ARCH_PEBS_BASE_LBR_ENTRIES 8
+struct arch_pebs_lbr_header {
+ u64 rsvd;
+ u64 ctl;
+ u64 depth;
+ u64 ler_from;
+ u64 ler_to;
+ u64 ler_info;
+};
+
/*
* AMD Extended Performance Monitoring and Debug cpuid feature detection
*/
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 1/2] arm64: mm: make linear mapping permission update more robust for patial range
From: Dev Jain @ 2025-10-15 6:46 UTC (permalink / raw)
To: Yang Shi, ryan.roberts, cl, catalin.marinas, will
Cc: linux-arm-kernel, linux-kernel
In-Reply-To: <20251013232803.3065100-2-yang@os.amperecomputing.com>
On 14/10/25 4:57 am, Yang Shi wrote:
> The commit fcf8dda8cc48 ("arm64: pageattr: Explicitly bail out when changing
> permissions for vmalloc_huge mappings") made permission update for
> partial range more robust. But the linear mapping permission update
> still assumes update the whole range by iterating from the first page
> all the way to the last page of the area.
>
> Make it more robust by updating the linear mapping permission from the
> page mapped by start address, and update the number of numpages.
>
> Fixes: fcf8dda8cc48 ("arm64: pageattr: Explicitly bail out when changing permissions for vmalloc_huge mappings")
> Signed-off-by: Yang Shi <yang@os.amperecomputing.com>
> ---
> arch/arm64/mm/pageattr.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c
> index 5135f2d66958..c21a2c319028 100644
> --- a/arch/arm64/mm/pageattr.c
> +++ b/arch/arm64/mm/pageattr.c
> @@ -148,7 +148,6 @@ static int change_memory_common(unsigned long addr, int numpages,
> unsigned long size = PAGE_SIZE * numpages;
> unsigned long end = start + size;
> struct vm_struct *area;
> - int i;
>
> if (!PAGE_ALIGNED(addr)) {
> start &= PAGE_MASK;
> @@ -184,8 +183,9 @@ static int change_memory_common(unsigned long addr, int numpages,
> */
> if (rodata_full && (pgprot_val(set_mask) == PTE_RDONLY ||
> pgprot_val(clear_mask) == PTE_RDONLY)) {
> - for (i = 0; i < area->nr_pages; i++) {
> - __change_memory_common((u64)page_address(area->pages[i]),
> + unsigned long idx = (start - (unsigned long)area->addr) >> PAGE_SHIFT;
> + for (int i = 0; i < numpages; i++) {
> + __change_memory_common((u64)page_address(area->pages[idx++]),
> PAGE_SIZE, set_mask, clear_mask);
Why not just use idx as the iterator in the for loop? Using i and then incrementing
idx is confusing.
As noted by Ryan, the fixes commit is wrong. The issues persists from commit c55191e.
After fixing these:
Reviewed-by: Dev Jain <dev.jain@arm.com>
> }
> }
^ permalink raw reply
* [Patch v8 07/12] perf/x86/intel/ds: Factor out PEBS group processing code to functions
From: Dapeng Mi @ 2025-10-15 6:44 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
In-Reply-To: <20251015064422.47437-1-dapeng1.mi@linux.intel.com>
Adaptive PEBS and arch-PEBS share lots of same code to process these
PEBS groups, like basic, GPR and meminfo groups. Extract these shared
code to generic functions to avoid duplicated code.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/ds.c | 170 +++++++++++++++++++++++--------------
1 file changed, 104 insertions(+), 66 deletions(-)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 41acbf0a11c9..d5441fca8d63 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2072,6 +2072,90 @@ static inline void __setup_pebs_counter_group(struct cpu_hw_events *cpuc,
#define PEBS_LATENCY_MASK 0xffff
+static inline void __setup_perf_sample_data(struct perf_event *event,
+ struct pt_regs *iregs,
+ struct perf_sample_data *data)
+{
+ perf_sample_data_init(data, 0, event->hw.last_period);
+
+ /*
+ * We must however always use iregs for the unwinder to stay sane; the
+ * record BP,SP,IP can point into thin air when the record is from a
+ * previous PMI context or an (I)RET happened between the record and
+ * PMI.
+ */
+ perf_sample_save_callchain(data, event, iregs);
+}
+
+static inline void __setup_pebs_basic_group(struct perf_event *event,
+ struct pt_regs *regs,
+ struct perf_sample_data *data,
+ u64 sample_type, u64 ip,
+ u64 tsc, u16 retire)
+{
+ /* The ip in basic is EventingIP */
+ set_linear_ip(regs, ip);
+ regs->flags = PERF_EFLAGS_EXACT;
+ setup_pebs_time(event, data, tsc);
+
+ if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT)
+ data->weight.var3_w = retire;
+}
+
+static inline void __setup_pebs_gpr_group(struct perf_event *event,
+ struct pt_regs *regs,
+ struct pebs_gprs *gprs,
+ u64 sample_type)
+{
+ if (event->attr.precise_ip < 2) {
+ set_linear_ip(regs, gprs->ip);
+ regs->flags &= ~PERF_EFLAGS_EXACT;
+ }
+
+ if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER))
+ adaptive_pebs_save_regs(regs, gprs);
+}
+
+static inline void __setup_pebs_meminfo_group(struct perf_event *event,
+ struct perf_sample_data *data,
+ u64 sample_type, u64 latency,
+ u16 instr_latency, u64 address,
+ u64 aux, u64 tsx_tuning, u64 ax)
+{
+ if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
+ u64 tsx_latency = intel_get_tsx_weight(tsx_tuning);
+
+ data->weight.var2_w = instr_latency;
+
+ /*
+ * Although meminfo::latency is defined as a u64,
+ * only the lower 32 bits include the valid data
+ * in practice on Ice Lake and earlier platforms.
+ */
+ if (sample_type & PERF_SAMPLE_WEIGHT)
+ data->weight.full = latency ?: tsx_latency;
+ else
+ data->weight.var1_dw = (u32)latency ?: tsx_latency;
+
+ data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
+ }
+
+ if (sample_type & PERF_SAMPLE_DATA_SRC) {
+ data->data_src.val = get_data_src(event, aux);
+ data->sample_flags |= PERF_SAMPLE_DATA_SRC;
+ }
+
+ if (sample_type & PERF_SAMPLE_ADDR_TYPE) {
+ data->addr = address;
+ data->sample_flags |= PERF_SAMPLE_ADDR;
+ }
+
+ if (sample_type & PERF_SAMPLE_TRANSACTION) {
+ data->txn = intel_get_tsx_transaction(tsx_tuning, ax);
+ data->sample_flags |= PERF_SAMPLE_TRANSACTION;
+ }
+}
+
/*
* With adaptive PEBS the layout depends on what fields are configured.
*/
@@ -2081,12 +2165,14 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
struct pt_regs *regs)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ u64 sample_type = event->attr.sample_type;
struct pebs_basic *basic = __pebs;
void *next_record = basic + 1;
- u64 sample_type, format_group;
struct pebs_meminfo *meminfo = NULL;
struct pebs_gprs *gprs = NULL;
struct x86_perf_regs *perf_regs;
+ u64 format_group;
+ u16 retire;
if (basic == NULL)
return;
@@ -2094,31 +2180,17 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
perf_regs = container_of(regs, struct x86_perf_regs, regs);
perf_regs->xmm_regs = NULL;
- sample_type = event->attr.sample_type;
format_group = basic->format_group;
- perf_sample_data_init(data, 0, event->hw.last_period);
- setup_pebs_time(event, data, basic->tsc);
-
- /*
- * We must however always use iregs for the unwinder to stay sane; the
- * record BP,SP,IP can point into thin air when the record is from a
- * previous PMI context or an (I)RET happened between the record and
- * PMI.
- */
- perf_sample_save_callchain(data, event, iregs);
+ __setup_perf_sample_data(event, iregs, data);
*regs = *iregs;
- /* The ip in basic is EventingIP */
- set_linear_ip(regs, basic->ip);
- regs->flags = PERF_EFLAGS_EXACT;
- if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) {
- if (x86_pmu.flags & PMU_FL_RETIRE_LATENCY)
- data->weight.var3_w = basic->retire_latency;
- else
- data->weight.var3_w = 0;
- }
+ /* basic group */
+ retire = x86_pmu.flags & PMU_FL_RETIRE_LATENCY ?
+ basic->retire_latency : 0;
+ __setup_pebs_basic_group(event, regs, data, sample_type,
+ basic->ip, basic->tsc, retire);
/*
* The record for MEMINFO is in front of GP
@@ -2134,54 +2206,20 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
gprs = next_record;
next_record = gprs + 1;
- if (event->attr.precise_ip < 2) {
- set_linear_ip(regs, gprs->ip);
- regs->flags &= ~PERF_EFLAGS_EXACT;
- }
-
- if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER))
- adaptive_pebs_save_regs(regs, gprs);
+ __setup_pebs_gpr_group(event, regs, gprs, sample_type);
}
if (format_group & PEBS_DATACFG_MEMINFO) {
- if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
- u64 latency = x86_pmu.flags & PMU_FL_INSTR_LATENCY ?
- meminfo->cache_latency : meminfo->mem_latency;
-
- if (x86_pmu.flags & PMU_FL_INSTR_LATENCY)
- data->weight.var2_w = meminfo->instr_latency;
-
- /*
- * Although meminfo::latency is defined as a u64,
- * only the lower 32 bits include the valid data
- * in practice on Ice Lake and earlier platforms.
- */
- if (sample_type & PERF_SAMPLE_WEIGHT) {
- data->weight.full = latency ?:
- intel_get_tsx_weight(meminfo->tsx_tuning);
- } else {
- data->weight.var1_dw = (u32)latency ?:
- intel_get_tsx_weight(meminfo->tsx_tuning);
- }
-
- data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
- }
-
- if (sample_type & PERF_SAMPLE_DATA_SRC) {
- data->data_src.val = get_data_src(event, meminfo->aux);
- data->sample_flags |= PERF_SAMPLE_DATA_SRC;
- }
-
- if (sample_type & PERF_SAMPLE_ADDR_TYPE) {
- data->addr = meminfo->address;
- data->sample_flags |= PERF_SAMPLE_ADDR;
- }
-
- if (sample_type & PERF_SAMPLE_TRANSACTION) {
- data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning,
- gprs ? gprs->ax : 0);
- data->sample_flags |= PERF_SAMPLE_TRANSACTION;
- }
+ u64 latency = x86_pmu.flags & PMU_FL_INSTR_LATENCY ?
+ meminfo->cache_latency : meminfo->mem_latency;
+ u64 instr_latency = x86_pmu.flags & PMU_FL_INSTR_LATENCY ?
+ meminfo->instr_latency : 0;
+ u64 ax = gprs ? gprs->ax : 0;
+
+ __setup_pebs_meminfo_group(event, data, sample_type, latency,
+ instr_latency, meminfo->address,
+ meminfo->aux, meminfo->tsx_tuning,
+ ax);
}
if (format_group & PEBS_DATACFG_XMMS) {
--
2.34.1
^ permalink raw reply related
* [Patch v8 06/12] perf/x86/intel/ds: Factor out PEBS record processing code to functions
From: Dapeng Mi @ 2025-10-15 6:44 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi, Kan Liang
In-Reply-To: <20251015064422.47437-1-dapeng1.mi@linux.intel.com>
Beside some PEBS record layout difference, arch-PEBS can share most of
PEBS record processing code with adaptive PEBS. Thus, factor out these
common processing code to independent inline functions, so they can be
reused by subsequent arch-PEBS handler.
Suggested-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/ds.c | 101 ++++++++++++++++++++++++-------------
1 file changed, 66 insertions(+), 35 deletions(-)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index a80881a20321..41acbf0a11c9 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2629,6 +2629,64 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
}
}
+static inline void __intel_pmu_handle_pebs_record(struct pt_regs *iregs,
+ struct pt_regs *regs,
+ struct perf_sample_data *data,
+ void *at, u64 pebs_status,
+ struct perf_event *events[],
+ short *counts, void **last,
+ setup_fn setup_sample)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ struct perf_event *event;
+ int bit;
+
+ for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) {
+ event = cpuc->events[bit];
+
+ if (WARN_ON_ONCE(!event) ||
+ WARN_ON_ONCE(!event->attr.precise_ip))
+ continue;
+
+ if (counts[bit]++)
+ __intel_pmu_pebs_event(event, iregs, regs, data,
+ last[bit], setup_sample);
+
+ last[bit] = at;
+ /*
+ * perf_event_overflow() called by below __intel_pmu_pebs_last_event()
+ * could trigger interrupt throttle and clear all event pointers of
+ * the group in cpuc->events[] to NULL. So snapshot the event[] before
+ * it could be cleared. This avoids the possible NULL event pointer
+ * access and PEBS record loss.
+ */
+ if (counts[bit] && !events[bit])
+ events[bit] = cpuc->events[bit];
+ }
+}
+
+static inline void
+__intel_pmu_handle_last_pebs_record(struct pt_regs *iregs, struct pt_regs *regs,
+ struct perf_sample_data *data, u64 mask,
+ struct perf_event *events[],
+ short *counts, void **last,
+ setup_fn setup_sample)
+{
+ struct perf_event *event;
+ int bit;
+
+ for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) {
+ if (!counts[bit])
+ continue;
+
+ event = events[bit];
+
+ __intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit],
+ counts[bit], setup_sample);
+ }
+
+}
+
static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
{
struct perf_event *events[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {NULL};
@@ -2639,9 +2697,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
struct x86_perf_regs perf_regs;
struct pt_regs *regs = &perf_regs.regs;
struct pebs_basic *basic;
- struct perf_event *event;
void *base, *at, *top;
- int bit;
u64 mask;
if (!x86_pmu.pebs_active)
@@ -2654,6 +2710,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
mask = hybrid(cpuc->pmu, pebs_events_mask) |
(hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED);
+ mask &= cpuc->pebs_enabled;
if (unlikely(base >= top)) {
intel_pmu_pebs_event_update_no_drain(cpuc, mask);
@@ -2671,41 +2728,15 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
if (basic->format_size != cpuc->pebs_record_size)
continue;
- pebs_status = basic->applicable_counters & cpuc->pebs_enabled & mask;
- for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) {
- event = cpuc->events[bit];
-
- if (WARN_ON_ONCE(!event) ||
- WARN_ON_ONCE(!event->attr.precise_ip))
- continue;
-
- if (counts[bit]++) {
- __intel_pmu_pebs_event(event, iregs, regs, data, last[bit],
- setup_pebs_adaptive_sample_data);
- }
- last[bit] = at;
-
- /*
- * perf_event_overflow() called by below __intel_pmu_pebs_last_event()
- * could trigger interrupt throttle and clear all event pointers of
- * the group in cpuc->events[] to NULL. So snapshot the event[] before
- * it could be cleared. This avoids the possible NULL event pointer
- * access and PEBS record loss.
- */
- if (counts[bit] && !events[bit])
- events[bit] = cpuc->events[bit];
- }
+ pebs_status = mask & basic->applicable_counters;
+ __intel_pmu_handle_pebs_record(iregs, regs, data, at,
+ pebs_status, events, counts, last,
+ setup_pebs_adaptive_sample_data);
}
- for_each_set_bit(bit, (unsigned long *)&mask, X86_PMC_IDX_MAX) {
- if (!counts[bit])
- continue;
-
- event = events[bit];
-
- __intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit],
- counts[bit], setup_pebs_adaptive_sample_data);
- }
+ __intel_pmu_handle_last_pebs_record(iregs, regs, data, mask, events,
+ counts, last,
+ setup_pebs_adaptive_sample_data);
}
static void __init intel_arch_pebs_init(void)
--
2.34.1
^ permalink raw reply related
* [Patch v8 05/12] perf/x86/intel: Initialize architectural PEBS
From: Dapeng Mi @ 2025-10-15 6:44 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
In-Reply-To: <20251015064422.47437-1-dapeng1.mi@linux.intel.com>
arch-PEBS leverages CPUID.23H.4/5 sub-leaves enumerate arch-PEBS
supported capabilities and counters bitmap. This patch parses these 2
sub-leaves and initializes arch-PEBS capabilities and corresponding
structures.
Since IA32_PEBS_ENABLE and MSR_PEBS_DATA_CFG MSRs are no longer existed
for arch-PEBS, arch-PEBS doesn't need to manipulate these MSRs. Thus add
a simple pair of __intel_pmu_pebs_enable/disable() callbacks for
arch-PEBS.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/core.c | 21 +++++++++---
arch/x86/events/intel/core.c | 55 +++++++++++++++++++++++--------
arch/x86/events/intel/ds.c | 52 ++++++++++++++++++++++++-----
arch/x86/events/perf_event.h | 25 ++++++++++++--
arch/x86/include/asm/perf_event.h | 7 +++-
5 files changed, 129 insertions(+), 31 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 745caa6c15a3..8c25ad2bf179 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -554,14 +554,22 @@ static inline int precise_br_compat(struct perf_event *event)
return m == b;
}
-int x86_pmu_max_precise(void)
+int x86_pmu_max_precise(struct pmu *pmu)
{
int precise = 0;
- /* Support for constant skid */
if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
- precise++;
+ /* arch PEBS */
+ if (x86_pmu.arch_pebs) {
+ precise = 2;
+ if (hybrid(pmu, arch_pebs_cap).pdists)
+ precise++;
+
+ return precise;
+ }
+ /* legacy PEBS - support for constant skid */
+ precise++;
/* Support for IP fixup */
if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
precise++;
@@ -569,13 +577,14 @@ int x86_pmu_max_precise(void)
if (x86_pmu.pebs_prec_dist)
precise++;
}
+
return precise;
}
int x86_pmu_hw_config(struct perf_event *event)
{
if (event->attr.precise_ip) {
- int precise = x86_pmu_max_precise();
+ int precise = x86_pmu_max_precise(event->pmu);
if (event->attr.precise_ip > precise)
return -EOPNOTSUPP;
@@ -2629,7 +2638,9 @@ static ssize_t max_precise_show(struct device *cdev,
struct device_attribute *attr,
char *buf)
{
- return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
+ struct pmu *pmu = dev_get_drvdata(cdev);
+
+ return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise(pmu));
}
static DEVICE_ATTR_RO(max_precise);
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index c88bcd5d2bc4..bfb123ff7c9a 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5273,34 +5273,58 @@ static inline bool intel_pmu_broken_perf_cap(void)
static void update_pmu_cap(struct pmu *pmu)
{
- unsigned int cntr, fixed_cntr, ecx, edx;
- union cpuid35_eax eax;
- union cpuid35_ebx ebx;
+ unsigned int eax, ebx, ecx, edx;
+ union cpuid35_eax eax_0;
+ union cpuid35_ebx ebx_0;
+ u64 cntrs_mask = 0;
+ u64 pebs_mask = 0;
+ u64 pdists_mask = 0;
- cpuid(ARCH_PERFMON_EXT_LEAF, &eax.full, &ebx.full, &ecx, &edx);
+ cpuid(ARCH_PERFMON_EXT_LEAF, &eax_0.full, &ebx_0.full, &ecx, &edx);
- if (ebx.split.umask2)
+ if (ebx_0.split.umask2)
hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2;
- if (ebx.split.eq)
+ if (ebx_0.split.eq)
hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ;
- if (eax.split.cntr_subleaf) {
+ if (eax_0.split.cntr_subleaf) {
cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
- &cntr, &fixed_cntr, &ecx, &edx);
- hybrid(pmu, cntr_mask64) = cntr;
- hybrid(pmu, fixed_cntr_mask64) = fixed_cntr;
+ &eax, &ebx, &ecx, &edx);
+ hybrid(pmu, cntr_mask64) = eax;
+ hybrid(pmu, fixed_cntr_mask64) = ebx;
+ cntrs_mask = (u64)ebx << INTEL_PMC_IDX_FIXED | eax;
}
- if (eax.split.acr_subleaf) {
+ if (eax_0.split.acr_subleaf) {
cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_ACR_LEAF,
- &cntr, &fixed_cntr, &ecx, &edx);
+ &eax, &ebx, &ecx, &edx);
/* The mask of the counters which can be reloaded */
- hybrid(pmu, acr_cntr_mask64) = cntr | ((u64)fixed_cntr << INTEL_PMC_IDX_FIXED);
+ hybrid(pmu, acr_cntr_mask64) = eax | ((u64)ebx << INTEL_PMC_IDX_FIXED);
/* The mask of the counters which can cause a reload of reloadable counters */
hybrid(pmu, acr_cause_mask64) = ecx | ((u64)edx << INTEL_PMC_IDX_FIXED);
}
+ /* Bits[5:4] should be set simultaneously if arch-PEBS is supported */
+ if (eax_0.split.pebs_caps_subleaf && eax_0.split.pebs_cnts_subleaf) {
+ cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_CAP_LEAF,
+ &eax, &ebx, &ecx, &edx);
+ hybrid(pmu, arch_pebs_cap).caps = (u64)ebx << 32;
+
+ cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_COUNTER_LEAF,
+ &eax, &ebx, &ecx, &edx);
+ pebs_mask = ((u64)ecx << INTEL_PMC_IDX_FIXED) | eax;
+ pdists_mask = ((u64)edx << INTEL_PMC_IDX_FIXED) | ebx;
+ hybrid(pmu, arch_pebs_cap).counters = pebs_mask;
+ hybrid(pmu, arch_pebs_cap).pdists = pdists_mask;
+
+ if (WARN_ON((pebs_mask | pdists_mask) & ~cntrs_mask))
+ x86_pmu.arch_pebs = 0;
+ } else {
+ WARN_ON(x86_pmu.arch_pebs == 1);
+ x86_pmu.arch_pebs = 0;
+ }
+
if (!intel_pmu_broken_perf_cap()) {
/* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration */
rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities);
@@ -6252,7 +6276,7 @@ tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
static umode_t
pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
{
- return x86_pmu.ds_pebs ? attr->mode : 0;
+ return intel_pmu_has_pebs() ? attr->mode : 0;
}
static umode_t
@@ -7728,6 +7752,9 @@ __init int intel_pmu_init(void)
if (!is_hybrid() && boot_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
update_pmu_cap(NULL);
+ if (x86_pmu.arch_pebs)
+ pr_cont("Architectural PEBS, ");
+
intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64,
&x86_pmu.fixed_cntr_mask64,
&x86_pmu.intel_ctrl);
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 259a0ff807eb..a80881a20321 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1531,6 +1531,15 @@ static inline void intel_pmu_drain_large_pebs(struct cpu_hw_events *cpuc)
intel_pmu_drain_pebs_buffer();
}
+static void __intel_pmu_pebs_enable(struct perf_event *event)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+
+ hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
+ cpuc->pebs_enabled |= 1ULL << hwc->idx;
+}
+
void intel_pmu_pebs_enable(struct perf_event *event)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
@@ -1539,9 +1548,7 @@ void intel_pmu_pebs_enable(struct perf_event *event)
struct debug_store *ds = cpuc->ds;
unsigned int idx = hwc->idx;
- hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
-
- cpuc->pebs_enabled |= 1ULL << hwc->idx;
+ __intel_pmu_pebs_enable(event);
if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5))
cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
@@ -1603,14 +1610,22 @@ void intel_pmu_pebs_del(struct perf_event *event)
pebs_update_state(needed_cb, cpuc, event, false);
}
-void intel_pmu_pebs_disable(struct perf_event *event)
+static void __intel_pmu_pebs_disable(struct perf_event *event)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
struct hw_perf_event *hwc = &event->hw;
intel_pmu_drain_large_pebs(cpuc);
-
cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
+ hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
+}
+
+void intel_pmu_pebs_disable(struct perf_event *event)
+{
+ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+
+ __intel_pmu_pebs_disable(event);
if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) &&
(x86_pmu.version < 5))
@@ -1622,8 +1637,6 @@ void intel_pmu_pebs_disable(struct perf_event *event)
if (cpuc->enabled)
wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
-
- hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
}
void intel_pmu_pebs_enable_all(void)
@@ -2695,11 +2708,26 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
}
}
+static void __init intel_arch_pebs_init(void)
+{
+ /*
+ * Current hybrid platforms always both support arch-PEBS or not
+ * on all kinds of cores. So directly set x86_pmu.arch_pebs flag
+ * if boot cpu supports arch-PEBS.
+ */
+ x86_pmu.arch_pebs = 1;
+ x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
+ x86_pmu.pebs_capable = ~0ULL;
+
+ x86_pmu.pebs_enable = __intel_pmu_pebs_enable;
+ x86_pmu.pebs_disable = __intel_pmu_pebs_disable;
+}
+
/*
* PEBS probe and setup
*/
-void __init intel_pebs_init(void)
+static void __init intel_ds_pebs_init(void)
{
/*
* No support for 32bit formats
@@ -2814,6 +2842,14 @@ void __init intel_pebs_init(void)
}
}
+void __init intel_pebs_init(void)
+{
+ if (x86_pmu.intel_cap.pebs_format == 0xf)
+ intel_arch_pebs_init();
+ else
+ intel_ds_pebs_init();
+}
+
void perf_restore_debug_store(void)
{
struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 285779c73479..ca5289980b52 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -708,6 +708,12 @@ enum hybrid_pmu_type {
hybrid_big_small_tiny = hybrid_big | hybrid_small_tiny,
};
+struct arch_pebs_cap {
+ u64 caps;
+ u64 counters;
+ u64 pdists;
+};
+
struct x86_hybrid_pmu {
struct pmu pmu;
const char *name;
@@ -752,6 +758,8 @@ struct x86_hybrid_pmu {
mid_ack :1,
enabled_ack :1;
+ struct arch_pebs_cap arch_pebs_cap;
+
u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX];
};
@@ -906,7 +914,7 @@ struct x86_pmu {
union perf_capabilities intel_cap;
/*
- * Intel DebugStore bits
+ * Intel DebugStore and PEBS bits
*/
unsigned int bts :1,
bts_active :1,
@@ -917,7 +925,8 @@ struct x86_pmu {
pebs_no_tlb :1,
pebs_no_isolation :1,
pebs_block :1,
- pebs_ept :1;
+ pebs_ept :1,
+ arch_pebs :1;
int pebs_record_size;
int pebs_buffer_size;
u64 pebs_events_mask;
@@ -929,6 +938,11 @@ struct x86_pmu {
u64 rtm_abort_event;
u64 pebs_capable;
+ /*
+ * Intel Architectural PEBS
+ */
+ struct arch_pebs_cap arch_pebs_cap;
+
/*
* Intel LBR
*/
@@ -1216,7 +1230,7 @@ int x86_reserve_hardware(void);
void x86_release_hardware(void);
-int x86_pmu_max_precise(void);
+int x86_pmu_max_precise(struct pmu *pmu);
void hw_perf_lbr_event_destroy(struct perf_event *event);
@@ -1791,6 +1805,11 @@ static inline int intel_pmu_max_num_pebs(struct pmu *pmu)
return fls((u32)hybrid(pmu, pebs_events_mask));
}
+static inline bool intel_pmu_has_pebs(void)
+{
+ return x86_pmu.ds_pebs || x86_pmu.arch_pebs;
+}
+
#else /* CONFIG_CPU_SUP_INTEL */
static inline void reserve_ds_buffers(void)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 49a4d442f3fc..0dfa06722bab 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -200,6 +200,8 @@ union cpuid10_edx {
#define ARCH_PERFMON_EXT_LEAF 0x00000023
#define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1
#define ARCH_PERFMON_ACR_LEAF 0x2
+#define ARCH_PERFMON_PEBS_CAP_LEAF 0x4
+#define ARCH_PERFMON_PEBS_COUNTER_LEAF 0x5
union cpuid35_eax {
struct {
@@ -210,7 +212,10 @@ union cpuid35_eax {
unsigned int acr_subleaf:1;
/* Events Sub-Leaf */
unsigned int events_subleaf:1;
- unsigned int reserved:28;
+ /* arch-PEBS Sub-Leaves */
+ unsigned int pebs_caps_subleaf:1;
+ unsigned int pebs_cnts_subleaf:1;
+ unsigned int reserved:26;
} split;
unsigned int full;
};
--
2.34.1
^ permalink raw reply related
* [Patch v8 04/12] perf/x86/intel: Correct large PEBS flag check
From: Dapeng Mi @ 2025-10-15 6:44 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
In-Reply-To: <20251015064422.47437-1-dapeng1.mi@linux.intel.com>
current large PEBS flag check only checks if sample_regs_user contains
unsupported GPRs but doesn't check if sample_regs_intr contains
unsupported GPRs.
Of course, currently PEBS HW supports to sample all perf supported GPRs,
the missed check doesn't cause real issue. But it won't be true any more
after the subsequent patches support to sample SSP register. SSP
sampling is not supported by adaptive PEBS HW and it would be supported
until arch-PEBS HW. So correct this issue.
Fixes: a47ba4d77e12 ("perf/x86: Enable free running PEBS for REGS_USER/INTR")
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 46a000eb0bb3..c88bcd5d2bc4 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4029,7 +4029,9 @@ static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
if (!event->attr.exclude_kernel)
flags &= ~PERF_SAMPLE_REGS_USER;
if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
- flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
+ flags &= ~PERF_SAMPLE_REGS_USER;
+ if (event->attr.sample_regs_intr & ~PEBS_GP_REGS)
+ flags &= ~PERF_SAMPLE_REGS_INTR;
return flags;
}
--
2.34.1
^ permalink raw reply related
* [Patch v8 03/12] perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call
From: Dapeng Mi @ 2025-10-15 6:44 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
In-Reply-To: <20251015064422.47437-1-dapeng1.mi@linux.intel.com>
Use x86_pmu_drain_pebs static call to replace calling x86_pmu.drain_pebs
function pointer.
Suggested-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 28f5468a6ea3..46a000eb0bb3 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3269,7 +3269,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
* The PEBS buffer has to be drained before handling the A-PMI
*/
if (is_pebs_counter_event_group(event))
- x86_pmu.drain_pebs(regs, &data);
+ static_call(x86_pmu_drain_pebs)(regs, &data);
last_period = event->hw.last_period;
--
2.34.1
^ permalink raw reply related
* [Patch v8 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss
From: Dapeng Mi @ 2025-10-15 6:44 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi,
kernel test robot, Kan Liang
In-Reply-To: <20251015064422.47437-1-dapeng1.mi@linux.intel.com>
When intel_pmu_drain_pebs_icl() is called to drain PEBS records, the
perf_event_overflow() could be called to process the last PEBS record.
While perf_event_overflow() could trigger the interrupt throttle and
stop all events of the group, like what the below call-chain shows.
perf_event_overflow()
-> __perf_event_overflow()
->__perf_event_account_interrupt()
-> perf_event_throttle_group()
-> perf_event_throttle()
-> event->pmu->stop()
-> x86_pmu_stop()
The side effect of stopping the events is that all corresponding event
pointers in cpuc->events[] array are cleared to NULL.
Assume there are two PEBS events (event a and event b) in a group. When
intel_pmu_drain_pebs_icl() calls perf_event_overflow() to process the
last PEBS record of PEBS event a, interrupt throttle is triggered and
all pointers of event a and event b are cleared to NULL. Then
intel_pmu_drain_pebs_icl() tries to process the last PEBS record of
event b and encounters NULL pointer access.
To avoid this NULL event access and potential PEBS record loss, snapshot
cpuc->events[] into a local events[] before drian_pebs() helper calling
perf_event_overflow() and then use the local events[] to process the
left PEBS records.
Besides intel_pmu_drain_pebs_nhm() has similar issue and fix it as well.
Reported-by: kernel test robot <oliver.sang@intel.com>
Closes: https://lore.kernel.org/oe-lkp/202507042103.a15d2923-lkp@intel.com
Fixes: 9734e25fbf5a ("perf: Fix the throttle logic for a group")
Suggested-by: Kan Liang <kan.liang@linux.intel.com>
Tested-by: kernel test robot <oliver.sang@intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/intel/ds.c | 36 +++++++++++++++++++++++++++++++-----
1 file changed, 31 insertions(+), 5 deletions(-)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index c0b7ac1c7594..259a0ff807eb 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2487,6 +2487,7 @@ static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, u64
static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_data *data)
{
+ struct perf_event *events[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {NULL};
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
struct debug_store *ds = cpuc->ds;
struct perf_event *event;
@@ -2526,9 +2527,11 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
/* PEBS v3 has more accurate status bits */
if (x86_pmu.intel_cap.pebs_format >= 3) {
- for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
+ for_each_set_bit(bit, (unsigned long *)&pebs_status, size) {
counts[bit]++;
-
+ if (counts[bit] && !events[bit])
+ events[bit] = cpuc->events[bit];
+ }
continue;
}
@@ -2566,19 +2569,31 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
* If collision happened, the record will be dropped.
*/
if (pebs_status != (1ULL << bit)) {
- for_each_set_bit(i, (unsigned long *)&pebs_status, size)
+ for_each_set_bit(i, (unsigned long *)&pebs_status, size) {
error[i]++;
+ if (error[i] && !events[i])
+ events[i] = cpuc->events[i];
+ }
continue;
}
counts[bit]++;
+ /*
+ * perf_event_overflow() called by below __intel_pmu_pebs_events()
+ * could trigger interrupt throttle and clear all event pointers of
+ * the group in cpuc->events[] to NULL. So snapshot the event[] before
+ * it could be cleared. This avoids the possible NULL event pointer
+ * access and PEBS record loss.
+ */
+ if (counts[bit] && !events[bit])
+ events[bit] = cpuc->events[bit];
}
for_each_set_bit(bit, (unsigned long *)&mask, size) {
if ((counts[bit] == 0) && (error[bit] == 0))
continue;
- event = cpuc->events[bit];
+ event = events[bit];
if (WARN_ON_ONCE(!event))
continue;
@@ -2603,6 +2618,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d
static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
{
+ struct perf_event *events[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {NULL};
short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
void *last[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS];
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
@@ -2655,6 +2671,16 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
setup_pebs_adaptive_sample_data);
}
last[bit] = at;
+
+ /*
+ * perf_event_overflow() called by below __intel_pmu_pebs_last_event()
+ * could trigger interrupt throttle and clear all event pointers of
+ * the group in cpuc->events[] to NULL. So snapshot the event[] before
+ * it could be cleared. This avoids the possible NULL event pointer
+ * access and PEBS record loss.
+ */
+ if (counts[bit] && !events[bit])
+ events[bit] = cpuc->events[bit];
}
}
@@ -2662,7 +2688,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
if (!counts[bit])
continue;
- event = cpuc->events[bit];
+ event = events[bit];
__intel_pmu_pebs_last_event(event, iregs, regs, data, last[bit],
counts[bit], setup_pebs_adaptive_sample_data);
--
2.34.1
^ permalink raw reply related
* [Patch v8 01/12] perf/x86: Remove redundant is_x86_event() prototype
From: Dapeng Mi @ 2025-10-15 6:44 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
In-Reply-To: <20251015064422.47437-1-dapeng1.mi@linux.intel.com>
2 is_x86_event() prototypes are defined in perf_event.h. Remove the
redundant one.
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
---
arch/x86/events/perf_event.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 2b969386dcdd..285779c73479 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1124,7 +1124,6 @@ static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\
.pmu_type = _pmu, \
}
-int is_x86_event(struct perf_event *event);
struct pmu *x86_get_pmu(unsigned int cpu);
extern struct x86_pmu x86_pmu __read_mostly;
--
2.34.1
^ permalink raw reply related
* [Patch v8 00/12] arch-PEBS enabling for Intel platforms
From: Dapeng Mi @ 2025-10-15 6:44 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Namhyung Kim, Ian Rogers, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Eranian Stephane
Cc: linux-kernel, linux-perf-users, Dapeng Mi, Dapeng Mi
Changes:
v7 -> v8:
* Fix the warning reported by Kernel test robot (Patch 02/12)
* Rebase code to 6.18-rc1.
v6 -> v7:
* Rebase code to last tip perf/core tree.
* Opportunistically remove the redundant is_x86_event() prototype.
(Patch 01/12)
* Fix PEBS handler NULL event access and record loss issue.
(Patch 02/12)
* Reset MSR_IA32_PEBS_INDEX at the head of_drain_arch_pebs() instead
of end. It avoids the processed PEBS records are processed again in
some corner cases like event throttling. (Patch 08/12)
v5 -> v6:
* Rebase code to last tip perf/core tree + "x86 perf bug fixes and
optimization" patchset
v4 -> v5:
* Rebase code to 6.16-rc3
* Allocate/free arch-PEBS buffer in callbacks *prepare_cpu/*dead_cpu
(patch 07/10, Peter)
* Code and comments refine (patch 09/10, Peter)
This patchset introduces architectural PEBS support for Intel platforms
like Clearwater Forest (CWF) and Panther Lake (PTL). The detailed
information about arch-PEBS can be found in chapter 11
"architectural PEBS" of "Intel Architecture Instruction Set Extensions
and Future Features".
This patch set doesn't include the SSP and SIMD regs (OPMASK/YMM/ZMM)
sampling support for arch-PEBS to avoid the dependency for the basic
SIMD regs sampling support patch series[1]. Once the basic SIMD regs
sampling is supported, the arch-PEBS based SSP and SIMD regs
(OPMASK/YMM/ZMM) sampling would be supported in a later patch set.
Tests:
Run below tests on Clearwater Forest and Pantherlake, no issue is
found.
1. Basic perf counting case.
perf stat -e '{branches,branches,branches,branches,branches,branches,branches,branches,cycles,instructions,ref-cycles}' sleep 1
2. Basic PMI based perf sampling case.
perf record -e '{branches,branches,branches,branches,branches,branches,branches,branches,cycles,instructions,ref-cycles}' sleep 1
3. Basic PEBS based perf sampling case.
perf record -e '{branches,branches,branches,branches,branches,branches,branches,branches,cycles,instructions,ref-cycles}:p' sleep 1
4. PEBS sampling case with basic, GPRs, vector-registers and LBR groups
perf record -e branches:p -Iax,bx,ip,xmm0 -b -c 10000 sleep 1
5. User space PEBS sampling case with basic, GPRs and LBR groups
perf record -e branches:p --user-regs=ax,bx,ip -b -c 10000 sleep 1
6. PEBS sampling case with auxiliary (memory info) group
perf mem record sleep 1
7. PEBS sampling case with counter group
perf record -e '{branches:p,branches,cycles}:S' -c 10000 sleep 1
8. Perf stat and record test
perf test 100; perf test 131
History:
v7: https://lore.kernel.org/all/20250828013435.1528459-1-dapeng1.mi@linux.intel.com/
v6: https://lore.kernel.org/all/20250821035805.159494-1-dapeng1.mi@linux.intel.com/
v5: https://lore.kernel.org/all/20250623223546.112465-1-dapeng1.mi@linux.intel.com/
v4: https://lore.kernel.org/all/20250620103909.1586595-1-dapeng1.mi@linux.intel.com/
v3: https://lore.kernel.org/all/20250415114428.341182-1-dapeng1.mi@linux.intel.com/
v2: https://lore.kernel.org/all/20250218152818.158614-1-dapeng1.mi@linux.intel.com/
v1: https://lore.kernel.org/all/20250123140721.2496639-1-dapeng1.mi@linux.intel.com/
Ref:
[1]: https://lore.kernel.org/all/20250925061213.178796-1-dapeng1.mi@linux.intel.com/
Dapeng Mi (12):
perf/x86: Remove redundant is_x86_event() prototype
perf/x86/intel: Fix NULL event access and potential PEBS record loss
perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call
perf/x86/intel: Correct large PEBS flag check
perf/x86/intel: Initialize architectural PEBS
perf/x86/intel/ds: Factor out PEBS record processing code to functions
perf/x86/intel/ds: Factor out PEBS group processing code to functions
perf/x86/intel: Process arch-PEBS records or record fragments
perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR
perf/x86/intel: Update dyn_constranit base on PEBS event precise level
perf/x86/intel: Setup PEBS data configuration and enable legacy groups
perf/x86/intel: Add counter group support for arch-PEBS
arch/x86/events/core.c | 21 +-
arch/x86/events/intel/core.c | 268 ++++++++++++-
arch/x86/events/intel/ds.c | 632 ++++++++++++++++++++++++------
arch/x86/events/perf_event.h | 41 +-
arch/x86/include/asm/intel_ds.h | 10 +-
arch/x86/include/asm/msr-index.h | 20 +
arch/x86/include/asm/perf_event.h | 116 +++++-
7 files changed, 963 insertions(+), 145 deletions(-)
base-commit: 3a8660878839faadb4f1a6dd72c3179c1df56787
--
2.34.1
^ permalink raw reply
* Re: [PATCH 00/18] media: microchip-isc: Color correction and histogram stats
From: Balamanikandan.Gunasundar @ 2025-10-15 6:45 UTC (permalink / raw)
To: kieran.bingham, eugen.hristev
Cc: 3chas3, Nicolas.Ferre, alexandre.belloni, claudiu.beznea,
Balakrishnan.S, hverkuil, ribalda, laurent.pinchart+renesas,
jacopo.mondi, dan.scally+renesas, tomi.valkeinen, linux-kernel,
linux-media, linux-atm-general, netdev, linux-arm-kernel, mchehab
In-Reply-To: <2316c0cb-6a84-432e-8cd3-ca953123bd67@microchip.com>
Hi Kieran,
On 15/10/25 11:35 am, Balamanikandan Gunasundar - I64410 wrote:
> Hi Kieran,
>
> On 10/10/25 1:51 pm, Kieran Bingham wrote:
>>> Hi Bala,
>>>
>>> On 10/9/25 18:52, Balamanikandan Gunasundar wrote:
>>>> Hi,
>>>>
>>>> This patch series has a set of enhancements to the Microchip Image Sensor
>>>> Controller driver. The objective is to expand its image processing
>>>> capabilities and to improve the colors.
>>>>
>>>> This series also introduces a new stats driver that exposes the histogram
>>>> data to userspace via v4l2 controls. This allows applications such as
>>>> libcamera to access real time image statistics for advanced image
>>>> processing like automatic exposure, white balance adjustments etc.
>> How much data do you anticipate to be passing through controls? (What
>> can the hardware provide in total if we look at the bigger picture to
>> support the full device?)
> Thanks for the feedback. Currently the hardware provides histogram data
> with 256 bins per color (R, G, B and Y) each 32 bit wide. So roughly
> around 4 x 256 x 4 = 4K of data per frame. The intent to use it as v4l2
> controls was to make this data easily accessible to user space without a
Correcting my mistake here. The histogram statistics are exported to
userspace as v4l2 meta data through the new driver. Not the v4l2 controls.
The controls like brightness, contrast etc are exported as v4l2 controls.
Thanks,
Bala.
> need for a new data interface initially. However I agree that we may
> expand the statistics for future ISP blocks to include region based
> stats (We are already in discussion with the design)
>> For all other ISPs we've been working towards using structured parameter
>> buffers to pass data - and we've been making that format extensible,
>> which I think could also be a design that can apply to statistics.
> That sounds great and we can certainly explore aligning with the
> structured buffers for histogram data and any other future statistics.
>
> Thanks,
>
> Bala
>
>> This would greatly reduce the overhead of managing 'one control per
>> value' ... or things like passing large tables (like a lens shading
>> table perhaps) through controls.
>>
>> --
>> Kieran
>
^ permalink raw reply
* Forwarded: [PATCH] ocfs2: validate chain list count before use in ocfs2_reserve_suballoc_bits
From: syzbot @ 2025-10-15 6:45 UTC (permalink / raw)
To: linux-kernel, syzkaller-bugs
In-Reply-To: <68ef030a.050a0220.91a22.022b.GAE@google.com>
For archival purposes, forwarding an incoming command email to
linux-kernel@vger.kernel.org, syzkaller-bugs@googlegroups.com.
***
Subject: [PATCH] ocfs2: validate chain list count before use in ocfs2_reserve_suballoc_bits
Author: kartikey406@gmail.com
#syz test: git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
Add validation to check if the chain list count (cl_count) is zero
before using the chain list in ocfs2_reserve_suballoc_bits(). When
cl_count is zero, the cl_recs array is empty, but the code attempts
to access cl_recs[0] in subsequent operations, leading to an
out-of-bounds array access.
The issue was discovered by syzbot using a corrupted filesystem image
where cl_count was set to 0. This triggers a UBSAN array-index-out-of-
bounds error when ocfs2_block_group_fill() attempts to access the
first chain record.
By adding this validation early in ocfs2_reserve_suballoc_bits(), we
catch the corruption before any allocation operations begin. The
filesystem will fail to mount with a clear error message directing
users to run fsck.ocfs2.
This follows the existing pattern in the function where similar
validation checks (like OCFS2_CHAIN_FL) are performed on the
allocator inode before use.
Link: https://syzkaller.appspot.com/bug?extid=77026564530dbc29b854
Reported-by:syzbot+77026564530dbc29b854@syzkaller.appspotmail.com
Tested-by: syzbot+77026564530dbc29b854@syzkaller.appspotmail.com
Signed-off-by: Deepanshu Kartikey <kartikey406@gmail.com>
---
fs/ocfs2/suballoc.c | 8 ++++++++
1 file changed, 8 insertions(+)
---
fs/ocfs2/suballoc.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/fs/ocfs2/suballoc.c b/fs/ocfs2/suballoc.c
index 6ac4dcd54588..57ec07f9751a 100644
--- a/fs/ocfs2/suballoc.c
+++ b/fs/ocfs2/suballoc.c
@@ -778,6 +778,7 @@ static int ocfs2_reserve_suballoc_bits(struct ocfs2_super *osb,
struct buffer_head *bh = NULL;
struct ocfs2_dinode *fe;
u32 free_bits;
+ struct ocfs2_chain_list *cl;
alloc_inode = ocfs2_get_system_file_inode(osb, type, slot);
if (!alloc_inode) {
@@ -800,7 +801,14 @@ static int ocfs2_reserve_suballoc_bits(struct ocfs2_super *osb,
ac->ac_alloc_slot = slot;
fe = (struct ocfs2_dinode *) bh->b_data;
-
+ cl = &fe->id2.i_chain;
+ /* Validate chain list before use */
+ if (le16_to_cpu(cl->cl_count) == 0) {
+ status = ocfs2_error(alloc_inode->i_sb,
+ "Chain allocator %llu has invalid chain list (cl_count=0)\n",
+ (unsigned long long)le64_to_cpu(fe->i_blkno));
+ goto bail;
+ }
/* The bh was validated by the inode read inside
* ocfs2_inode_lock(). Any corruption is a code bug. */
BUG_ON(!OCFS2_IS_VALID_DINODE(fe));
--
2.43.0
^ permalink raw reply related
* [PATCH] mm/khugepaged: fix comment for default scan sleep duration
From: wang lian @ 2025-10-15 6:43 UTC (permalink / raw)
To: Andrew Morton
Cc: David Hildenbrand, Lorenzo Stoakes, Zi Yan, Baolin Wang,
Liam R. Howlett, Nico Pache, Ryan Roberts, Dev Jain, Barry Song,
Lance Yang, Andrea Arcangeli, Rik van Riel, Wei Yang, linux-mm,
linux-kernel, wang lian
The comment for khugepaged_scan_sleep_millisecs incorrectly states
the default scan period is 30 seconds. The actual default value in the
code is 10000ms (10 seconds).
This patch corrects the comment to match the code, preventing potential
confusion. The incorrect comment has existed since the feature was
first introduced.
Fixes: ba76149f47d8 ("thp: khugepaged")
Signed-off-by: wang lian <lianux.mm@gmail.com>
---
mm/khugepaged.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/mm/khugepaged.c b/mm/khugepaged.c
index e947b96e1443..449f983b8891 100644
--- a/mm/khugepaged.c
+++ b/mm/khugepaged.c
@@ -67,7 +67,7 @@ enum scan_result {
static struct task_struct *khugepaged_thread __read_mostly;
static DEFINE_MUTEX(khugepaged_mutex);
-/* default scan 8*512 pte (or vmas) every 30 second */
+/* default scan 8*512 pte (or vmas) every 10 second */
static unsigned int khugepaged_pages_to_scan __read_mostly;
static unsigned int khugepaged_pages_collapsed;
static unsigned int khugepaged_full_scans;
--
2.50.1 (Apple Git-155)
^ permalink raw reply related
* Re: [PATCH net-next] net: remove obsolete WARN_ON(refcount_read(&sk->sk_refcnt) == 1)
From: Eric Dumazet @ 2025-10-15 6:44 UTC (permalink / raw)
To: luoxuanqiang
Cc: David S . Miller, Jakub Kicinski, Paolo Abeni, Simon Horman,
netdev, eric.dumazet, Kuniyuki Iwashima
In-Reply-To: <9e7530fc-c546-4420-9ca7-0e3d0a7b63e5@linux.dev>
On Tue, Oct 14, 2025 at 11:04 PM luoxuanqiang <xuanqiang.luo@linux.dev> wrote:
>
>
> 在 2025/10/14 22:06, Eric Dumazet 写道:
> > sk->sk_refcnt has been converted to refcount_t in 2017.
> >
> > __sock_put(sk) being refcount_dec(&sk->sk_refcnt), it will complain
> > loudly if the current refcnt is 1 (or less) in a non racy way.
> >
> > We can remove four WARN_ON() in favor of the generic refcount_dec()
> > check.
> >
> > Signed-off-by: Eric Dumazet <edumazet@google.com>
>
> Reviewed-by: Xuanqiang Luo<luoxuanqiang@kylinos.cn>
>
> Dear Eric,
>
> Following your line of thought, I found there's also a point in btrfs that
> needs modification.
>
> Would you like to modify it together? Though it has nothing to do with
> socket, or shall I modify it separately later?
I removed stuff around sk_refcnt only.
If you want, please send a patch to the appropriate lists and maintainers.
^ permalink raw reply
* Re: [PATCH 4/4] nvme-pci: unmap MMIO pages with appropriate interface
From: Leon Romanovsky @ 2025-10-15 6:44 UTC (permalink / raw)
To: Christoph Hellwig
Cc: Jens Axboe, Jason Gunthorpe, Keith Busch, linux-block,
linux-kernel, linux-nvme, Sagi Grimberg
In-Reply-To: <20251015042053.GC7073@lst.de>
On Wed, Oct 15, 2025 at 06:20:53AM +0200, Christoph Hellwig wrote:
> On Mon, Oct 13, 2025 at 06:34:12PM +0300, Leon Romanovsky wrote:
> > From: Leon Romanovsky <leonro@nvidia.com>
> >
> > Block layer maps MMIO memory through dma_map_phys() interface
> > with help of DMA_ATTR_MMIO attribute. There is a need to unmap
> > that memory with the appropriate unmap function, something which
> > wasn't possible before adding new REQ attribute to block layer in
> > previous patch.
>
> This should go into the same patch that switches to dma_map_phys.
I don't think so, dma_map_phys() patch [1] doesn't change any behavior
and dma_map_page() is equal to dma_map_phys(... , attr = 0),
> Unless I'm missing something it also misses passing the flag for
> the metadata mapping.
Yes, I didn't realize that same request can have both metadata and data
payloads.
>
> Btw, where is all this going? Are you trying to remove the auto
> detection of P2P in the low-level dma mapping routines? If so that
> should probably go into at very least the cover lttter, but probably also
> the commit logs.
It is an outcome of multiple things:
1. We missed setting of IOMMU_MMIO flag in dma-iommu.c flow for p2p pages
and for that we need some external indication as memory type is already
known to the callers.
2. Robin expressed concerns about overloading DMA_ATTR_SKIP_CPU_SYNC.
[1] https://lore.kernel.org/all/a40705f38a9f3c757f30228b9b848ce0a87cbcdd.1760369219.git.leon@kernel.org/
[2] https://lore.kernel.org/all/751e7ece-8640-4653-b308-96da6731b8e7@arm.com/
^ permalink raw reply
* [PATCH i-g-t] tests/intel-ci : Add Xe Multigpu blocklist file
From: himanshu.girotra @ 2025-10-15 6:44 UTC (permalink / raw)
To: igt-dev; +Cc: ramadevi.gandi
From: Himanshu Girotra <himanshu.girotra@intel.com>
Add Xe Multigpu Blocklist and unblock multigpu tests from core specific
Blocklist to display the metrics on Grafana.
Signed-off-by: Himanshu Girotra <himanshu.girotra@intel.com>
---
tests/intel-ci/meson.build | 1 +
tests/intel-ci/xe.bmg.core.blocklist.txt | 7 -------
tests/intel-ci/xe.multigpu.blocklist.txt | 5 +++++
3 files changed, 6 insertions(+), 7 deletions(-)
create mode 100644 tests/intel-ci/xe.multigpu.blocklist.txt
diff --git a/tests/intel-ci/meson.build b/tests/intel-ci/meson.build
index ca50e93aa..0c3b79d51 100644
--- a/tests/intel-ci/meson.build
+++ b/tests/intel-ci/meson.build
@@ -21,6 +21,7 @@ intelci_files = [
'xe.lnl.core.blocklist.txt',
'xe.lnl.display.blocklist.txt',
'xe.lnl.eudebug.blocklist.txt',
+ 'xe.multigpu.blocklist.txt',
'xe.ptl.core.blocklist.txt',
'xe.ptl.display.blocklist.txt',
'xe-fast-feedback.testlist',
diff --git a/tests/intel-ci/xe.bmg.core.blocklist.txt b/tests/intel-ci/xe.bmg.core.blocklist.txt
index 25da760aa..15dbbf2b8 100644
--- a/tests/intel-ci/xe.bmg.core.blocklist.txt
+++ b/tests/intel-ci/xe.bmg.core.blocklist.txt
@@ -18,13 +18,6 @@ igt@xe_media_fill@media-fill
##################################################################
igt@xe_pat@pat-index-xe3p-xpc
##################################################################
-# Expected skip on single card machines
-##################################################################
-igt@xe_peer2peer@.*
-igt@xe_query@multigpu-query-.*
-igt@xe_create@multigpu-create-massive-size
-igt@xe_exec_basic@.*multigpu.*
-##################################################################
# Expected skip - small bar not supported
##################################################################
igt@xe_mmap@small-bar
diff --git a/tests/intel-ci/xe.multigpu.blocklist.txt b/tests/intel-ci/xe.multigpu.blocklist.txt
new file mode 100644
index 000000000..387c3413e
--- /dev/null
+++ b/tests/intel-ci/xe.multigpu.blocklist.txt
@@ -0,0 +1,5 @@
+#####################################################
+# Blocklist for Xe MuitiGPU tests
+#####################################################
+igt@(?!.*xe.*multigpu.*|xe_peer2peer.*).*
+#####################################################
--
2.40.0
^ permalink raw reply related
* ✗ Xe.CI.Full: failure for drm/i915/prefill: Introduce helpers for prefill latency calculations (rev2)
From: Patchwork @ 2025-10-15 6:42 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-xe
In-Reply-To: <20251014191808.12326-1-ville.syrjala@linux.intel.com>
[-- Attachment #1: Type: text/plain, Size: 72079 bytes --]
== Series Details ==
Series: drm/i915/prefill: Introduce helpers for prefill latency calculations (rev2)
URL : https://patchwork.freedesktop.org/series/155628/
State : failure
== Summary ==
CI Bug Log - changes from xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb_FULL -> xe-pw-155628v2_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-155628v2_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-155628v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-155628v2_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cdclk@plane-scaling@pipe-a-hdmi-a-6:
- shard-dg2-set2: [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-432/igt@kms_cdclk@plane-scaling@pipe-a-hdmi-a-6.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-436/igt@kms_cdclk@plane-scaling@pipe-a-hdmi-a-6.html
* igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-lnl: [PASS][3] -> [INCOMPLETE][4] +1 other test incomplete
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-1/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-5/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_panel_fitting@legacy:
- shard-lnl: [PASS][5] -> [DMESG-WARN][6] +1 other test dmesg-warn
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-4/igt@kms_panel_fitting@legacy.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-7/igt@kms_panel_fitting@legacy.html
* igt@xe_compute_preempt@compute-threadgroup-preempt:
- shard-adlp: NOTRUN -> [SKIP][7]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_compute_preempt@compute-threadgroup-preempt.html
- shard-dg2-set2: NOTRUN -> [SKIP][8]
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-435/igt@xe_compute_preempt@compute-threadgroup-preempt.html
#### Warnings ####
* igt@xe_compute_preempt@compute-preempt:
- shard-dg2-set2: [SKIP][9] ([Intel XE#1280] / [Intel XE#455]) -> [SKIP][10]
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-433/igt@xe_compute_preempt@compute-preempt.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-435/igt@xe_compute_preempt@compute-preempt.html
* igt@xe_compute_preempt@compute-preempt-many:
- shard-adlp: [SKIP][11] ([Intel XE#455] / [Intel XE#5632]) -> [SKIP][12] +2 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-8/igt@xe_compute_preempt@compute-preempt-many.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_compute_preempt@compute-preempt-many.html
- shard-dg2-set2: [FAIL][13] ([Intel XE#5890]) -> [SKIP][14] +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-435/igt@xe_compute_preempt@compute-preempt-many.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-436/igt@xe_compute_preempt@compute-preempt-many.html
* igt@xe_query@multigpu-query-engines:
- shard-adlp: [SKIP][15] ([Intel XE#944]) -> [FAIL][16]
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-1/igt@xe_query@multigpu-query-engines.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_query@multigpu-query-engines.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@xe_compute_preempt@compute-preempt-many-vram-evict}:
- shard-dg2-set2: [FAIL][17] ([Intel XE#5890]) -> [SKIP][18] +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-466/igt@xe_compute_preempt@compute-preempt-many-vram-evict.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-435/igt@xe_compute_preempt@compute-preempt-many-vram-evict.html
* {igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma}:
- shard-lnl: [PASS][19] -> [FAIL][20]
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-3/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-5/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
Known issues
------------
Here are the changes found in xe-pw-155628v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@intel_hwmon@hwmon-read:
- shard-adlp: NOTRUN -> [SKIP][21] ([Intel XE#1125] / [Intel XE#5574])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@intel_hwmon@hwmon-read.html
* igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1:
- shard-lnl: [PASS][22] -> [FAIL][23] ([Intel XE#5993]) +3 other tests fail
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-2/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
* igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [FAIL][24] ([Intel XE#3884]) +1 other test fail
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][25] ([Intel XE#316])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-435/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-adlp: NOTRUN -> [SKIP][26] ([Intel XE#607]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-adlp: NOTRUN -> [SKIP][27] ([Intel XE#610])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-adlp: NOTRUN -> [SKIP][28] ([Intel XE#316]) +5 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- shard-adlp: NOTRUN -> [DMESG-FAIL][29] ([Intel XE#4543]) +11 other tests dmesg-fail
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#2328])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-8/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-dg2-set2: NOTRUN -> [SKIP][31] ([Intel XE#1124])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-466/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
- shard-adlp: NOTRUN -> [SKIP][32] ([Intel XE#1124]) +14 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
- shard-bmg: [PASS][33] -> [SKIP][34] ([Intel XE#2314] / [Intel XE#2894])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-1/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
* igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
- shard-adlp: NOTRUN -> [SKIP][35] ([Intel XE#2191]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
* igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#2314] / [Intel XE#2894])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-8/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-4-displays-2560x1440p:
- shard-adlp: NOTRUN -> [SKIP][37] ([Intel XE#367]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
- shard-dg2-set2: NOTRUN -> [SKIP][38] ([Intel XE#455] / [Intel XE#787]) +7 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-466/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-adlp: NOTRUN -> [SKIP][39] ([Intel XE#2907])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][40] ([Intel XE#787]) +71 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][41] ([Intel XE#787]) +27 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-433/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [PASS][42] -> [INCOMPLETE][43] ([Intel XE#3862]) +1 other test incomplete
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#3432])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
- shard-lnl: NOTRUN -> [SKIP][45] ([Intel XE#2887])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
- shard-adlp: NOTRUN -> [SKIP][46] ([Intel XE#455] / [Intel XE#787]) +47 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: [PASS][47] -> [INCOMPLETE][48] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_chamelium_color@degamma:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#2325])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-6/igt@kms_chamelium_color@degamma.html
- shard-adlp: NOTRUN -> [SKIP][50] ([Intel XE#306])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@kms_chamelium_color@degamma.html
- shard-dg2-set2: NOTRUN -> [SKIP][51] ([Intel XE#306])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-433/igt@kms_chamelium_color@degamma.html
- shard-lnl: NOTRUN -> [SKIP][52] ([Intel XE#306])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-8/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
- shard-adlp: NOTRUN -> [SKIP][53] ([Intel XE#373]) +9 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html
* igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode:
- shard-bmg: NOTRUN -> [SKIP][54] ([Intel XE#2252])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-8/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-adlp: NOTRUN -> [SKIP][55] ([Intel XE#307]) +1 other test skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@srm@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][56] ([Intel XE#1178])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-8/igt@kms_content_protection@srm@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-adlp: NOTRUN -> [SKIP][57] ([Intel XE#308])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-32x32:
- shard-dg2-set2: NOTRUN -> [SKIP][58] ([Intel XE#455])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-466/igt@kms_cursor_crc@cursor-sliding-32x32.html
- shard-bmg: NOTRUN -> [SKIP][59] ([Intel XE#2320])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-4/igt@kms_cursor_crc@cursor-sliding-32x32.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-lnl: NOTRUN -> [SKIP][60] ([Intel XE#1424]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-4/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-adlp: NOTRUN -> [SKIP][61] ([Intel XE#309]) +10 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-bmg: [PASS][62] -> [SKIP][63] ([Intel XE#2291]) +4 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-dg2-set2: NOTRUN -> [SKIP][64] ([Intel XE#323])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-435/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
- shard-adlp: NOTRUN -> [SKIP][65] ([Intel XE#323])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_dp_link_training@uhbr-sst:
- shard-adlp: NOTRUN -> [SKIP][66] ([Intel XE#4356])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@kms_dp_link_training@uhbr-sst.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-lnl: NOTRUN -> [SKIP][67] ([Intel XE#2244])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-4/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
- shard-adlp: NOTRUN -> [SKIP][68] ([Intel XE#4422])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
* igt@kms_fbcon_fbt@fbc:
- shard-bmg: NOTRUN -> [SKIP][69] ([Intel XE#5425])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-1/igt@kms_fbcon_fbt@fbc.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-adlp: NOTRUN -> [SKIP][70] ([Intel XE#776])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@chamelium:
- shard-dg2-set2: NOTRUN -> [SKIP][71] ([Intel XE#701])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-432/igt@kms_feature_discovery@chamelium.html
- shard-adlp: NOTRUN -> [SKIP][72] ([Intel XE#701])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-2/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-2x:
- shard-bmg: [PASS][73] -> [SKIP][74] ([Intel XE#2373])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-3/igt@kms_feature_discovery@display-2x.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-6/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@psr1:
- shard-adlp: NOTRUN -> [SKIP][75] ([Intel XE#1135])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@kms_feature_discovery@psr1.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-bmg: [PASS][76] -> [SKIP][77] ([Intel XE#2316]) +2 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-4/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-lnl: NOTRUN -> [SKIP][78] ([Intel XE#1421])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-7/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
- shard-bmg: NOTRUN -> [SKIP][79] ([Intel XE#2316])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-adlp: NOTRUN -> [SKIP][80] ([Intel XE#310]) +8 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1:
- shard-adlp: NOTRUN -> [DMESG-WARN][81] ([Intel XE#4543]) +3 other tests dmesg-warn
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1:
- shard-adlp: [PASS][82] -> [DMESG-WARN][83] ([Intel XE#4543]) +1 other test dmesg-warn
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend:
- shard-bmg: [PASS][84] -> [INCOMPLETE][85] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_flip@flip-vs-suspend.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-4/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend@d-dp4:
- shard-dg2-set2: [PASS][86] -> [INCOMPLETE][87] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-433/igt@kms_flip@flip-vs-suspend@d-dp4.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-434/igt@kms_flip@flip-vs-suspend@d-dp4.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-bmg: NOTRUN -> [SKIP][88] ([Intel XE#2293] / [Intel XE#2380])
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
- shard-lnl: NOTRUN -> [SKIP][89] ([Intel XE#1401] / [Intel XE#1745])
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][90] ([Intel XE#1401])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][91] ([Intel XE#2293])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling:
- shard-adlp: NOTRUN -> [DMESG-FAIL][92] ([Intel XE#4543] / [Intel XE#4921]) +3 other tests dmesg-fail
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen:
- shard-adlp: NOTRUN -> [SKIP][93] ([Intel XE#651]) +20 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
- shard-adlp: NOTRUN -> [SKIP][94] ([Intel XE#656]) +49 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff:
- shard-dg2-set2: NOTRUN -> [SKIP][95] ([Intel XE#651]) +5 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt:
- shard-lnl: NOTRUN -> [SKIP][96] ([Intel XE#656]) +3 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-bmg: NOTRUN -> [SKIP][97] ([Intel XE#5390])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][98] ([Intel XE#2311]) +4 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][99] ([Intel XE#2312]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-adlp: NOTRUN -> [SKIP][100] ([Intel XE#653]) +14 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-adlp: NOTRUN -> [SKIP][101] ([Intel XE#1151])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][102] ([Intel XE#2313]) +2 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
- shard-dg2-set2: NOTRUN -> [SKIP][103] ([Intel XE#653]) +7 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
* igt@kms_joiner@basic-big-joiner:
- shard-adlp: NOTRUN -> [SKIP][104] ([Intel XE#346])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-2/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-bmg: NOTRUN -> [SKIP][105] ([Intel XE#2934])
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-4/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_panel_fitting@legacy:
- shard-adlp: NOTRUN -> [SKIP][106] ([Intel XE#455]) +25 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
- shard-dg2-set2: NOTRUN -> [FAIL][107] ([Intel XE#616]) +3 other tests fail
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-433/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html
* igt@kms_plane_multiple@2x-tiling-none:
- shard-adlp: NOTRUN -> [SKIP][108] ([Intel XE#4596])
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@kms_plane_multiple@2x-tiling-none.html
* igt@kms_plane_multiple@2x-tiling-x:
- shard-bmg: [PASS][109] -> [SKIP][110] ([Intel XE#4596])
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-x.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-x.html
* igt@kms_plane_multiple@2x-tiling-y:
- shard-bmg: NOTRUN -> [SKIP][111] ([Intel XE#5021])
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-y.html
* igt@kms_plane_multiple@tiling-4:
- shard-adlp: NOTRUN -> [SKIP][112] ([Intel XE#5020])
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@kms_plane_multiple@tiling-4.html
* igt@kms_pm_backlight@fade:
- shard-adlp: NOTRUN -> [SKIP][113] ([Intel XE#870])
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@kms_pm_backlight@fade.html
* igt@kms_pm_dc@dc5-psr:
- shard-adlp: NOTRUN -> [SKIP][114] ([Intel XE#1129])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@kms_pm_dc@dc5-psr.html
- shard-lnl: [PASS][115] -> [FAIL][116] ([Intel XE#718])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-8/igt@kms_pm_dc@dc5-psr.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-1/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_dc@dc6-psr:
- shard-bmg: NOTRUN -> [SKIP][117] ([Intel XE#2392])
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-3/igt@kms_pm_dc@dc6-psr.html
* igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
- shard-dg2-set2: NOTRUN -> [SKIP][118] ([Intel XE#1406] / [Intel XE#1489])
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-435/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf:
- shard-adlp: NOTRUN -> [SKIP][119] ([Intel XE#1406] / [Intel XE#1489]) +9 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
- shard-bmg: NOTRUN -> [SKIP][120] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-2/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-adlp: NOTRUN -> [SKIP][121] ([Intel XE#1122] / [Intel XE#1406] / [Intel XE#5580]) +1 other test skip
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@fbc-psr2-cursor-plane-move:
- shard-adlp: NOTRUN -> [SKIP][122] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +18 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@kms_psr@fbc-psr2-cursor-plane-move.html
* igt@kms_psr@fbc-psr2-primary-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][123] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929])
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-463/igt@kms_psr@fbc-psr2-primary-blt.html
* igt@kms_psr@pr-primary-blt:
- shard-bmg: NOTRUN -> [SKIP][124] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +1 other test skip
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-1/igt@kms_psr@pr-primary-blt.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-adlp: NOTRUN -> [SKIP][125] ([Intel XE#3414]) +4 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-2/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-adlp: NOTRUN -> [SKIP][126] ([Intel XE#1127])
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_tv_load_detect@load-detect:
- shard-adlp: NOTRUN -> [SKIP][127] ([Intel XE#330])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vrr@cmrr@pipe-a-edp-1:
- shard-lnl: [PASS][128] -> [FAIL][129] ([Intel XE#4459]) +1 other test fail
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-2/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-1/igt@kms_vrr@cmrr@pipe-a-edp-1.html
* igt@xe_ccs@block-multicopy-compressed:
- shard-adlp: NOTRUN -> [SKIP][130] ([Intel XE#455] / [Intel XE#488] / [Intel XE#5607]) +1 other test skip
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-2/igt@xe_ccs@block-multicopy-compressed.html
* igt@xe_configfs@survivability-mode:
- shard-adlp: NOTRUN -> [SKIP][131] ([Intel XE#6010])
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@xe_configfs@survivability-mode.html
* igt@xe_copy_basic@mem-copy-linear-0xfd:
- shard-adlp: NOTRUN -> [SKIP][132] ([Intel XE#1123])
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_copy_basic@mem-copy-linear-0xfd.html
* igt@xe_copy_basic@mem-set-linear-0x369:
- shard-adlp: NOTRUN -> [SKIP][133] ([Intel XE#1126])
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-2/igt@xe_copy_basic@mem-set-linear-0x369.html
* igt@xe_eu_stall@unprivileged-access:
- shard-adlp: NOTRUN -> [SKIP][134] ([Intel XE#5626])
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@xe_eu_stall@unprivileged-access.html
- shard-dg2-set2: NOTRUN -> [SKIP][135] ([Intel XE#5626])
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-435/igt@xe_eu_stall@unprivileged-access.html
* igt@xe_eudebug@read-metadata:
- shard-lnl: NOTRUN -> [SKIP][136] ([Intel XE#4837]) +1 other test skip
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-3/igt@xe_eudebug@read-metadata.html
* igt@xe_eudebug_online@interrupt-other-debuggable:
- shard-dg2-set2: NOTRUN -> [SKIP][137] ([Intel XE#4837]) +3 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-466/igt@xe_eudebug_online@interrupt-other-debuggable.html
* igt@xe_eudebug_online@single-step:
- shard-adlp: NOTRUN -> [SKIP][138] ([Intel XE#4837] / [Intel XE#5565]) +13 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@xe_eudebug_online@single-step.html
* igt@xe_eudebug_online@stopped-thread:
- shard-bmg: NOTRUN -> [SKIP][139] ([Intel XE#4837]) +3 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-8/igt@xe_eudebug_online@stopped-thread.html
* igt@xe_evict@evict-beng-cm-threads-small:
- shard-adlp: NOTRUN -> [SKIP][140] ([Intel XE#261]) +4 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@xe_evict@evict-beng-cm-threads-small.html
* igt@xe_evict@evict-beng-large-multi-vm:
- shard-adlp: NOTRUN -> [SKIP][141] ([Intel XE#261] / [Intel XE#5564]) +1 other test skip
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@xe_evict@evict-beng-large-multi-vm.html
* igt@xe_evict@evict-small-external-cm:
- shard-adlp: NOTRUN -> [SKIP][142] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688]) +3 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@xe_evict@evict-small-external-cm.html
* igt@xe_evict@evict-threads-small:
- shard-adlp: NOTRUN -> [SKIP][143] ([Intel XE#261] / [Intel XE#688]) +2 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_evict@evict-threads-small.html
* igt@xe_evict_ccs@evict-overcommit-standalone-nofree-reopen:
- shard-adlp: NOTRUN -> [SKIP][144] ([Intel XE#688]) +1 other test skip
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-2/igt@xe_evict_ccs@evict-overcommit-standalone-nofree-reopen.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind:
- shard-adlp: NOTRUN -> [SKIP][145] ([Intel XE#1392] / [Intel XE#5575]) +10 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html
- shard-bmg: NOTRUN -> [SKIP][146] ([Intel XE#2322])
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-7/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html
- shard-lnl: NOTRUN -> [SKIP][147] ([Intel XE#1392])
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-7/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html
* igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-imm:
- shard-adlp: NOTRUN -> [SKIP][148] ([Intel XE#288] / [Intel XE#5561]) +34 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-imm.html
* igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][149] ([Intel XE#288]) +3 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-436/igt@xe_exec_fault_mode@many-execqueues-userptr-invalidate-race-imm.html
* igt@xe_exec_system_allocator@threads-many-malloc-mlock-nomemset:
- shard-dg2-set2: NOTRUN -> [SKIP][150] ([Intel XE#4915]) +43 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-436/igt@xe_exec_system_allocator@threads-many-malloc-mlock-nomemset.html
* igt@xe_exec_system_allocator@threads-many-stride-mmap-huge:
- shard-bmg: NOTRUN -> [SKIP][151] ([Intel XE#4943]) +2 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-7/igt@xe_exec_system_allocator@threads-many-stride-mmap-huge.html
- shard-lnl: NOTRUN -> [SKIP][152] ([Intel XE#4943])
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-5/igt@xe_exec_system_allocator@threads-many-stride-mmap-huge.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-race-nomemset:
- shard-adlp: NOTRUN -> [SKIP][153] ([Intel XE#4915]) +353 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@xe_exec_system_allocator@threads-shared-vm-many-large-mmap-new-race-nomemset.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-dg2-set2: NOTRUN -> [ABORT][154] ([Intel XE#4917] / [Intel XE#5466])
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-464/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
- shard-adlp: NOTRUN -> [ABORT][155] ([Intel XE#5530])
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
* igt@xe_mmap@pci-membarrier-parallel:
- shard-adlp: NOTRUN -> [SKIP][156] ([Intel XE#5100])
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_mmap@pci-membarrier-parallel.html
* igt@xe_oa@mmio-triggered-reports-read:
- shard-adlp: NOTRUN -> [SKIP][157] ([Intel XE#6032])
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@xe_oa@mmio-triggered-reports-read.html
* igt@xe_oa@syncs-syncobj-cfg:
- shard-adlp: NOTRUN -> [SKIP][158] ([Intel XE#3573]) +6 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_oa@syncs-syncobj-cfg.html
- shard-dg2-set2: NOTRUN -> [SKIP][159] ([Intel XE#3573])
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-436/igt@xe_oa@syncs-syncobj-cfg.html
* igt@xe_pat@display-vs-wb-transient:
- shard-dg2-set2: NOTRUN -> [SKIP][160] ([Intel XE#1337])
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-466/igt@xe_pat@display-vs-wb-transient.html
* igt@xe_peer2peer@read:
- shard-adlp: NOTRUN -> [SKIP][161] ([Intel XE#1061] / [Intel XE#5568])
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@xe_peer2peer@read.html
* igt@xe_pm@d3hot-i2c:
- shard-adlp: NOTRUN -> [SKIP][162] ([Intel XE#5742])
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_pm@d3hot-i2c.html
* igt@xe_pm@s3-d3cold-basic-exec:
- shard-adlp: NOTRUN -> [SKIP][163] ([Intel XE#2284] / [Intel XE#366]) +2 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@xe_pm@s3-d3cold-basic-exec.html
* igt@xe_pm@s4-basic:
- shard-lnl: [PASS][164] -> [FAIL][165] ([Intel XE#6339]) +1 other test fail
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-8/igt@xe_pm@s4-basic.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-5/igt@xe_pm@s4-basic.html
* igt@xe_pmu@fn-engine-activity-load:
- shard-dg2-set2: NOTRUN -> [SKIP][166] ([Intel XE#4650]) +1 other test skip
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-434/igt@xe_pmu@fn-engine-activity-load.html
* igt@xe_pmu@fn-engine-activity-sched-if-idle:
- shard-bmg: [PASS][167] -> [DMESG-WARN][168] ([Intel XE#3876])
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-3/igt@xe_pmu@fn-engine-activity-sched-if-idle.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-8/igt@xe_pmu@fn-engine-activity-sched-if-idle.html
* igt@xe_pxp@display-pxp-fb:
- shard-adlp: NOTRUN -> [SKIP][169] ([Intel XE#4733]) +1 other test skip
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@xe_pxp@display-pxp-fb.html
- shard-dg2-set2: NOTRUN -> [SKIP][170] ([Intel XE#4733])
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-433/igt@xe_pxp@display-pxp-fb.html
* igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq:
- shard-adlp: NOTRUN -> [SKIP][171] ([Intel XE#4733] / [Intel XE#5594]) +6 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html
* igt@xe_query@multigpu-query-uc-fw-version-huc:
- shard-adlp: NOTRUN -> [SKIP][172] ([Intel XE#944]) +2 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@xe_query@multigpu-query-uc-fw-version-huc.html
* igt@xe_render_copy@render-stress-4-copies:
- shard-adlp: NOTRUN -> [SKIP][173] ([Intel XE#4814] / [Intel XE#5614]) +2 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@xe_render_copy@render-stress-4-copies.html
* igt@xe_spin_batch@spin-mem-copy:
- shard-adlp: NOTRUN -> [SKIP][174] ([Intel XE#4821])
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@xe_spin_batch@spin-mem-copy.html
* igt@xe_sriov_scheduling@equal-throughput:
- shard-adlp: NOTRUN -> [DMESG-FAIL][175] ([Intel XE#3868] / [Intel XE#5213] / [Intel XE#5545]) +1 other test dmesg-fail
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_sriov_scheduling@equal-throughput.html
#### Possible fixes ####
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: [INCOMPLETE][176] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [PASS][177]
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: [INCOMPLETE][178] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][179]
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-bmg: [SKIP][180] ([Intel XE#2291]) -> [PASS][181] +2 other tests pass
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [FAIL][182] ([Intel XE#5299]) -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_dp_aux_dev:
- shard-bmg: [SKIP][184] ([Intel XE#3009]) -> [PASS][185]
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_dp_aux_dev.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-3/igt@kms_dp_aux_dev.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-bmg: [SKIP][186] ([Intel XE#4354]) -> [PASS][187]
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-7/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-bmg: [SKIP][188] ([Intel XE#2316]) -> [PASS][189]
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-7/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@flip-vs-rmfb:
- shard-adlp: [DMESG-WARN][190] ([Intel XE#5208]) -> [PASS][191]
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-9/igt@kms_flip@flip-vs-rmfb.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@kms_flip@flip-vs-rmfb.html
* igt@kms_flip@flip-vs-rmfb@d-hdmi-a1:
- shard-adlp: [DMESG-WARN][192] ([Intel XE#4543]) -> [PASS][193] +6 other tests pass
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-9/igt@kms_flip@flip-vs-rmfb@d-hdmi-a1.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@kms_flip@flip-vs-rmfb@d-hdmi-a1.html
* igt@kms_plane_scaling@planes-upscale-20x20:
- shard-adlp: [DMESG-WARN][194] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][195] +4 other tests pass
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-1/igt@kms_plane_scaling@planes-upscale-20x20.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@kms_plane_scaling@planes-upscale-20x20.html
* igt@kms_pm_dc@dc6-psr:
- shard-lnl: [FAIL][196] ([Intel XE#718]) -> [PASS][197]
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-7/igt@kms_pm_dc@dc6-psr.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-7/igt@kms_pm_dc@dc6-psr.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-bmg: [SKIP][198] ([Intel XE#1435]) -> [PASS][199]
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-8/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@xe_module_load@load:
- shard-adlp: ([PASS][200], [PASS][201], [SKIP][202], [PASS][203], [PASS][204], [PASS][205], [PASS][206], [PASS][207], [PASS][208], [PASS][209], [PASS][210], [PASS][211], [PASS][212], [PASS][213], [PASS][214], [PASS][215]) ([Intel XE#378] / [Intel XE#5612]) -> ([PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [PASS][223], [PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230])
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-9/igt@xe_module_load@load.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-9/igt@xe_module_load@load.html
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-2/igt@xe_module_load@load.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-2/igt@xe_module_load@load.html
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-2/igt@xe_module_load@load.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-6/igt@xe_module_load@load.html
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-6/igt@xe_module_load@load.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-6/igt@xe_module_load@load.html
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-8/igt@xe_module_load@load.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-8/igt@xe_module_load@load.html
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-1/igt@xe_module_load@load.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-1/igt@xe_module_load@load.html
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-9/igt@xe_module_load@load.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-8/igt@xe_module_load@load.html
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-1/igt@xe_module_load@load.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-2/igt@xe_module_load@load.html
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_module_load@load.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@xe_module_load@load.html
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_module_load@load.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-2/igt@xe_module_load@load.html
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-2/igt@xe_module_load@load.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@xe_module_load@load.html
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@xe_module_load@load.html
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-9/igt@xe_module_load@load.html
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-6/igt@xe_module_load@load.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@xe_module_load@load.html
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@xe_module_load@load.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@xe_module_load@load.html
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@xe_module_load@load.html
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-1/igt@xe_module_load@load.html
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-2/igt@xe_module_load@load.html
* igt@xe_pm@s4-basic-exec:
- shard-bmg: [FAIL][231] ([Intel XE#6339]) -> [PASS][232]
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-1/igt@xe_pm@s4-basic-exec.html
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-1/igt@xe_pm@s4-basic-exec.html
- shard-dg2-set2: [FAIL][233] ([Intel XE#6339]) -> [PASS][234]
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-466/igt@xe_pm@s4-basic-exec.html
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-463/igt@xe_pm@s4-basic-exec.html
* igt@xe_pm@s4-d3hot-basic-exec:
- shard-lnl: [FAIL][235] ([Intel XE#6339]) -> [PASS][236] +3 other tests pass
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-lnl-8/igt@xe_pm@s4-d3hot-basic-exec.html
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-lnl-4/igt@xe_pm@s4-d3hot-basic-exec.html
#### Warnings ####
* igt@kms_content_protection@srm:
- shard-bmg: [SKIP][237] ([Intel XE#2341]) -> [FAIL][238] ([Intel XE#1178])
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_content_protection@srm.html
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-8/igt@kms_content_protection@srm.html
* igt@kms_flip@flip-vs-suspend:
- shard-adlp: [DMESG-WARN][239] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [DMESG-WARN][240] ([Intel XE#4543])
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-adlp-1/igt@kms_flip@flip-vs-suspend.html
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-adlp-8/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt:
- shard-bmg: [SKIP][241] ([Intel XE#2311]) -> [SKIP][242] ([Intel XE#2312]) +9 other tests skip
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][243] ([Intel XE#2312]) -> [SKIP][244] ([Intel XE#2311]) +8 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
- shard-bmg: [SKIP][245] ([Intel XE#5390]) -> [SKIP][246] ([Intel XE#2312]) +6 other tests skip
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][247] ([Intel XE#2312]) -> [SKIP][248] ([Intel XE#5390]) +3 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][249] ([Intel XE#2312]) -> [SKIP][250] ([Intel XE#2313]) +7 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-bmg: [SKIP][251] ([Intel XE#2313]) -> [SKIP][252] ([Intel XE#2312]) +6 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][253] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][254] ([Intel XE#3544])
[253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-4/igt@kms_hdr@brightness-with-hdr.html
[254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2-set2: [SKIP][255] ([Intel XE#362]) -> [SKIP][256] ([Intel XE#1500])
[255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-bmg: [ABORT][257] ([Intel XE#5466] / [Intel XE#5530]) -> [ABORT][258] ([Intel XE#4917] / [Intel XE#5466] / [Intel XE#5530])
[257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb/shard-bmg-7/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/shard-bmg-4/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
[Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
[Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
[Intel XE#1151]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1151
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
[Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2934]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2934
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4356
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
[Intel XE#4821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4821
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
[Intel XE#4921]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4921
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
[Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
[Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
[Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
[Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
[Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
[Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5425
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
[Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
[Intel XE#5568]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5568
[Intel XE#5574]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5574
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5580]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5580
[Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
[Intel XE#5607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5607
[Intel XE#5612]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5612
[Intel XE#5614]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5614
[Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
[Intel XE#5632]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5632
[Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
[Intel XE#5745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5745
[Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
[Intel XE#5890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5890
[Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
[Intel XE#6010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6010
[Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#6258]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6258
[Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6320
[Intel XE#6326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6326
[Intel XE#6339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6339
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
[Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_8582 -> IGT_8583
* Linux: xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb -> xe-pw-155628v2
IGT_8582: 8582
IGT_8583: 8583
xe-3921-c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb: c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb
xe-pw-155628v2: 155628v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155628v2/index.html
[-- Attachment #2: Type: text/html, Size: 83298 bytes --]
^ permalink raw reply
* Re: [f2fs-dev] [PATCH] f2fs: Perform sanity check before unlinking directory inode
From: Chao Yu via Linux-f2fs-devel @ 2025-10-15 6:41 UTC (permalink / raw)
To: Nikola Z. Ivanov
Cc: david.hunter.linux, syzbot+c07d47c7bc68f47b9083, linux-kernel,
linux-f2fs-devel, khalid, skhan, jaegeuk, linux-kernel-mentees
In-Reply-To: <zomib7dzvmnggqqy6aqlwij3zihbvzkzrnfvzhk7tcp2mdgh34@tjjugevo4q4a>
On 10/14/25 20:17, Nikola Z. Ivanov wrote:
> On Mon, Oct 13, 2025 at 08:53:04PM +0800, Chao Yu wrote:
>> On 10/13/25 05:19, Nikola Z. Ivanov wrote:
>>> On Thu, Oct 09, 2025 at 10:54:40AM +0800, Chao Yu wrote:
>>>> On 10/3/2025 9:47 PM, Nikola Z. Ivanov wrote:
>>>>> Current i_nlink corruption check does not take into account
>>>>> directory inodes which have one additional i_nlink for their "." entry.
>>>>>
>>>>> Add additional check and a common corruption path.
>>>>>
>>>>> Reported-by: syzbot+c07d47c7bc68f47b9083@syzkaller.appspotmail.com
>>>>> Closes: https://syzkaller.appspot.com/bug?extid=c07d47c7bc68f47b9083
>>>>> Fixes: 81edb983b3f5 ("f2fs: add check for deleted inode")
>>>>> Signed-off-by: Nikola Z. Ivanov <zlatistiv@gmail.com>
>>>>> ---
>>>>> fs/f2fs/namei.c | 28 ++++++++++++++++++++--------
>>>>> 1 file changed, 20 insertions(+), 8 deletions(-)
>>>>>
>>>>> diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c
>>>>> index b882771e4699..68b33e8089b0 100644
>>>>> --- a/fs/f2fs/namei.c
>>>>> +++ b/fs/f2fs/namei.c
>>>>> @@ -502,12 +502,14 @@ static struct dentry *f2fs_lookup(struct inode *dir, struct dentry *dentry,
>>>>> goto out;
>>>>> }
>>>>> - if (inode->i_nlink == 0) {
>>>>> + if (unlikely(inode->i_nlink == 0)) {
>>>>> f2fs_warn(F2FS_I_SB(inode), "%s: inode (ino=%lx) has zero i_nlink",
>>>>> __func__, inode->i_ino);
>>>>> - err = -EFSCORRUPTED;
>>>>> - set_sbi_flag(F2FS_I_SB(inode), SBI_NEED_FSCK);
>>>>> - goto out_iput;
>>>>> + goto corrupted;
>>>>> + } else if (unlikely(S_ISDIR(inode->i_mode) && inode->i_nlink == 1)) {
>>>>> + f2fs_warn(F2FS_I_SB(inode), "%s: directory inode (ino=%lx) has a single i_nlink",
>>>>> + __func__, inode->i_ino);
>>>>> + goto corrupted;
>>>>
>>>> Can we detect such corruption in sanity_check_inode() as well? So that if
>>>> f2fs internal flow calls f2fs_iget() on corrupted inode, we can set SBI_NEED_FSCK
>>>> flag and then triggering fsck repairment later.
>>>>
>>>> Thanks,
>>>>
>>>>> }
>>>>> if (IS_ENCRYPTED(dir) &&
>>>>> @@ -533,6 +535,9 @@ static struct dentry *f2fs_lookup(struct inode *dir, struct dentry *dentry,
>>>>> trace_f2fs_lookup_end(dir, !IS_ERR_OR_NULL(new) ? new : dentry,
>>>>> ino, IS_ERR(new) ? PTR_ERR(new) : err);
>>>>> return new;
>>>>> +corrupted:
>>>>> + err = -EFSCORRUPTED;
>>>>> + set_sbi_flag(F2FS_I_SB(inode), SBI_NEED_FSCK);
>>>>> out_iput:
>>>>> iput(inode);
>>>>> out:
>>>>> @@ -572,10 +577,11 @@ static int f2fs_unlink(struct inode *dir, struct dentry *dentry)
>>>>> if (unlikely(inode->i_nlink == 0)) {
>>>>> f2fs_warn(F2FS_I_SB(inode), "%s: inode (ino=%lx) has zero i_nlink",
>>>>> __func__, inode->i_ino);
>>>>> - err = -EFSCORRUPTED;
>>>>> - set_sbi_flag(F2FS_I_SB(inode), SBI_NEED_FSCK);
>>>>> - f2fs_folio_put(folio, false);
>>>>> - goto fail;
>>>>> + goto corrupted;
>>>>> + } else if (unlikely(S_ISDIR(inode->i_mode) && inode->i_nlink == 1)) {
>>>>> + f2fs_warn(F2FS_I_SB(inode), "%s: directory inode (ino=%lx) has a single i_nlink",
>>>>> + __func__, inode->i_ino);
>>>>> + goto corrupted;
>>>>> }
>>>>> f2fs_balance_fs(sbi, true);
>>>>> @@ -601,6 +607,12 @@ static int f2fs_unlink(struct inode *dir, struct dentry *dentry)
>>>>> if (IS_DIRSYNC(dir))
>>>>> f2fs_sync_fs(sbi->sb, 1);
>>>>> +
>>>>> + goto fail;
>>>>> +corrupted:
>>>>> + err = -EFSCORRUPTED;
>>>>> + set_sbi_flag(F2FS_I_SB(inode), SBI_NEED_FSCK);
>>>>> + f2fs_folio_put(folio, false);
>>>>> fail:
>>>>> trace_f2fs_unlink_exit(inode, err);
>>>>> return err;
>>>>
>>>
>>> Hi Chao,
>>>
>>> Thank you for the suggestion.
>>> I will add this to sanity_check_inode and remove it
>>> from f2fs_lookup as it becomes redundant since f2fs_lookup
>>> obtains the inode through f2fs_iget. For f2fs_unlink I will
>>> move the i_nlink == 1 check to f2fs_rmdir.
>>
>> Hi Nikola,
>>
>> I meant we can move the i_nlink == 1 check from both f2fs_lookup() and
>> f2fs_unlink() to sanity_check_inode(), because before we create in-memory
>> inode, we will always call sanity_check_inode().
>>
>> Let me know if you have other concerns.
>>
>> Thanks,
>>
>
> The issue here is that sanity_check_inode will be called only when
> we initially read the inode off disk, not when it's already in the cache
>
> The syzkaller repro does something like this:
> Creates a directory structure /dir1/dir2 where dir1 has
> i_nlink == 2, which is one less than it should. It then does
> rmdir(/dir1/dir2) followed by rmdir(/dir1) which leads to the warning.
Oh, I missed this case.
>
> In such case what would you say should happen, should the second rmdir
> fail and report the corruption, or do we close our eyes and just drop
> i_nlink to 0 and possibly log a message that something isn't quite right?
I agreed that we should keep i_nlink == 1 check in f2fs_unlink().
Thanks,
>
> Thank you,
>
>>>
>>> I will send v2 as soon as I do some more testing.
>>
_______________________________________________
Linux-f2fs-devel mailing list
Linux-f2fs-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/linux-f2fs-devel
^ permalink raw reply
* Re: [PATCH] f2fs: Perform sanity check before unlinking directory inode
From: Chao Yu @ 2025-10-15 6:41 UTC (permalink / raw)
To: Nikola Z. Ivanov
Cc: chao, jaegeuk, linux-f2fs-devel, linux-kernel, skhan,
david.hunter.linux, linux-kernel-mentees, khalid,
syzbot+c07d47c7bc68f47b9083
In-Reply-To: <zomib7dzvmnggqqy6aqlwij3zihbvzkzrnfvzhk7tcp2mdgh34@tjjugevo4q4a>
On 10/14/25 20:17, Nikola Z. Ivanov wrote:
> On Mon, Oct 13, 2025 at 08:53:04PM +0800, Chao Yu wrote:
>> On 10/13/25 05:19, Nikola Z. Ivanov wrote:
>>> On Thu, Oct 09, 2025 at 10:54:40AM +0800, Chao Yu wrote:
>>>> On 10/3/2025 9:47 PM, Nikola Z. Ivanov wrote:
>>>>> Current i_nlink corruption check does not take into account
>>>>> directory inodes which have one additional i_nlink for their "." entry.
>>>>>
>>>>> Add additional check and a common corruption path.
>>>>>
>>>>> Reported-by: syzbot+c07d47c7bc68f47b9083@syzkaller.appspotmail.com
>>>>> Closes: https://syzkaller.appspot.com/bug?extid=c07d47c7bc68f47b9083
>>>>> Fixes: 81edb983b3f5 ("f2fs: add check for deleted inode")
>>>>> Signed-off-by: Nikola Z. Ivanov <zlatistiv@gmail.com>
>>>>> ---
>>>>> fs/f2fs/namei.c | 28 ++++++++++++++++++++--------
>>>>> 1 file changed, 20 insertions(+), 8 deletions(-)
>>>>>
>>>>> diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c
>>>>> index b882771e4699..68b33e8089b0 100644
>>>>> --- a/fs/f2fs/namei.c
>>>>> +++ b/fs/f2fs/namei.c
>>>>> @@ -502,12 +502,14 @@ static struct dentry *f2fs_lookup(struct inode *dir, struct dentry *dentry,
>>>>> goto out;
>>>>> }
>>>>> - if (inode->i_nlink == 0) {
>>>>> + if (unlikely(inode->i_nlink == 0)) {
>>>>> f2fs_warn(F2FS_I_SB(inode), "%s: inode (ino=%lx) has zero i_nlink",
>>>>> __func__, inode->i_ino);
>>>>> - err = -EFSCORRUPTED;
>>>>> - set_sbi_flag(F2FS_I_SB(inode), SBI_NEED_FSCK);
>>>>> - goto out_iput;
>>>>> + goto corrupted;
>>>>> + } else if (unlikely(S_ISDIR(inode->i_mode) && inode->i_nlink == 1)) {
>>>>> + f2fs_warn(F2FS_I_SB(inode), "%s: directory inode (ino=%lx) has a single i_nlink",
>>>>> + __func__, inode->i_ino);
>>>>> + goto corrupted;
>>>>
>>>> Can we detect such corruption in sanity_check_inode() as well? So that if
>>>> f2fs internal flow calls f2fs_iget() on corrupted inode, we can set SBI_NEED_FSCK
>>>> flag and then triggering fsck repairment later.
>>>>
>>>> Thanks,
>>>>
>>>>> }
>>>>> if (IS_ENCRYPTED(dir) &&
>>>>> @@ -533,6 +535,9 @@ static struct dentry *f2fs_lookup(struct inode *dir, struct dentry *dentry,
>>>>> trace_f2fs_lookup_end(dir, !IS_ERR_OR_NULL(new) ? new : dentry,
>>>>> ino, IS_ERR(new) ? PTR_ERR(new) : err);
>>>>> return new;
>>>>> +corrupted:
>>>>> + err = -EFSCORRUPTED;
>>>>> + set_sbi_flag(F2FS_I_SB(inode), SBI_NEED_FSCK);
>>>>> out_iput:
>>>>> iput(inode);
>>>>> out:
>>>>> @@ -572,10 +577,11 @@ static int f2fs_unlink(struct inode *dir, struct dentry *dentry)
>>>>> if (unlikely(inode->i_nlink == 0)) {
>>>>> f2fs_warn(F2FS_I_SB(inode), "%s: inode (ino=%lx) has zero i_nlink",
>>>>> __func__, inode->i_ino);
>>>>> - err = -EFSCORRUPTED;
>>>>> - set_sbi_flag(F2FS_I_SB(inode), SBI_NEED_FSCK);
>>>>> - f2fs_folio_put(folio, false);
>>>>> - goto fail;
>>>>> + goto corrupted;
>>>>> + } else if (unlikely(S_ISDIR(inode->i_mode) && inode->i_nlink == 1)) {
>>>>> + f2fs_warn(F2FS_I_SB(inode), "%s: directory inode (ino=%lx) has a single i_nlink",
>>>>> + __func__, inode->i_ino);
>>>>> + goto corrupted;
>>>>> }
>>>>> f2fs_balance_fs(sbi, true);
>>>>> @@ -601,6 +607,12 @@ static int f2fs_unlink(struct inode *dir, struct dentry *dentry)
>>>>> if (IS_DIRSYNC(dir))
>>>>> f2fs_sync_fs(sbi->sb, 1);
>>>>> +
>>>>> + goto fail;
>>>>> +corrupted:
>>>>> + err = -EFSCORRUPTED;
>>>>> + set_sbi_flag(F2FS_I_SB(inode), SBI_NEED_FSCK);
>>>>> + f2fs_folio_put(folio, false);
>>>>> fail:
>>>>> trace_f2fs_unlink_exit(inode, err);
>>>>> return err;
>>>>
>>>
>>> Hi Chao,
>>>
>>> Thank you for the suggestion.
>>> I will add this to sanity_check_inode and remove it
>>> from f2fs_lookup as it becomes redundant since f2fs_lookup
>>> obtains the inode through f2fs_iget. For f2fs_unlink I will
>>> move the i_nlink == 1 check to f2fs_rmdir.
>>
>> Hi Nikola,
>>
>> I meant we can move the i_nlink == 1 check from both f2fs_lookup() and
>> f2fs_unlink() to sanity_check_inode(), because before we create in-memory
>> inode, we will always call sanity_check_inode().
>>
>> Let me know if you have other concerns.
>>
>> Thanks,
>>
>
> The issue here is that sanity_check_inode will be called only when
> we initially read the inode off disk, not when it's already in the cache
>
> The syzkaller repro does something like this:
> Creates a directory structure /dir1/dir2 where dir1 has
> i_nlink == 2, which is one less than it should. It then does
> rmdir(/dir1/dir2) followed by rmdir(/dir1) which leads to the warning.
Oh, I missed this case.
>
> In such case what would you say should happen, should the second rmdir
> fail and report the corruption, or do we close our eyes and just drop
> i_nlink to 0 and possibly log a message that something isn't quite right?
I agreed that we should keep i_nlink == 1 check in f2fs_unlink().
Thanks,
>
> Thank you,
>
>>>
>>> I will send v2 as soon as I do some more testing.
>>
^ permalink raw reply
* Re: [PATCH v2 19/19] drivers: fix Klocwork issues
From: Jerin Jacob @ 2025-10-15 6:41 UTC (permalink / raw)
To: Nithin Dabilpuram
Cc: Thomas Monjalon, Kiran Kumar K, Sunil Kumar Kori, Satha Rao,
Harman Kalra, jerinj, dev, Aarnav JP, stable
In-Reply-To: <20251013065949.200414-19-ndabilpuram@marvell.com>
On Mon, Oct 13, 2025 at 1:50 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Aarnav JP <ajp@marvell.com>
>
> fixed klocwork suggested issues in
> cnxk component of drivers module
>
> Fixes: db5744d3cd23 ("common/cnxk: support NIX debug for CN20K")
> Fixes: 3c31a7485172 ("common/cnxk: config CPT result address for CN20K")
> Fixes: 4b8eb5bd6627 ("common/cnxk: reserve CPT LF for Rx inject")
> Fixes: f410059baac6 ("common/cnxk: support inline inbound queue")
> Fixes: 47cca253d605 ("net/cnxk: support Rx inject")
> Fixes: ac35d4bf4cd6 ("net/cnxk: support ingress meter pre-color")
> Cc: stable@dpdk.org
Fix the following issues
### [PATCH] common/cnxk: add support for per packet SQ count update
Warning in drivers/common/cnxk/roc_nix_queue.c:
Use plt_ symbols instead of rte_ API in cnxk base driver
### [PATCH] common/cnxk: add support for SQ resize
Warning in drivers/common/cnxk/roc_nix_queue.c:
Use plt_ symbols instead of rte_ API in cnxk base driver
>
^ permalink raw reply
* Re: [PPC] Boot problems after the pci-v6.18-changes
From: Manivannan Sadhasivam @ 2025-10-15 6:41 UTC (permalink / raw)
To: Christian Zigotzky
Cc: Lukas Wunner, Manivannan Sadhasivam, Ilpo Järvinen,
Bjorn Helgaas, linux-pci, mad skateman, R.T.Dickinson,
Christian Zigotzky, linuxppc-dev, hypexed, Darren Stevens,
debian-powerpc
In-Reply-To: <00fe408b-db39-4a9f-b996-0fad73724759@xenosoft.de>
On Tue, Oct 14, 2025 at 06:55:07AM +0200, Christian Zigotzky wrote:
> On 13 October 2025 at 05:58 pm, Manivannan Sadhasivam wrote:
> > Either the Root Port could be triggering these AER messages due to ASPM
> issue or
> > due to the endpoint connected downstream.
> >
> > If possible, please share the whole dmesg log instead of the snippet so
> that we
> > can be sure from where the AER messages are coming from.
> >
> > You can also add the below quirk and check:
> >
> > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FSL, 0x0451,
> quirk_disable_aspm_all);
> >
> > But it would be better to get the whole dmesg.
> >
> > - Mani
>
> Hello Mani,
>
> Thanks for your help.
>
> The kernel doesn't compile with PCI_VENDOR_ID_FSL but it compiles with
> PCI_VENDOR_ID_FREESCALE.
>
> I tried it with the following patch:
>
> diff -rupN a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> --- a/drivers/pci/quirks.c 2025-10-12 22:42:36.000000000 +0200
> +++ b/drivers/pci/quirks.c 2025-10-13 17:59:51.473097708 +0200
> @@ -2525,6 +2525,16 @@ static void quirk_disable_aspm_l0s_l1(st
> */
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080,
> quirk_disable_aspm_l0s_l1);
>
> +
> +static void quirk_disable_aspm_all(struct pci_dev *dev)
> +{
> + pci_info(dev, "Disabling ASPM\n");
> + pci_disable_link_state(dev, PCIE_LINK_STATE_ALL);
> +}
> +
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
> quirk_disable_aspm_all);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
> quirk_disable_aspm_all);
> +
> /*
> * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
> * Link bit cleared after starting the link retrain process to allow this
>
> ---
>
> Unfortunately it doesn't solve the issue with pcieport 0001:00:00.0.
>
That's unfortunate indeed. Could you please share the 'sudo lspci -vv' output?
That will allow us to see the topology and AER status.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply
* Re: [Buildroot] [PATCH 07/14] package/python-websockets: bump version to 15.0.1
From: Peter Korsgaard @ 2025-10-15 6:40 UTC (permalink / raw)
To: Bernd Kuhls
Cc: Joseph Kogut, Christophe Vu-Brugier, James Hilliard,
Vinicius Tinti, buildroot
In-Reply-To: <20251014185113.3583315-7-bernd@kuhls.net>
>>>>> "Bernd" == Bernd Kuhls <bernd@kuhls.net> writes:
> Signed-off-by: Bernd Kuhls <bernd@kuhls.net>
Committed, thanks.
--
Bye, Peter Korsgaard
_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot
^ permalink raw reply
* [PATCH] uio: uio_fsl_elbc_gpcm:: Add null pointer check to uio_fsl_elbc_gpcm_probe
From: Li Qiang @ 2025-10-15 6:40 UTC (permalink / raw)
To: gregkh, alexandru.ardelean; +Cc: linux-kernel, Li Qiang
devm_kasprintf() returns a pointer to dynamically allocated memory
which can be NULL upon failure.
Fixes: d57801c45f53e ("uio: uio_fsl_elbc_gpcm: use device-managed allocators")
Signed-off-by: Li Qiang <liqiang01@kylinos.cn>
---
drivers/uio/uio_fsl_elbc_gpcm.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/uio/uio_fsl_elbc_gpcm.c b/drivers/uio/uio_fsl_elbc_gpcm.c
index 81454c3e2484..338dd2aaabc8 100644
--- a/drivers/uio/uio_fsl_elbc_gpcm.c
+++ b/drivers/uio/uio_fsl_elbc_gpcm.c
@@ -384,6 +384,11 @@ static int uio_fsl_elbc_gpcm_probe(struct platform_device *pdev)
/* set all UIO data */
info->mem[0].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%pOFn", node);
+ if (!info->mem[0].name) {
+ ret = -ENODEV;
+ goto out_err3;
+ }
+
info->mem[0].addr = res.start;
info->mem[0].size = resource_size(&res);
info->mem[0].memtype = UIO_MEM_PHYS;
@@ -423,6 +428,8 @@ static int uio_fsl_elbc_gpcm_probe(struct platform_device *pdev)
out_err2:
if (priv->shutdown)
priv->shutdown(info, true);
+
+out_err3:
iounmap(info->mem[0].internal_addr);
return ret;
}
--
2.25.1
^ permalink raw reply related
* [PATCH v2/resend 0/8] dce, riscv: Unused syscall trimming with PUSHSECTION and conditional KEEP()
From: Yuan Tan @ 2025-10-15 6:38 UTC (permalink / raw)
To: arnd, masahiroy, nathan, palmer, linux-kbuild, linux-riscv
Cc: linux-arch, linux-kernel, i, tanyuan, falcon, ronbogo,
z1652074432, lx24
In-Reply-To: <cover.1760463245.git.tanyuan@tinylab.org>
Hi all,
Sorry for the noise — it looks like my mail provider rewrote the Message-ID
of the cover letter, which broke the thread. I'm resending the cover letter
to make the series appear correctly threaded on lore.
This series aims to introduce syscall trimming support based on dead code
and data elimination (DCE). This can reduce the final image size, which is
particularly useful for embedded devices, while also reducing the attack
surface. It might further benefit specialized scenarios such as unikernels
or LTO builds, and could potentially help shrink the instruction cache
footprint.
Besides that, this series also introduces a new PUSHSECTION macro. This
wrapper allows sections created by .pushsection to have a proper reference
relationship with their callers, so that --gc-sections can safely work
without requiring unconditional KEEP() entries in linker scripts.
Since the new syscalltbl.sh infrastructure has been merged, I think it’s a
good time to push this patchsetTODO? forward.
Patch 1–3 introduce the infrastructure for TRIM_UNUSED_SYSCALLS, mainly
allowing syscalltbl.sh to decide which syscalls to keep according to
USED_SYSCALLS.
Patch 4 enables TRIM_UNUSED_SYSCALLS for the RISC-V architecture. With
syscalltbl.sh now available, this feature should be applicable to all
architectures that support LD_DEAD_CODE_DATA_ELIMINATION and use
syscalltbl.sh, but let’s focus on RISC-V first.
Patch 5–8 address the dependency inversion problem caused by sections
created with .pushsection that are forcibly retained by KEEP() in linker
scripts.
Here is an example to illustrate the problem:
void fun2(void);
void fun1(void) {
asm volatile (
".pushsection .text.pushed,\"ax\"\n\t" "call fun2\n\t"
".popsection\n\t"
);
}
If fun1() is used, .text.fun1 is kept alive, but .text.pushed has no
reference to .text.fun1, so --gc-sections may incorrectly discard
.text.pushed. To avoid this, the kernel traditionally wraps such sections
with KEEP() in the linker script. However, KEEP() introduces a dependency
inversion: if fun1() and fun2() are unused, .text.fun1, .text.fun2 and
.text.pushed should be removed, but KEEP() forces .text.pushed to stay,
which even keeps .text.fun2. As a result, sections that should be
eliminated are retained unnecessarily.
In Linux, sections such as ex_table, jump_table, bug_table, and alternative
are created by .pushsection and suffer from this issue. They prevent some
syscalls from being trimmed.
Ideally, .text.fun1 and .text.pushed should share the same fate: if fun1()
is not referenced, .text.pushed should be discarded as well. To achieve
this, we can establish a relocation with a directive between the caller and
the section created by .pushsection:
.section .text.fun1,"ax"
.reloc ., BFD_RELOC_NONE, pushedlabel
.pushsection .text.pushed,"ax" pushedlabel:
call fun2
.popsection
Based on this idea, we introduce the PUSHSECTION macro. This macro emits a
relocation directive and a new label automatically, while remaining fully
compatible with all existing .pushsection parameters. With this macro, all
current uses of .pushsection (and even .section) in the kernel can be
replaced, significantly reducing the number of KEEP() in linker scripts and
enabling --gc-sections to work more effectively.
Without PUSHSECTION, there are 56 syscalls that cannot be trimmed in
defconfig and TRIM_UNUSED_SYSCALLS enabled. With PUSHSECTION, all syscalls
can now be properly trimmed.
We have tested enabling TRIM_UNUSED_SYSCALLS while keeping all syscalls
listed in USED_SYSCALLS and successfully booted Ubuntu on a configuration
based on v6.18-rc1 defconfig. The detailed configuration is provided in
[1]. This confirms that the trimming mechanism functions correctly under a
standard kernel setup.
The vmlinux size with tinyconfig is as follows:
| | syscall remain | vmlinux size | vmlinux after strip |
| ------------------------------- | -------------- | -------------- | ------------------- |
| enable DCE | 188 | 1437008 | 915160 |
| enable DCE and syscall trimming | 3 | 1263528 (-12%) | 800472 (-13%) |
Changes in v2:
- Rebased on the unified syscalltbl.sh infrastructure for syscall trimming.
USED_SYSCALLS now accepts only syscall names to avoid confusion, whereas v1
also allowed entry point symbols.
- Uses the .reloc directive to establish dependencies.
Compared with previous proposals using SHF_LINK_ORDER or SHF_GROUP, this
approach provides a generic, parameter-compatible macro for all
.pushsection usages without side effects.
Previous versions:
- RFC: https://lore.kernel.org/lkml/cover.1676594211.git.falcon@tinylab.org/
- v1 part 1: https://lore.kernel.org/lkml/cover.1695679700.git.falcon@tinylab.org/
- v1 part 2: https://lore.kernel.org/lkml/cover.1699025537.git.tanyuan@tinylab.org/
Links:
[1] https://pastebin.com/St51bk2K
Yuan Tan (4):
kconfig: add CONFIG_PUSHSECTION_WITH_RELOC for relocation support
compiler.h: introduce PUSHSECTION macro to establish proper references
vmlinux.lds.h: support conditional KEEP() in linker script
riscv: use PUSHSECTION in ex_table, jump_table, bug_table and
alternatives
Yuhang Zheng (4):
init/Kconfig: add CONFIG_TRIM_UNUSED_SYSCALLS and related options
scripts/syscalltbl.sh: add optional --used-syscalls argument for
syscall trimming
scripts/Makefile.asm-headers: pass USED_SYSCALLS to syscalltbl.sh
riscv: enable HAVE_TRIM_UNUSED_SYSCALLS when toolchain supports DCE
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/alternative-macros.h | 8 ++--
arch/riscv/include/asm/asm-extable.h | 10 +++--
arch/riscv/include/asm/bug.h | 2 +-
arch/riscv/include/asm/jump_label.h | 3 +-
arch/riscv/kernel/vmlinux.lds.S | 9 +++-
include/asm-generic/vmlinux.lds.h | 12 ++++-
include/linux/compiler.h | 43 +++++++++++++++++-
include/linux/compiler_types.h | 8 ++--
init/Kconfig | 49 +++++++++++++++++++++
scripts/Makefile.asm-headers | 4 ++
scripts/syscalltbl.sh | 19 +++++++-
12 files changed, 150 insertions(+), 18 deletions(-)
base-commit: 3a8660878839faadb4f1a6dd72c3179c1df56787
prerequisite-patch-id: 7af3175326df94637f04a050dee7356416eb1edd
--
2.43.0
^ permalink raw reply
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