From: Keir Fraser <keir@xensource.com>
To: Kaushik Barde <Kaushik_Barde@Phoenix.com>,
Christoph Egger <Christoph.Egger@amd.com>,
xen-devel@lists.xensource.com
Subject: Re: NMI delivery not correctly working
Date: Wed, 25 Jul 2007 07:55:11 +0100 [thread overview]
Message-ID: <C2CCB25F.B62A%keir@xensource.com> (raw)
In-Reply-To: <0EF82802ABAA22479BC1CE8E2F60E8C3017E79E5@scl-exch2k3.phoenix.com>
On 25/7/07 07:43, "Kaushik Barde" <Kaushik_Barde@Phoenix.com> wrote:
> Thanks.
>
>>>
> via masking of maskable interrupts
> <<
> What I'd meant there was all other interrupts are masked (by processor during
> NMI handling) except for NMI.
NMIs *are* masked by x86 CPU from when an NMI is delivered to the CPU until
after that CPU next executes an IRET. The CPU has a special NMI mask for
this purpose (not directly architecturally visible). It's unrelated to
EFLAGS.IF.
-- Keir
next prev parent reply other threads:[~2007-07-25 6:55 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-07-24 15:47 NMI delivery not correctly working Christoph Egger
2007-07-24 17:07 ` Keir Fraser
2007-07-24 18:26 ` Kaushik Barde
2007-07-25 6:22 ` Keir Fraser
2007-07-25 6:43 ` Kaushik Barde
2007-07-25 6:55 ` Keir Fraser [this message]
2007-07-25 6:48 ` Christoph Egger
2007-07-25 6:57 ` Keir Fraser
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