* [PATCH 1/4] arm64: tegra: Move AHUB ports to SoC DTSI
2024-02-07 12:05 [PATCH 0/4] Add audio support for Jetson Orin NX and Jetson Sheetal .
@ 2024-02-07 12:05 ` Sheetal .
2024-02-07 12:05 ` [PATCH 2/4] arm64: tegra: Define missing IO ports Sheetal .
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Sheetal . @ 2024-02-07 12:05 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, devicetree, linux-kernel
Cc: thierry.reding, linux-tegra, spujar, jonathanh, mkumard, sheetal
From: sheetal <sheetal@nvidia.com>
AHUB and its child nodes ports are part of platform DTS and with new
platform support these entries need to be defined again.
As they are common across the platforms, moving them to SoC
DTSI to avoid code duplicacy.
AHUB HW accelerators are used for audio processing and typically all of
these are made available. Platforms can enable all of these just by
enabling the AHUB parent device. However IO interfaces (which are also
children of AHUB) are selectively enabled based on what the platform
actually exposes for interaction with external world.
Signed-off-by: sheetal <sheetal@nvidia.com>
---
.../arm64/boot/dts/nvidia/tegra234-p3701.dtsi | 1948 -----------------
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 1925 +++++++++++++++-
2 files changed, 1899 insertions(+), 1974 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi
index db6ef711674a..835288a44cdf 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi
@@ -12,1970 +12,22 @@ ahub@2900800 {
i2s@2901000 {
status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- i2s1_cif: endpoint {
- remote-endpoint = <&xbar_i2s1>;
- };
- };
-
- i2s1_port: port@1 {
- reg = <1>;
-
- i2s1_dap: endpoint {
- dai-format = "i2s";
- /* placeholder for external codec */
- };
- };
- };
};
i2s@2901100 {
status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- i2s2_cif: endpoint {
- remote-endpoint = <&xbar_i2s2>;
- };
- };
-
- i2s2_port: port@1 {
- reg = <1>;
-
- i2s2_dap: endpoint {
- dai-format = "i2s";
- /* placeholder for external codec */
- };
- };
- };
};
i2s@2901300 {
status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- i2s4_cif: endpoint {
- remote-endpoint = <&xbar_i2s4>;
- };
- };
-
- i2s4_port: port@1 {
- reg = <1>;
-
- i2s4_dap: endpoint {
- dai-format = "i2s";
- /* placeholder for external codec */
- };
- };
- };
};
i2s@2901500 {
status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- i2s6_cif: endpoint {
- remote-endpoint = <&xbar_i2s6>;
- };
- };
-
- i2s6_port: port@1 {
- reg = <1>;
-
- i2s6_dap: endpoint {
- dai-format = "i2s";
- /* placeholder for external codec */
- };
- };
- };
- };
-
- sfc@2902000 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sfc1_cif_in: endpoint {
- remote-endpoint = <&xbar_sfc1_in>;
- };
- };
-
- sfc1_out_port: port@1 {
- reg = <1>;
-
- sfc1_cif_out: endpoint {
- remote-endpoint = <&xbar_sfc1_out>;
- };
- };
- };
- };
-
- sfc@2902200 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sfc2_cif_in: endpoint {
- remote-endpoint = <&xbar_sfc2_in>;
- };
- };
-
- sfc2_out_port: port@1 {
- reg = <1>;
-
- sfc2_cif_out: endpoint {
- remote-endpoint = <&xbar_sfc2_out>;
- };
- };
- };
- };
-
- sfc@2902400 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sfc3_cif_in: endpoint {
- remote-endpoint = <&xbar_sfc3_in>;
- };
- };
-
- sfc3_out_port: port@1 {
- reg = <1>;
-
- sfc3_cif_out: endpoint {
- remote-endpoint = <&xbar_sfc3_out>;
- };
- };
- };
- };
-
- sfc@2902600 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- sfc4_cif_in: endpoint {
- remote-endpoint = <&xbar_sfc4_in>;
- };
- };
-
- sfc4_out_port: port@1 {
- reg = <1>;
-
- sfc4_cif_out: endpoint {
- remote-endpoint = <&xbar_sfc4_out>;
- };
- };
- };
- };
-
- amx@2903000 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- amx1_in1: endpoint {
- remote-endpoint = <&xbar_amx1_in1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- amx1_in2: endpoint {
- remote-endpoint = <&xbar_amx1_in2>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- amx1_in3: endpoint {
- remote-endpoint = <&xbar_amx1_in3>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- amx1_in4: endpoint {
- remote-endpoint = <&xbar_amx1_in4>;
- };
- };
-
- amx1_out_port: port@4 {
- reg = <4>;
-
- amx1_out: endpoint {
- remote-endpoint = <&xbar_amx1_out>;
- };
- };
- };
- };
-
- amx@2903100 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- amx2_in1: endpoint {
- remote-endpoint = <&xbar_amx2_in1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- amx2_in2: endpoint {
- remote-endpoint = <&xbar_amx2_in2>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- amx2_in3: endpoint {
- remote-endpoint = <&xbar_amx2_in3>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- amx2_in4: endpoint {
- remote-endpoint = <&xbar_amx2_in4>;
- };
- };
-
- amx2_out_port: port@4 {
- reg = <4>;
-
- amx2_out: endpoint {
- remote-endpoint = <&xbar_amx2_out>;
- };
- };
- };
- };
-
- amx@2903200 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- amx3_in1: endpoint {
- remote-endpoint = <&xbar_amx3_in1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- amx3_in2: endpoint {
- remote-endpoint = <&xbar_amx3_in2>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- amx3_in3: endpoint {
- remote-endpoint = <&xbar_amx3_in3>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- amx3_in4: endpoint {
- remote-endpoint = <&xbar_amx3_in4>;
- };
- };
-
- amx3_out_port: port@4 {
- reg = <4>;
-
- amx3_out: endpoint {
- remote-endpoint = <&xbar_amx3_out>;
- };
- };
- };
- };
-
- amx@2903300 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- amx4_in1: endpoint {
- remote-endpoint = <&xbar_amx4_in1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- amx4_in2: endpoint {
- remote-endpoint = <&xbar_amx4_in2>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- amx4_in3: endpoint {
- remote-endpoint = <&xbar_amx4_in3>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- amx4_in4: endpoint {
- remote-endpoint = <&xbar_amx4_in4>;
- };
- };
-
- amx4_out_port: port@4 {
- reg = <4>;
-
- amx4_out: endpoint {
- remote-endpoint = <&xbar_amx4_out>;
- };
- };
- };
- };
-
- adx@2903800 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- adx1_in: endpoint {
- remote-endpoint = <&xbar_adx1_in>;
- };
- };
-
- adx1_out1_port: port@1 {
- reg = <1>;
-
- adx1_out1: endpoint {
- remote-endpoint = <&xbar_adx1_out1>;
- };
- };
-
- adx1_out2_port: port@2 {
- reg = <2>;
-
- adx1_out2: endpoint {
- remote-endpoint = <&xbar_adx1_out2>;
- };
- };
-
- adx1_out3_port: port@3 {
- reg = <3>;
-
- adx1_out3: endpoint {
- remote-endpoint = <&xbar_adx1_out3>;
- };
- };
-
- adx1_out4_port: port@4 {
- reg = <4>;
-
- adx1_out4: endpoint {
- remote-endpoint = <&xbar_adx1_out4>;
- };
- };
- };
- };
-
- adx@2903900 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- adx2_in: endpoint {
- remote-endpoint = <&xbar_adx2_in>;
- };
- };
-
- adx2_out1_port: port@1 {
- reg = <1>;
-
- adx2_out1: endpoint {
- remote-endpoint = <&xbar_adx2_out1>;
- };
- };
-
- adx2_out2_port: port@2 {
- reg = <2>;
-
- adx2_out2: endpoint {
- remote-endpoint = <&xbar_adx2_out2>;
- };
- };
-
- adx2_out3_port: port@3 {
- reg = <3>;
-
- adx2_out3: endpoint {
- remote-endpoint = <&xbar_adx2_out3>;
- };
- };
-
- adx2_out4_port: port@4 {
- reg = <4>;
-
- adx2_out4: endpoint {
- remote-endpoint = <&xbar_adx2_out4>;
- };
- };
- };
- };
-
- adx@2903a00 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- adx3_in: endpoint {
- remote-endpoint = <&xbar_adx3_in>;
- };
- };
-
- adx3_out1_port: port@1 {
- reg = <1>;
-
- adx3_out1: endpoint {
- remote-endpoint = <&xbar_adx3_out1>;
- };
- };
-
- adx3_out2_port: port@2 {
- reg = <2>;
-
- adx3_out2: endpoint {
- remote-endpoint = <&xbar_adx3_out2>;
- };
- };
-
- adx3_out3_port: port@3 {
- reg = <3>;
-
- adx3_out3: endpoint {
- remote-endpoint = <&xbar_adx3_out3>;
- };
- };
-
- adx3_out4_port: port@4 {
- reg = <4>;
-
- adx3_out4: endpoint {
- remote-endpoint = <&xbar_adx3_out4>;
- };
- };
- };
- };
-
- adx@2903b00 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- adx4_in: endpoint {
- remote-endpoint = <&xbar_adx4_in>;
- };
- };
-
- adx4_out1_port: port@1 {
- reg = <1>;
-
- adx4_out1: endpoint {
- remote-endpoint = <&xbar_adx4_out1>;
- };
- };
-
- adx4_out2_port: port@2 {
- reg = <2>;
-
- adx4_out2: endpoint {
- remote-endpoint = <&xbar_adx4_out2>;
- };
- };
-
- adx4_out3_port: port@3 {
- reg = <3>;
-
- adx4_out3: endpoint {
- remote-endpoint = <&xbar_adx4_out3>;
- };
- };
-
- adx4_out4_port: port@4 {
- reg = <4>;
-
- adx4_out4: endpoint {
- remote-endpoint = <&xbar_adx4_out4>;
- };
- };
- };
};
dmic@2904200 {
status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- dmic3_cif: endpoint {
- remote-endpoint = <&xbar_dmic3>;
- };
- };
-
- dmic3_port: port@1 {
- reg = <1>;
-
- dmic3_dap: endpoint {
- /* placeholder for external codec */
- };
- };
- };
- };
-
- processing-engine@2908000 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0x0>;
-
- ope1_cif_in_ep: endpoint {
- remote-endpoint = <&xbar_ope1_in_ep>;
- };
- };
-
- ope1_out_port: port@1 {
- reg = <0x1>;
-
- ope1_cif_out_ep: endpoint {
- remote-endpoint = <&xbar_ope1_out_ep>;
- };
- };
- };
- };
-
- mvc@290a000 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- mvc1_cif_in: endpoint {
- remote-endpoint = <&xbar_mvc1_in>;
- };
- };
-
- mvc1_out_port: port@1 {
- reg = <1>;
-
- mvc1_cif_out: endpoint {
- remote-endpoint = <&xbar_mvc1_out>;
- };
- };
- };
- };
-
- mvc@290a200 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- mvc2_cif_in: endpoint {
- remote-endpoint = <&xbar_mvc2_in>;
- };
- };
-
- mvc2_out_port: port@1 {
- reg = <1>;
-
- mvc2_cif_out: endpoint {
- remote-endpoint = <&xbar_mvc2_out>;
- };
- };
- };
- };
-
- amixer@290bb00 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0x0>;
-
- mix_in1: endpoint {
- remote-endpoint = <&xbar_mix_in1>;
- };
- };
-
- port@1 {
- reg = <0x1>;
-
- mix_in2: endpoint {
- remote-endpoint = <&xbar_mix_in2>;
- };
- };
-
- port@2 {
- reg = <0x2>;
-
- mix_in3: endpoint {
- remote-endpoint = <&xbar_mix_in3>;
- };
- };
-
- port@3 {
- reg = <0x3>;
-
- mix_in4: endpoint {
- remote-endpoint = <&xbar_mix_in4>;
- };
- };
-
- port@4 {
- reg = <0x4>;
-
- mix_in5: endpoint {
- remote-endpoint = <&xbar_mix_in5>;
- };
- };
-
- port@5 {
- reg = <0x5>;
-
- mix_in6: endpoint {
- remote-endpoint = <&xbar_mix_in6>;
- };
- };
-
- port@6 {
- reg = <0x6>;
-
- mix_in7: endpoint {
- remote-endpoint = <&xbar_mix_in7>;
- };
- };
-
- port@7 {
- reg = <0x7>;
-
- mix_in8: endpoint {
- remote-endpoint = <&xbar_mix_in8>;
- };
- };
-
- port@8 {
- reg = <0x8>;
-
- mix_in9: endpoint {
- remote-endpoint = <&xbar_mix_in9>;
- };
- };
-
- port@9 {
- reg = <0x9>;
-
- mix_in10: endpoint {
- remote-endpoint = <&xbar_mix_in10>;
- };
- };
-
- mix_out1_port: port@a {
- reg = <0xa>;
-
- mix_out1: endpoint {
- remote-endpoint = <&xbar_mix_out1>;
- };
- };
-
- mix_out2_port: port@b {
- reg = <0xb>;
-
- mix_out2: endpoint {
- remote-endpoint = <&xbar_mix_out2>;
- };
- };
-
- mix_out3_port: port@c {
- reg = <0xc>;
-
- mix_out3: endpoint {
- remote-endpoint = <&xbar_mix_out3>;
- };
- };
-
- mix_out4_port: port@d {
- reg = <0xd>;
-
- mix_out4: endpoint {
- remote-endpoint = <&xbar_mix_out4>;
- };
- };
-
- mix_out5_port: port@e {
- reg = <0xe>;
-
- mix_out5: endpoint {
- remote-endpoint = <&xbar_mix_out5>;
- };
- };
- };
- };
-
- admaif@290f000 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- admaif0_port: port@0 {
- reg = <0x0>;
-
- admaif0: endpoint {
- remote-endpoint = <&xbar_admaif0>;
- };
- };
-
- admaif1_port: port@1 {
- reg = <0x1>;
-
- admaif1: endpoint {
- remote-endpoint = <&xbar_admaif1>;
- };
- };
-
- admaif2_port: port@2 {
- reg = <0x2>;
-
- admaif2: endpoint {
- remote-endpoint = <&xbar_admaif2>;
- };
- };
-
- admaif3_port: port@3 {
- reg = <0x3>;
-
- admaif3: endpoint {
- remote-endpoint = <&xbar_admaif3>;
- };
- };
-
- admaif4_port: port@4 {
- reg = <0x4>;
-
- admaif4: endpoint {
- remote-endpoint = <&xbar_admaif4>;
- };
- };
-
- admaif5_port: port@5 {
- reg = <0x5>;
-
- admaif5: endpoint {
- remote-endpoint = <&xbar_admaif5>;
- };
- };
-
- admaif6_port: port@6 {
- reg = <0x6>;
-
- admaif6: endpoint {
- remote-endpoint = <&xbar_admaif6>;
- };
- };
-
- admaif7_port: port@7 {
- reg = <0x7>;
-
- admaif7: endpoint {
- remote-endpoint = <&xbar_admaif7>;
- };
- };
-
- admaif8_port: port@8 {
- reg = <0x8>;
-
- admaif8: endpoint {
- remote-endpoint = <&xbar_admaif8>;
- };
- };
-
- admaif9_port: port@9 {
- reg = <0x9>;
-
- admaif9: endpoint {
- remote-endpoint = <&xbar_admaif9>;
- };
- };
-
- admaif10_port: port@a {
- reg = <0xa>;
-
- admaif10: endpoint {
- remote-endpoint = <&xbar_admaif10>;
- };
- };
-
- admaif11_port: port@b {
- reg = <0xb>;
-
- admaif11: endpoint {
- remote-endpoint = <&xbar_admaif11>;
- };
- };
-
- admaif12_port: port@c {
- reg = <0xc>;
-
- admaif12: endpoint {
- remote-endpoint = <&xbar_admaif12>;
- };
- };
-
- admaif13_port: port@d {
- reg = <0xd>;
-
- admaif13: endpoint {
- remote-endpoint = <&xbar_admaif13>;
- };
- };
-
- admaif14_port: port@e {
- reg = <0xe>;
-
- admaif14: endpoint {
- remote-endpoint = <&xbar_admaif14>;
- };
- };
-
- admaif15_port: port@f {
- reg = <0xf>;
-
- admaif15: endpoint {
- remote-endpoint = <&xbar_admaif15>;
- };
- };
-
- admaif16_port: port@10 {
- reg = <0x10>;
-
- admaif16: endpoint {
- remote-endpoint = <&xbar_admaif16>;
- };
- };
-
- admaif17_port: port@11 {
- reg = <0x11>;
-
- admaif17: endpoint {
- remote-endpoint = <&xbar_admaif17>;
- };
- };
-
- admaif18_port: port@12 {
- reg = <0x12>;
-
- admaif18: endpoint {
- remote-endpoint = <&xbar_admaif18>;
- };
- };
-
- admaif19_port: port@13 {
- reg = <0x13>;
-
- admaif19: endpoint {
- remote-endpoint = <&xbar_admaif19>;
- };
- };
- };
- };
-
- asrc@2910000 {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0x0>;
-
- asrc_in1_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in1_ep>;
- };
- };
-
- port@1 {
- reg = <0x1>;
-
- asrc_in2_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in2_ep>;
- };
- };
-
- port@2 {
- reg = <0x2>;
-
- asrc_in3_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in3_ep>;
- };
- };
-
- port@3 {
- reg = <0x3>;
-
- asrc_in4_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in4_ep>;
- };
- };
-
- port@4 {
- reg = <0x4>;
-
- asrc_in5_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in5_ep>;
- };
- };
-
- port@5 {
- reg = <0x5>;
-
- asrc_in6_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in6_ep>;
- };
- };
-
- port@6 {
- reg = <0x6>;
-
- asrc_in7_ep: endpoint {
- remote-endpoint = <&xbar_asrc_in7_ep>;
- };
- };
-
- asrc_out1_port: port@7 {
- reg = <0x7>;
-
- asrc_out1_ep: endpoint {
- remote-endpoint = <&xbar_asrc_out1_ep>;
- };
- };
-
- asrc_out2_port: port@8 {
- reg = <0x8>;
-
- asrc_out2_ep: endpoint {
- remote-endpoint = <&xbar_asrc_out2_ep>;
- };
- };
-
- asrc_out3_port: port@9 {
- reg = <0x9>;
-
- asrc_out3_ep: endpoint {
- remote-endpoint = <&xbar_asrc_out3_ep>;
- };
- };
-
- asrc_out4_port: port@a {
- reg = <0xa>;
-
- asrc_out4_ep: endpoint {
- remote-endpoint = <&xbar_asrc_out4_ep>;
- };
- };
-
- asrc_out5_port: port@b {
- reg = <0xb>;
-
- asrc_out5_ep: endpoint {
- remote-endpoint = <&xbar_asrc_out5_ep>;
- };
- };
-
- asrc_out6_port: port@c {
- reg = <0xc>;
-
- asrc_out6_ep: endpoint {
- remote-endpoint = <&xbar_asrc_out6_ep>;
- };
- };
- };
- };
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0x0>;
-
- xbar_admaif0: endpoint {
- remote-endpoint = <&admaif0>;
- };
- };
-
- port@1 {
- reg = <0x1>;
-
- xbar_admaif1: endpoint {
- remote-endpoint = <&admaif1>;
- };
- };
-
- port@2 {
- reg = <0x2>;
-
- xbar_admaif2: endpoint {
- remote-endpoint = <&admaif2>;
- };
- };
-
- port@3 {
- reg = <0x3>;
-
- xbar_admaif3: endpoint {
- remote-endpoint = <&admaif3>;
- };
- };
-
- port@4 {
- reg = <0x4>;
-
- xbar_admaif4: endpoint {
- remote-endpoint = <&admaif4>;
- };
- };
-
- port@5 {
- reg = <0x5>;
-
- xbar_admaif5: endpoint {
- remote-endpoint = <&admaif5>;
- };
- };
-
- port@6 {
- reg = <0x6>;
-
- xbar_admaif6: endpoint {
- remote-endpoint = <&admaif6>;
- };
- };
-
- port@7 {
- reg = <0x7>;
-
- xbar_admaif7: endpoint {
- remote-endpoint = <&admaif7>;
- };
- };
-
- port@8 {
- reg = <0x8>;
-
- xbar_admaif8: endpoint {
- remote-endpoint = <&admaif8>;
- };
- };
-
- port@9 {
- reg = <0x9>;
-
- xbar_admaif9: endpoint {
- remote-endpoint = <&admaif9>;
- };
- };
-
- port@a {
- reg = <0xa>;
-
- xbar_admaif10: endpoint {
- remote-endpoint = <&admaif10>;
- };
- };
-
- port@b {
- reg = <0xb>;
-
- xbar_admaif11: endpoint {
- remote-endpoint = <&admaif11>;
- };
- };
-
- port@c {
- reg = <0xc>;
-
- xbar_admaif12: endpoint {
- remote-endpoint = <&admaif12>;
- };
- };
-
- port@d {
- reg = <0xd>;
-
- xbar_admaif13: endpoint {
- remote-endpoint = <&admaif13>;
- };
- };
-
- port@e {
- reg = <0xe>;
-
- xbar_admaif14: endpoint {
- remote-endpoint = <&admaif14>;
- };
- };
-
- port@f {
- reg = <0xf>;
-
- xbar_admaif15: endpoint {
- remote-endpoint = <&admaif15>;
- };
- };
-
- port@10 {
- reg = <0x10>;
-
- xbar_admaif16: endpoint {
- remote-endpoint = <&admaif16>;
- };
- };
-
- port@11 {
- reg = <0x11>;
-
- xbar_admaif17: endpoint {
- remote-endpoint = <&admaif17>;
- };
- };
-
- port@12 {
- reg = <0x12>;
-
- xbar_admaif18: endpoint {
- remote-endpoint = <&admaif18>;
- };
- };
-
- port@13 {
- reg = <0x13>;
-
- xbar_admaif19: endpoint {
- remote-endpoint = <&admaif19>;
- };
- };
-
- xbar_i2s1_port: port@14 {
- reg = <0x14>;
-
- xbar_i2s1: endpoint {
- remote-endpoint = <&i2s1_cif>;
- };
- };
-
- xbar_i2s2_port: port@15 {
- reg = <0x15>;
-
- xbar_i2s2: endpoint {
- remote-endpoint = <&i2s2_cif>;
- };
- };
-
- xbar_i2s4_port: port@17 {
- reg = <0x17>;
-
- xbar_i2s4: endpoint {
- remote-endpoint = <&i2s4_cif>;
- };
- };
-
- xbar_i2s6_port: port@19 {
- reg = <0x19>;
-
- xbar_i2s6: endpoint {
- remote-endpoint = <&i2s6_cif>;
- };
- };
-
- xbar_dmic3_port: port@1c {
- reg = <0x1c>;
-
- xbar_dmic3: endpoint {
- remote-endpoint = <&dmic3_cif>;
- };
- };
-
- xbar_sfc1_in_port: port@20 {
- reg = <0x20>;
-
- xbar_sfc1_in: endpoint {
- remote-endpoint = <&sfc1_cif_in>;
- };
- };
-
- port@21 {
- reg = <0x21>;
-
- xbar_sfc1_out: endpoint {
- remote-endpoint = <&sfc1_cif_out>;
- };
- };
-
- xbar_sfc2_in_port: port@22 {
- reg = <0x22>;
-
- xbar_sfc2_in: endpoint {
- remote-endpoint = <&sfc2_cif_in>;
- };
- };
-
- port@23 {
- reg = <0x23>;
-
- xbar_sfc2_out: endpoint {
- remote-endpoint = <&sfc2_cif_out>;
- };
- };
-
- xbar_sfc3_in_port: port@24 {
- reg = <0x24>;
-
- xbar_sfc3_in: endpoint {
- remote-endpoint = <&sfc3_cif_in>;
- };
- };
-
- port@25 {
- reg = <0x25>;
-
- xbar_sfc3_out: endpoint {
- remote-endpoint = <&sfc3_cif_out>;
- };
- };
-
- xbar_sfc4_in_port: port@26 {
- reg = <0x26>;
-
- xbar_sfc4_in: endpoint {
- remote-endpoint = <&sfc4_cif_in>;
- };
- };
-
- port@27 {
- reg = <0x27>;
-
- xbar_sfc4_out: endpoint {
- remote-endpoint = <&sfc4_cif_out>;
- };
- };
-
- xbar_mvc1_in_port: port@28 {
- reg = <0x28>;
-
- xbar_mvc1_in: endpoint {
- remote-endpoint = <&mvc1_cif_in>;
- };
- };
-
- port@29 {
- reg = <0x29>;
-
- xbar_mvc1_out: endpoint {
- remote-endpoint = <&mvc1_cif_out>;
- };
- };
-
- xbar_mvc2_in_port: port@2a {
- reg = <0x2a>;
-
- xbar_mvc2_in: endpoint {
- remote-endpoint = <&mvc2_cif_in>;
- };
- };
-
- port@2b {
- reg = <0x2b>;
-
- xbar_mvc2_out: endpoint {
- remote-endpoint = <&mvc2_cif_out>;
- };
- };
-
- xbar_amx1_in1_port: port@2c {
- reg = <0x2c>;
-
- xbar_amx1_in1: endpoint {
- remote-endpoint = <&amx1_in1>;
- };
- };
-
- xbar_amx1_in2_port: port@2d {
- reg = <0x2d>;
-
- xbar_amx1_in2: endpoint {
- remote-endpoint = <&amx1_in2>;
- };
- };
-
- xbar_amx1_in3_port: port@2e {
- reg = <0x2e>;
-
- xbar_amx1_in3: endpoint {
- remote-endpoint = <&amx1_in3>;
- };
- };
-
- xbar_amx1_in4_port: port@2f {
- reg = <0x2f>;
-
- xbar_amx1_in4: endpoint {
- remote-endpoint = <&amx1_in4>;
- };
- };
-
- port@30 {
- reg = <0x30>;
-
- xbar_amx1_out: endpoint {
- remote-endpoint = <&amx1_out>;
- };
- };
-
- xbar_amx2_in1_port: port@31 {
- reg = <0x31>;
-
- xbar_amx2_in1: endpoint {
- remote-endpoint = <&amx2_in1>;
- };
- };
-
- xbar_amx2_in2_port: port@32 {
- reg = <0x32>;
-
- xbar_amx2_in2: endpoint {
- remote-endpoint = <&amx2_in2>;
- };
- };
-
- xbar_amx2_in3_port: port@33 {
- reg = <0x33>;
-
- xbar_amx2_in3: endpoint {
- remote-endpoint = <&amx2_in3>;
- };
- };
-
- xbar_amx2_in4_port: port@34 {
- reg = <0x34>;
-
- xbar_amx2_in4: endpoint {
- remote-endpoint = <&amx2_in4>;
- };
- };
-
- port@35 {
- reg = <0x35>;
-
- xbar_amx2_out: endpoint {
- remote-endpoint = <&amx2_out>;
- };
- };
-
- xbar_amx3_in1_port: port@36 {
- reg = <0x36>;
-
- xbar_amx3_in1: endpoint {
- remote-endpoint = <&amx3_in1>;
- };
- };
-
- xbar_amx3_in2_port: port@37 {
- reg = <0x37>;
-
- xbar_amx3_in2: endpoint {
- remote-endpoint = <&amx3_in2>;
- };
- };
-
- xbar_amx3_in3_port: port@38 {
- reg = <0x38>;
-
- xbar_amx3_in3: endpoint {
- remote-endpoint = <&amx3_in3>;
- };
- };
-
- xbar_amx3_in4_port: port@39 {
- reg = <0x39>;
-
- xbar_amx3_in4: endpoint {
- remote-endpoint = <&amx3_in4>;
- };
- };
-
- port@3a {
- reg = <0x3a>;
-
- xbar_amx3_out: endpoint {
- remote-endpoint = <&amx3_out>;
- };
- };
-
- xbar_amx4_in1_port: port@3b {
- reg = <0x3b>;
-
- xbar_amx4_in1: endpoint {
- remote-endpoint = <&amx4_in1>;
- };
- };
-
- xbar_amx4_in2_port: port@3c {
- reg = <0x3c>;
-
- xbar_amx4_in2: endpoint {
- remote-endpoint = <&amx4_in2>;
- };
- };
-
- xbar_amx4_in3_port: port@3d {
- reg = <0x3d>;
-
- xbar_amx4_in3: endpoint {
- remote-endpoint = <&amx4_in3>;
- };
- };
-
- xbar_amx4_in4_port: port@3e {
- reg = <0x3e>;
-
- xbar_amx4_in4: endpoint {
- remote-endpoint = <&amx4_in4>;
- };
- };
-
- port@3f {
- reg = <0x3f>;
-
- xbar_amx4_out: endpoint {
- remote-endpoint = <&amx4_out>;
- };
- };
-
- xbar_adx1_in_port: port@40 {
- reg = <0x40>;
-
- xbar_adx1_in: endpoint {
- remote-endpoint = <&adx1_in>;
- };
- };
-
- port@41 {
- reg = <0x41>;
-
- xbar_adx1_out1: endpoint {
- remote-endpoint = <&adx1_out1>;
- };
- };
-
- port@42 {
- reg = <0x42>;
-
- xbar_adx1_out2: endpoint {
- remote-endpoint = <&adx1_out2>;
- };
- };
-
- port@43 {
- reg = <0x43>;
-
- xbar_adx1_out3: endpoint {
- remote-endpoint = <&adx1_out3>;
- };
- };
-
- port@44 {
- reg = <0x44>;
-
- xbar_adx1_out4: endpoint {
- remote-endpoint = <&adx1_out4>;
- };
- };
-
- xbar_adx2_in_port: port@45 {
- reg = <0x45>;
-
- xbar_adx2_in: endpoint {
- remote-endpoint = <&adx2_in>;
- };
- };
-
- port@46 {
- reg = <0x46>;
-
- xbar_adx2_out1: endpoint {
- remote-endpoint = <&adx2_out1>;
- };
- };
-
- port@47 {
- reg = <0x47>;
-
- xbar_adx2_out2: endpoint {
- remote-endpoint = <&adx2_out2>;
- };
- };
-
- port@48 {
- reg = <0x48>;
-
- xbar_adx2_out3: endpoint {
- remote-endpoint = <&adx2_out3>;
- };
- };
-
- port@49 {
- reg = <0x49>;
-
- xbar_adx2_out4: endpoint {
- remote-endpoint = <&adx2_out4>;
- };
- };
-
- xbar_adx3_in_port: port@4a {
- reg = <0x4a>;
-
- xbar_adx3_in: endpoint {
- remote-endpoint = <&adx3_in>;
- };
- };
-
- port@4b {
- reg = <0x4b>;
-
- xbar_adx3_out1: endpoint {
- remote-endpoint = <&adx3_out1>;
- };
- };
-
- port@4c {
- reg = <0x4c>;
-
- xbar_adx3_out2: endpoint {
- remote-endpoint = <&adx3_out2>;
- };
- };
-
- port@4d {
- reg = <0x4d>;
-
- xbar_adx3_out3: endpoint {
- remote-endpoint = <&adx3_out3>;
- };
- };
-
- port@4e {
- reg = <0x4e>;
-
- xbar_adx3_out4: endpoint {
- remote-endpoint = <&adx3_out4>;
- };
- };
-
- xbar_adx4_in_port: port@4f {
- reg = <0x4f>;
-
- xbar_adx4_in: endpoint {
- remote-endpoint = <&adx4_in>;
- };
- };
-
- port@50 {
- reg = <0x50>;
-
- xbar_adx4_out1: endpoint {
- remote-endpoint = <&adx4_out1>;
- };
- };
-
- port@51 {
- reg = <0x51>;
-
- xbar_adx4_out2: endpoint {
- remote-endpoint = <&adx4_out2>;
- };
- };
-
- port@52 {
- reg = <0x52>;
-
- xbar_adx4_out3: endpoint {
- remote-endpoint = <&adx4_out3>;
- };
- };
-
- port@53 {
- reg = <0x53>;
-
- xbar_adx4_out4: endpoint {
- remote-endpoint = <&adx4_out4>;
- };
- };
-
- xbar_mix_in1_port: port@54 {
- reg = <0x54>;
-
- xbar_mix_in1: endpoint {
- remote-endpoint = <&mix_in1>;
- };
- };
-
- xbar_mix_in2_port: port@55 {
- reg = <0x55>;
-
- xbar_mix_in2: endpoint {
- remote-endpoint = <&mix_in2>;
- };
- };
-
- xbar_mix_in3_port: port@56 {
- reg = <0x56>;
-
- xbar_mix_in3: endpoint {
- remote-endpoint = <&mix_in3>;
- };
- };
-
- xbar_mix_in4_port: port@57 {
- reg = <0x57>;
-
- xbar_mix_in4: endpoint {
- remote-endpoint = <&mix_in4>;
- };
- };
-
- xbar_mix_in5_port: port@58 {
- reg = <0x58>;
-
- xbar_mix_in5: endpoint {
- remote-endpoint = <&mix_in5>;
- };
- };
-
- xbar_mix_in6_port: port@59 {
- reg = <0x59>;
-
- xbar_mix_in6: endpoint {
- remote-endpoint = <&mix_in6>;
- };
- };
-
- xbar_mix_in7_port: port@5a {
- reg = <0x5a>;
-
- xbar_mix_in7: endpoint {
- remote-endpoint = <&mix_in7>;
- };
- };
-
- xbar_mix_in8_port: port@5b {
- reg = <0x5b>;
-
- xbar_mix_in8: endpoint {
- remote-endpoint = <&mix_in8>;
- };
- };
-
- xbar_mix_in9_port: port@5c {
- reg = <0x5c>;
-
- xbar_mix_in9: endpoint {
- remote-endpoint = <&mix_in9>;
- };
- };
-
- xbar_mix_in10_port: port@5d {
- reg = <0x5d>;
-
- xbar_mix_in10: endpoint {
- remote-endpoint = <&mix_in10>;
- };
- };
-
- port@5e {
- reg = <0x5e>;
-
- xbar_mix_out1: endpoint {
- remote-endpoint = <&mix_out1>;
- };
- };
-
- port@5f {
- reg = <0x5f>;
-
- xbar_mix_out2: endpoint {
- remote-endpoint = <&mix_out2>;
- };
- };
-
- port@60 {
- reg = <0x60>;
-
- xbar_mix_out3: endpoint {
- remote-endpoint = <&mix_out3>;
- };
- };
-
- port@61 {
- reg = <0x61>;
-
- xbar_mix_out4: endpoint {
- remote-endpoint = <&mix_out4>;
- };
- };
-
- port@62 {
- reg = <0x62>;
-
- xbar_mix_out5: endpoint {
- remote-endpoint = <&mix_out5>;
- };
- };
-
- xbar_asrc_in1_port: port@63 {
- reg = <0x63>;
-
- xbar_asrc_in1_ep: endpoint {
- remote-endpoint = <&asrc_in1_ep>;
- };
- };
-
- port@64 {
- reg = <0x64>;
-
- xbar_asrc_out1_ep: endpoint {
- remote-endpoint = <&asrc_out1_ep>;
- };
- };
-
- xbar_asrc_in2_port: port@65 {
- reg = <0x65>;
-
- xbar_asrc_in2_ep: endpoint {
- remote-endpoint = <&asrc_in2_ep>;
- };
- };
-
- port@66 {
- reg = <0x66>;
-
- xbar_asrc_out2_ep: endpoint {
- remote-endpoint = <&asrc_out2_ep>;
- };
- };
-
- xbar_asrc_in3_port: port@67 {
- reg = <0x67>;
-
- xbar_asrc_in3_ep: endpoint {
- remote-endpoint = <&asrc_in3_ep>;
- };
- };
-
- port@68 {
- reg = <0x68>;
-
- xbar_asrc_out3_ep: endpoint {
- remote-endpoint = <&asrc_out3_ep>;
- };
- };
-
- xbar_asrc_in4_port: port@69 {
- reg = <0x69>;
-
- xbar_asrc_in4_ep: endpoint {
- remote-endpoint = <&asrc_in4_ep>;
- };
- };
-
- port@6a {
- reg = <0x6a>;
-
- xbar_asrc_out4_ep: endpoint {
- remote-endpoint = <&asrc_out4_ep>;
- };
- };
-
- xbar_asrc_in5_port: port@6b {
- reg = <0x6b>;
-
- xbar_asrc_in5_ep: endpoint {
- remote-endpoint = <&asrc_in5_ep>;
- };
- };
-
- port@6c {
- reg = <0x6c>;
-
- xbar_asrc_out5_ep: endpoint {
- remote-endpoint = <&asrc_out5_ep>;
- };
- };
-
- xbar_asrc_in6_port: port@6d {
- reg = <0x6d>;
-
- xbar_asrc_in6_ep: endpoint {
- remote-endpoint = <&asrc_in6_ep>;
- };
- };
-
- port@6e {
- reg = <0x6e>;
-
- xbar_asrc_out6_ep: endpoint {
- remote-endpoint = <&asrc_out6_ep>;
- };
- };
-
- xbar_asrc_in7_port: port@6f {
- reg = <0x6f>;
-
- xbar_asrc_in7_ep: endpoint {
- remote-endpoint = <&asrc_in7_ep>;
- };
- };
-
- xbar_ope1_in_port: port@70 {
- reg = <0x70>;
-
- xbar_ope1_in_ep: endpoint {
- remote-endpoint = <&ope1_cif_in_ep>;
- };
- };
-
- port@71 {
- reg = <0x71>;
-
- xbar_ope1_out_ep: endpoint {
- remote-endpoint = <&ope1_cif_out_ep>;
- };
- };
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 3f16595d099c..a01ff6174f74 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -200,6 +200,28 @@ tegra_i2s1: i2s@2901000 {
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S1";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s1_cif: endpoint {
+ remote-endpoint = <&xbar_i2s1>;
+ };
+ };
+
+ i2s1_port: port@1 {
+ reg = <1>;
+
+ i2s1_dap: endpoint {
+ dai-format = "i2s";
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_i2s2: i2s@2901100 {
@@ -214,6 +236,28 @@ tegra_i2s2: i2s@2901100 {
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S2";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s2_cif: endpoint {
+ remote-endpoint = <&xbar_i2s2>;
+ };
+ };
+
+ i2s2_port: port@1 {
+ reg = <1>;
+
+ i2s2_dap: endpoint {
+ dai-format = "i2s";
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_i2s3: i2s@2901200 {
@@ -242,6 +286,28 @@ tegra_i2s4: i2s@2901300 {
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S4";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s4_cif: endpoint {
+ remote-endpoint = <&xbar_i2s4>;
+ };
+ };
+
+ i2s4_port: port@1 {
+ reg = <1>;
+
+ i2s4_dap: endpoint {
+ dai-format = "i2s";
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_i2s5: i2s@2901400 {
@@ -270,6 +336,28 @@ tegra_i2s6: i2s@2901500 {
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S6";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s6_cif: endpoint {
+ remote-endpoint = <&xbar_i2s6>;
+ };
+ };
+
+ i2s6_port: port@1 {
+ reg = <1>;
+
+ i2s6_dap: endpoint {
+ dai-format = "i2s";
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_sfc1: sfc@2902000 {
@@ -277,7 +365,27 @@ tegra_sfc1: sfc@2902000 {
"nvidia,tegra210-sfc";
reg = <0x0 0x2902000 0x0 0x200>;
sound-name-prefix = "SFC1";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc1_cif_in: endpoint {
+ remote-endpoint = <&xbar_sfc1_in>;
+ };
+ };
+
+ sfc1_out_port: port@1 {
+ reg = <1>;
+
+ sfc1_cif_out: endpoint {
+ remote-endpoint = <&xbar_sfc1_out>;
+ };
+ };
+ };
};
tegra_sfc2: sfc@2902200 {
@@ -285,7 +393,27 @@ tegra_sfc2: sfc@2902200 {
"nvidia,tegra210-sfc";
reg = <0x0 0x2902200 0x0 0x200>;
sound-name-prefix = "SFC2";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc2_cif_in: endpoint {
+ remote-endpoint = <&xbar_sfc2_in>;
+ };
+ };
+
+ sfc2_out_port: port@1 {
+ reg = <1>;
+
+ sfc2_cif_out: endpoint {
+ remote-endpoint = <&xbar_sfc2_out>;
+ };
+ };
+ };
};
tegra_sfc3: sfc@2902400 {
@@ -293,7 +421,27 @@ tegra_sfc3: sfc@2902400 {
"nvidia,tegra210-sfc";
reg = <0x0 0x2902400 0x0 0x200>;
sound-name-prefix = "SFC3";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc3_cif_in: endpoint {
+ remote-endpoint = <&xbar_sfc3_in>;
+ };
+ };
+
+ sfc3_out_port: port@1 {
+ reg = <1>;
+
+ sfc3_cif_out: endpoint {
+ remote-endpoint = <&xbar_sfc3_out>;
+ };
+ };
+ };
};
tegra_sfc4: sfc@2902600 {
@@ -301,7 +449,27 @@ tegra_sfc4: sfc@2902600 {
"nvidia,tegra210-sfc";
reg = <0x0 0x2902600 0x0 0x200>;
sound-name-prefix = "SFC4";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sfc4_cif_in: endpoint {
+ remote-endpoint = <&xbar_sfc4_in>;
+ };
+ };
+
+ sfc4_out_port: port@1 {
+ reg = <1>;
+
+ sfc4_cif_out: endpoint {
+ remote-endpoint = <&xbar_sfc4_out>;
+ };
+ };
+ };
};
tegra_amx1: amx@2903000 {
@@ -309,7 +477,51 @@ tegra_amx1: amx@2903000 {
"nvidia,tegra194-amx";
reg = <0x0 0x2903000 0x0 0x100>;
sound-name-prefix = "AMX1";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx1_in1: endpoint {
+ remote-endpoint = <&xbar_amx1_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx1_in2: endpoint {
+ remote-endpoint = <&xbar_amx1_in2>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx1_in3: endpoint {
+ remote-endpoint = <&xbar_amx1_in3>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx1_in4: endpoint {
+ remote-endpoint = <&xbar_amx1_in4>;
+ };
+ };
+
+ amx1_out_port: port@4 {
+ reg = <4>;
+
+ amx1_out: endpoint {
+ remote-endpoint = <&xbar_amx1_out>;
+ };
+ };
+ };
};
tegra_amx2: amx@2903100 {
@@ -317,7 +529,51 @@ tegra_amx2: amx@2903100 {
"nvidia,tegra194-amx";
reg = <0x0 0x2903100 0x0 0x100>;
sound-name-prefix = "AMX2";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx2_in1: endpoint {
+ remote-endpoint = <&xbar_amx2_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx2_in2: endpoint {
+ remote-endpoint = <&xbar_amx2_in2>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx2_in3: endpoint {
+ remote-endpoint = <&xbar_amx2_in3>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx2_in4: endpoint {
+ remote-endpoint = <&xbar_amx2_in4>;
+ };
+ };
+
+ amx2_out_port: port@4 {
+ reg = <4>;
+
+ amx2_out: endpoint {
+ remote-endpoint = <&xbar_amx2_out>;
+ };
+ };
+ };
};
tegra_amx3: amx@2903200 {
@@ -325,7 +581,51 @@ tegra_amx3: amx@2903200 {
"nvidia,tegra194-amx";
reg = <0x0 0x2903200 0x0 0x100>;
sound-name-prefix = "AMX3";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx3_in1: endpoint {
+ remote-endpoint = <&xbar_amx3_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx3_in2: endpoint {
+ remote-endpoint = <&xbar_amx3_in2>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx3_in3: endpoint {
+ remote-endpoint = <&xbar_amx3_in3>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx3_in4: endpoint {
+ remote-endpoint = <&xbar_amx3_in4>;
+ };
+ };
+
+ amx3_out_port: port@4 {
+ reg = <4>;
+
+ amx3_out: endpoint {
+ remote-endpoint = <&xbar_amx3_out>;
+ };
+ };
+ };
};
tegra_amx4: amx@2903300 {
@@ -333,7 +633,51 @@ tegra_amx4: amx@2903300 {
"nvidia,tegra194-amx";
reg = <0x0 0x2903300 0x0 0x100>;
sound-name-prefix = "AMX4";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ amx4_in1: endpoint {
+ remote-endpoint = <&xbar_amx4_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ amx4_in2: endpoint {
+ remote-endpoint = <&xbar_amx4_in2>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ amx4_in3: endpoint {
+ remote-endpoint = <&xbar_amx4_in3>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ amx4_in4: endpoint {
+ remote-endpoint = <&xbar_amx4_in4>;
+ };
+ };
+
+ amx4_out_port: port@4 {
+ reg = <4>;
+
+ amx4_out: endpoint {
+ remote-endpoint = <&xbar_amx4_out>;
+ };
+ };
+ };
};
tegra_adx1: adx@2903800 {
@@ -341,7 +685,51 @@ tegra_adx1: adx@2903800 {
"nvidia,tegra210-adx";
reg = <0x0 0x2903800 0x0 0x100>;
sound-name-prefix = "ADX1";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx1_in: endpoint {
+ remote-endpoint = <&xbar_adx1_in>;
+ };
+ };
+
+ adx1_out1_port: port@1 {
+ reg = <1>;
+
+ adx1_out1: endpoint {
+ remote-endpoint = <&xbar_adx1_out1>;
+ };
+ };
+
+ adx1_out2_port: port@2 {
+ reg = <2>;
+
+ adx1_out2: endpoint {
+ remote-endpoint = <&xbar_adx1_out2>;
+ };
+ };
+
+ adx1_out3_port: port@3 {
+ reg = <3>;
+
+ adx1_out3: endpoint {
+ remote-endpoint = <&xbar_adx1_out3>;
+ };
+ };
+
+ adx1_out4_port: port@4 {
+ reg = <4>;
+
+ adx1_out4: endpoint {
+ remote-endpoint = <&xbar_adx1_out4>;
+ };
+ };
+ };
};
tegra_adx2: adx@2903900 {
@@ -349,7 +737,51 @@ tegra_adx2: adx@2903900 {
"nvidia,tegra210-adx";
reg = <0x0 0x2903900 0x0 0x100>;
sound-name-prefix = "ADX2";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx2_in: endpoint {
+ remote-endpoint = <&xbar_adx2_in>;
+ };
+ };
+
+ adx2_out1_port: port@1 {
+ reg = <1>;
+
+ adx2_out1: endpoint {
+ remote-endpoint = <&xbar_adx2_out1>;
+ };
+ };
+
+ adx2_out2_port: port@2 {
+ reg = <2>;
+
+ adx2_out2: endpoint {
+ remote-endpoint = <&xbar_adx2_out2>;
+ };
+ };
+
+ adx2_out3_port: port@3 {
+ reg = <3>;
+
+ adx2_out3: endpoint {
+ remote-endpoint = <&xbar_adx2_out3>;
+ };
+ };
+
+ adx2_out4_port: port@4 {
+ reg = <4>;
+
+ adx2_out4: endpoint {
+ remote-endpoint = <&xbar_adx2_out4>;
+ };
+ };
+ };
};
tegra_adx3: adx@2903a00 {
@@ -357,7 +789,51 @@ tegra_adx3: adx@2903a00 {
"nvidia,tegra210-adx";
reg = <0x0 0x2903a00 0x0 0x100>;
sound-name-prefix = "ADX3";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx3_in: endpoint {
+ remote-endpoint = <&xbar_adx3_in>;
+ };
+ };
+
+ adx3_out1_port: port@1 {
+ reg = <1>;
+
+ adx3_out1: endpoint {
+ remote-endpoint = <&xbar_adx3_out1>;
+ };
+ };
+
+ adx3_out2_port: port@2 {
+ reg = <2>;
+
+ adx3_out2: endpoint {
+ remote-endpoint = <&xbar_adx3_out2>;
+ };
+ };
+
+ adx3_out3_port: port@3 {
+ reg = <3>;
+
+ adx3_out3: endpoint {
+ remote-endpoint = <&xbar_adx3_out3>;
+ };
+ };
+
+ adx3_out4_port: port@4 {
+ reg = <4>;
+
+ adx3_out4: endpoint {
+ remote-endpoint = <&xbar_adx3_out4>;
+ };
+ };
+ };
};
tegra_adx4: adx@2903b00 {
@@ -365,7 +841,51 @@ tegra_adx4: adx@2903b00 {
"nvidia,tegra210-adx";
reg = <0x0 0x2903b00 0x0 0x100>;
sound-name-prefix = "ADX4";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adx4_in: endpoint {
+ remote-endpoint = <&xbar_adx4_in>;
+ };
+ };
+
+ adx4_out1_port: port@1 {
+ reg = <1>;
+
+ adx4_out1: endpoint {
+ remote-endpoint = <&xbar_adx4_out1>;
+ };
+ };
+
+ adx4_out2_port: port@2 {
+ reg = <2>;
+
+ adx4_out2: endpoint {
+ remote-endpoint = <&xbar_adx4_out2>;
+ };
+ };
+
+ adx4_out3_port: port@3 {
+ reg = <3>;
+
+ adx4_out3: endpoint {
+ remote-endpoint = <&xbar_adx4_out3>;
+ };
+ };
+
+ adx4_out4_port: port@4 {
+ reg = <4>;
+
+ adx4_out4: endpoint {
+ remote-endpoint = <&xbar_adx4_out4>;
+ };
+ };
+ };
};
@@ -406,6 +926,27 @@ tegra_dmic3: dmic@2904200 {
assigned-clock-rates = <3072000>;
sound-name-prefix = "DMIC3";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic3_cif: endpoint {
+ remote-endpoint = <&xbar_dmic3>;
+ };
+ };
+
+ dmic3_port: port@1 {
+ reg = <1>;
+
+ dmic3_dap: endpoint {
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_dmic4: dmic@2904300 {
@@ -452,7 +993,6 @@ tegra_ope1: processing-engine@2908000 {
"nvidia,tegra210-ope";
reg = <0x0 0x2908000 0x0 0x100>;
sound-name-prefix = "OPE1";
- status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
@@ -469,6 +1009,29 @@ dynamic-range-compressor@2908200 {
"nvidia,tegra210-mbdrc";
reg = <0x0 0x2908200 0x0 0x200>;
};
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ ope1_cif_in_ep: endpoint {
+ remote-endpoint =
+ <&xbar_ope1_in_ep>;
+ };
+ };
+
+ ope1_out_port: port@1 {
+ reg = <0x1>;
+
+ ope1_cif_out_ep: endpoint {
+ remote-endpoint =
+ <&xbar_ope1_out_ep>;
+ };
+ };
+ };
};
tegra_mvc1: mvc@290a000 {
@@ -476,7 +1039,27 @@ tegra_mvc1: mvc@290a000 {
"nvidia,tegra210-mvc";
reg = <0x0 0x290a000 0x0 0x200>;
sound-name-prefix = "MVC1";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc1_cif_in: endpoint {
+ remote-endpoint = <&xbar_mvc1_in>;
+ };
+ };
+
+ mvc1_out_port: port@1 {
+ reg = <1>;
+
+ mvc1_cif_out: endpoint {
+ remote-endpoint = <&xbar_mvc1_out>;
+ };
+ };
+ };
};
tegra_mvc2: mvc@290a200 {
@@ -484,7 +1067,27 @@ tegra_mvc2: mvc@290a200 {
"nvidia,tegra210-mvc";
reg = <0x0 0x290a200 0x0 0x200>;
sound-name-prefix = "MVC2";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mvc2_cif_in: endpoint {
+ remote-endpoint = <&xbar_mvc2_in>;
+ };
+ };
+
+ mvc2_out_port: port@1 {
+ reg = <1>;
+
+ mvc2_cif_out: endpoint {
+ remote-endpoint = <&xbar_mvc2_out>;
+ };
+ };
+ };
};
tegra_amixer: amixer@290bb00 {
@@ -492,16 +1095,140 @@ tegra_amixer: amixer@290bb00 {
"nvidia,tegra210-amixer";
reg = <0x0 0x290bb00 0x0 0x800>;
sound-name-prefix = "MIXER1";
- status = "disabled";
- };
- tegra_admaif: admaif@290f000 {
- compatible = "nvidia,tegra234-admaif",
- "nvidia,tegra186-admaif";
- reg = <0x0 0x0290f000 0x0 0x1000>;
- dmas = <&adma 1>, <&adma 1>,
- <&adma 2>, <&adma 2>,
- <&adma 3>, <&adma 3>,
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ mix_in1: endpoint {
+ remote-endpoint = <&xbar_mix_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ mix_in2: endpoint {
+ remote-endpoint = <&xbar_mix_in2>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ mix_in3: endpoint {
+ remote-endpoint = <&xbar_mix_in3>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ mix_in4: endpoint {
+ remote-endpoint = <&xbar_mix_in4>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ mix_in5: endpoint {
+ remote-endpoint = <&xbar_mix_in5>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ mix_in6: endpoint {
+ remote-endpoint = <&xbar_mix_in6>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ mix_in7: endpoint {
+ remote-endpoint = <&xbar_mix_in7>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ mix_in8: endpoint {
+ remote-endpoint = <&xbar_mix_in8>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ mix_in9: endpoint {
+ remote-endpoint = <&xbar_mix_in9>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ mix_in10: endpoint {
+ remote-endpoint = <&xbar_mix_in10>;
+ };
+ };
+
+ mix_out1_port: port@a {
+ reg = <0xa>;
+
+ mix_out1: endpoint {
+ remote-endpoint = <&xbar_mix_out1>;
+ };
+ };
+
+ mix_out2_port: port@b {
+ reg = <0xb>;
+
+ mix_out2: endpoint {
+ remote-endpoint = <&xbar_mix_out2>;
+ };
+ };
+
+ mix_out3_port: port@c {
+ reg = <0xc>;
+
+ mix_out3: endpoint {
+ remote-endpoint = <&xbar_mix_out3>;
+ };
+ };
+
+ mix_out4_port: port@d {
+ reg = <0xd>;
+
+ mix_out4: endpoint {
+ remote-endpoint = <&xbar_mix_out4>;
+ };
+ };
+
+ mix_out5_port: port@e {
+ reg = <0xe>;
+
+ mix_out5: endpoint {
+ remote-endpoint = <&xbar_mix_out5>;
+ };
+ };
+ };
+ };
+
+ tegra_admaif: admaif@290f000 {
+ compatible = "nvidia,tegra234-admaif",
+ "nvidia,tegra186-admaif";
+ reg = <0x0 0x0290f000 0x0 0x1000>;
+ dmas = <&adma 1>, <&adma 1>,
+ <&adma 2>, <&adma 2>,
+ <&adma 3>, <&adma 3>,
<&adma 4>, <&adma 4>,
<&adma 5>, <&adma 5>,
<&adma 6>, <&adma 6>,
@@ -543,7 +1270,171 @@ tegra_admaif: admaif@290f000 {
<&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_APE>;
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ admaif0_port: port@0 {
+ reg = <0x0>;
+
+ admaif0: endpoint {
+ remote-endpoint = <&xbar_admaif0>;
+ };
+ };
+
+ admaif1_port: port@1 {
+ reg = <0x1>;
+
+ admaif1: endpoint {
+ remote-endpoint = <&xbar_admaif1>;
+ };
+ };
+
+ admaif2_port: port@2 {
+ reg = <0x2>;
+
+ admaif2: endpoint {
+ remote-endpoint = <&xbar_admaif2>;
+ };
+ };
+
+ admaif3_port: port@3 {
+ reg = <0x3>;
+
+ admaif3: endpoint {
+ remote-endpoint = <&xbar_admaif3>;
+ };
+ };
+
+ admaif4_port: port@4 {
+ reg = <0x4>;
+
+ admaif4: endpoint {
+ remote-endpoint = <&xbar_admaif4>;
+ };
+ };
+
+ admaif5_port: port@5 {
+ reg = <0x5>;
+
+ admaif5: endpoint {
+ remote-endpoint = <&xbar_admaif5>;
+ };
+ };
+
+ admaif6_port: port@6 {
+ reg = <0x6>;
+
+ admaif6: endpoint {
+ remote-endpoint = <&xbar_admaif6>;
+ };
+ };
+
+ admaif7_port: port@7 {
+ reg = <0x7>;
+
+ admaif7: endpoint {
+ remote-endpoint = <&xbar_admaif7>;
+ };
+ };
+
+ admaif8_port: port@8 {
+ reg = <0x8>;
+
+ admaif8: endpoint {
+ remote-endpoint = <&xbar_admaif8>;
+ };
+ };
+
+ admaif9_port: port@9 {
+ reg = <0x9>;
+
+ admaif9: endpoint {
+ remote-endpoint = <&xbar_admaif9>;
+ };
+ };
+
+ admaif10_port: port@a {
+ reg = <0xa>;
+
+ admaif10: endpoint {
+ remote-endpoint = <&xbar_admaif10>;
+ };
+ };
+
+ admaif11_port: port@b {
+ reg = <0xb>;
+
+ admaif11: endpoint {
+ remote-endpoint = <&xbar_admaif11>;
+ };
+ };
+
+ admaif12_port: port@c {
+ reg = <0xc>;
+
+ admaif12: endpoint {
+ remote-endpoint = <&xbar_admaif12>;
+ };
+ };
+
+ admaif13_port: port@d {
+ reg = <0xd>;
+
+ admaif13: endpoint {
+ remote-endpoint = <&xbar_admaif13>;
+ };
+ };
+
+ admaif14_port: port@e {
+ reg = <0xe>;
+
+ admaif14: endpoint {
+ remote-endpoint = <&xbar_admaif14>;
+ };
+ };
+
+ admaif15_port: port@f {
+ reg = <0xf>;
+
+ admaif15: endpoint {
+ remote-endpoint = <&xbar_admaif15>;
+ };
+ };
+
+ admaif16_port: port@10 {
+ reg = <0x10>;
+
+ admaif16: endpoint {
+ remote-endpoint = <&xbar_admaif16>;
+ };
+ };
+
+ admaif17_port: port@11 {
+ reg = <0x11>;
+
+ admaif17: endpoint {
+ remote-endpoint = <&xbar_admaif17>;
+ };
+ };
+
+ admaif18_port: port@12 {
+ reg = <0x12>;
+
+ admaif18: endpoint {
+ remote-endpoint = <&xbar_admaif18>;
+ };
+ };
+
+ admaif19_port: port@13 {
+ reg = <0x13>;
+
+ admaif19: endpoint {
+ remote-endpoint = <&xbar_admaif19>;
+ };
+ };
+ };
};
tegra_asrc: asrc@2910000 {
@@ -551,7 +1442,989 @@ tegra_asrc: asrc@2910000 {
"nvidia,tegra186-asrc";
reg = <0x0 0x2910000 0x0 0x2000>;
sound-name-prefix = "ASRC1";
- status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ asrc_in1_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in1_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ asrc_in2_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in2_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ asrc_in3_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in3_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ asrc_in4_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in4_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ asrc_in5_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in5_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ asrc_in6_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in6_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ asrc_in7_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_in7_ep>;
+ };
+ };
+
+ asrc_out1_port: port@7 {
+ reg = <0x7>;
+
+ asrc_out1_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_out1_ep>;
+ };
+ };
+
+ asrc_out2_port: port@8 {
+ reg = <0x8>;
+
+ asrc_out2_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_out2_ep>;
+ };
+ };
+
+ asrc_out3_port: port@9 {
+ reg = <0x9>;
+
+ asrc_out3_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_out3_ep>;
+ };
+ };
+
+ asrc_out4_port: port@a {
+ reg = <0xa>;
+
+ asrc_out4_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_out4_ep>;
+ };
+ };
+
+ asrc_out5_port: port@b {
+ reg = <0xb>;
+
+ asrc_out5_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_out5_ep>;
+ };
+ };
+
+ asrc_out6_port: port@c {
+ reg = <0xc>;
+
+ asrc_out6_ep: endpoint {
+ remote-endpoint =
+ <&xbar_asrc_out6_ep>;
+ };
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ xbar_admaif0: endpoint {
+ remote-endpoint = <&admaif0>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ xbar_admaif1: endpoint {
+ remote-endpoint = <&admaif1>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ xbar_admaif2: endpoint {
+ remote-endpoint = <&admaif2>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ xbar_admaif3: endpoint {
+ remote-endpoint = <&admaif3>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ xbar_admaif4: endpoint {
+ remote-endpoint = <&admaif4>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ xbar_admaif5: endpoint {
+ remote-endpoint = <&admaif5>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ xbar_admaif6: endpoint {
+ remote-endpoint = <&admaif6>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ xbar_admaif7: endpoint {
+ remote-endpoint = <&admaif7>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ xbar_admaif8: endpoint {
+ remote-endpoint = <&admaif8>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ xbar_admaif9: endpoint {
+ remote-endpoint = <&admaif9>;
+ };
+ };
+
+ port@a {
+ reg = <0xa>;
+
+ xbar_admaif10: endpoint {
+ remote-endpoint = <&admaif10>;
+ };
+ };
+
+ port@b {
+ reg = <0xb>;
+
+ xbar_admaif11: endpoint {
+ remote-endpoint = <&admaif11>;
+ };
+ };
+
+ port@c {
+ reg = <0xc>;
+
+ xbar_admaif12: endpoint {
+ remote-endpoint = <&admaif12>;
+ };
+ };
+
+ port@d {
+ reg = <0xd>;
+
+ xbar_admaif13: endpoint {
+ remote-endpoint = <&admaif13>;
+ };
+ };
+
+ port@e {
+ reg = <0xe>;
+
+ xbar_admaif14: endpoint {
+ remote-endpoint = <&admaif14>;
+ };
+ };
+
+ port@f {
+ reg = <0xf>;
+
+ xbar_admaif15: endpoint {
+ remote-endpoint = <&admaif15>;
+ };
+ };
+
+ port@10 {
+ reg = <0x10>;
+
+ xbar_admaif16: endpoint {
+ remote-endpoint = <&admaif16>;
+ };
+ };
+
+ port@11 {
+ reg = <0x11>;
+
+ xbar_admaif17: endpoint {
+ remote-endpoint = <&admaif17>;
+ };
+ };
+
+ port@12 {
+ reg = <0x12>;
+
+ xbar_admaif18: endpoint {
+ remote-endpoint = <&admaif18>;
+ };
+ };
+
+ port@13 {
+ reg = <0x13>;
+
+ xbar_admaif19: endpoint {
+ remote-endpoint = <&admaif19>;
+ };
+ };
+
+ xbar_i2s1_port: port@14 {
+ reg = <0x14>;
+
+ xbar_i2s1: endpoint {
+ remote-endpoint = <&i2s1_cif>;
+ };
+ };
+
+ xbar_i2s2_port: port@15 {
+ reg = <0x15>;
+
+ xbar_i2s2: endpoint {
+ remote-endpoint = <&i2s2_cif>;
+ };
+ };
+
+ xbar_i2s4_port: port@17 {
+ reg = <0x17>;
+
+ xbar_i2s4: endpoint {
+ remote-endpoint = <&i2s4_cif>;
+ };
+ };
+
+ xbar_i2s6_port: port@19 {
+ reg = <0x19>;
+
+ xbar_i2s6: endpoint {
+ remote-endpoint = <&i2s6_cif>;
+ };
+ };
+
+ xbar_dmic3_port: port@1c {
+ reg = <0x1c>;
+
+ xbar_dmic3: endpoint {
+ remote-endpoint = <&dmic3_cif>;
+ };
+ };
+
+ xbar_sfc1_in_port: port@20 {
+ reg = <0x20>;
+
+ xbar_sfc1_in: endpoint {
+ remote-endpoint = <&sfc1_cif_in>;
+ };
+ };
+
+ port@21 {
+ reg = <0x21>;
+
+ xbar_sfc1_out: endpoint {
+ remote-endpoint = <&sfc1_cif_out>;
+ };
+ };
+
+ xbar_sfc2_in_port: port@22 {
+ reg = <0x22>;
+
+ xbar_sfc2_in: endpoint {
+ remote-endpoint = <&sfc2_cif_in>;
+ };
+ };
+
+ port@23 {
+ reg = <0x23>;
+
+ xbar_sfc2_out: endpoint {
+ remote-endpoint = <&sfc2_cif_out>;
+ };
+ };
+
+ xbar_sfc3_in_port: port@24 {
+ reg = <0x24>;
+
+ xbar_sfc3_in: endpoint {
+ remote-endpoint = <&sfc3_cif_in>;
+ };
+ };
+
+ port@25 {
+ reg = <0x25>;
+
+ xbar_sfc3_out: endpoint {
+ remote-endpoint = <&sfc3_cif_out>;
+ };
+ };
+
+ xbar_sfc4_in_port: port@26 {
+ reg = <0x26>;
+
+ xbar_sfc4_in: endpoint {
+ remote-endpoint = <&sfc4_cif_in>;
+ };
+ };
+
+ port@27 {
+ reg = <0x27>;
+
+ xbar_sfc4_out: endpoint {
+ remote-endpoint = <&sfc4_cif_out>;
+ };
+ };
+
+ xbar_mvc1_in_port: port@28 {
+ reg = <0x28>;
+
+ xbar_mvc1_in: endpoint {
+ remote-endpoint = <&mvc1_cif_in>;
+ };
+ };
+
+ port@29 {
+ reg = <0x29>;
+
+ xbar_mvc1_out: endpoint {
+ remote-endpoint = <&mvc1_cif_out>;
+ };
+ };
+
+ xbar_mvc2_in_port: port@2a {
+ reg = <0x2a>;
+
+ xbar_mvc2_in: endpoint {
+ remote-endpoint = <&mvc2_cif_in>;
+ };
+ };
+
+ port@2b {
+ reg = <0x2b>;
+
+ xbar_mvc2_out: endpoint {
+ remote-endpoint = <&mvc2_cif_out>;
+ };
+ };
+
+ xbar_amx1_in1_port: port@2c {
+ reg = <0x2c>;
+
+ xbar_amx1_in1: endpoint {
+ remote-endpoint = <&amx1_in1>;
+ };
+ };
+
+ xbar_amx1_in2_port: port@2d {
+ reg = <0x2d>;
+
+ xbar_amx1_in2: endpoint {
+ remote-endpoint = <&amx1_in2>;
+ };
+ };
+
+ xbar_amx1_in3_port: port@2e {
+ reg = <0x2e>;
+
+ xbar_amx1_in3: endpoint {
+ remote-endpoint = <&amx1_in3>;
+ };
+ };
+
+ xbar_amx1_in4_port: port@2f {
+ reg = <0x2f>;
+
+ xbar_amx1_in4: endpoint {
+ remote-endpoint = <&amx1_in4>;
+ };
+ };
+
+ port@30 {
+ reg = <0x30>;
+
+ xbar_amx1_out: endpoint {
+ remote-endpoint = <&amx1_out>;
+ };
+ };
+
+ xbar_amx2_in1_port: port@31 {
+ reg = <0x31>;
+
+ xbar_amx2_in1: endpoint {
+ remote-endpoint = <&amx2_in1>;
+ };
+ };
+
+ xbar_amx2_in2_port: port@32 {
+ reg = <0x32>;
+
+ xbar_amx2_in2: endpoint {
+ remote-endpoint = <&amx2_in2>;
+ };
+ };
+
+ xbar_amx2_in3_port: port@33 {
+ reg = <0x33>;
+
+ xbar_amx2_in3: endpoint {
+ remote-endpoint = <&amx2_in3>;
+ };
+ };
+
+ xbar_amx2_in4_port: port@34 {
+ reg = <0x34>;
+
+ xbar_amx2_in4: endpoint {
+ remote-endpoint = <&amx2_in4>;
+ };
+ };
+
+ port@35 {
+ reg = <0x35>;
+
+ xbar_amx2_out: endpoint {
+ remote-endpoint = <&amx2_out>;
+ };
+ };
+
+ xbar_amx3_in1_port: port@36 {
+ reg = <0x36>;
+
+ xbar_amx3_in1: endpoint {
+ remote-endpoint = <&amx3_in1>;
+ };
+ };
+
+ xbar_amx3_in2_port: port@37 {
+ reg = <0x37>;
+
+ xbar_amx3_in2: endpoint {
+ remote-endpoint = <&amx3_in2>;
+ };
+ };
+
+ xbar_amx3_in3_port: port@38 {
+ reg = <0x38>;
+
+ xbar_amx3_in3: endpoint {
+ remote-endpoint = <&amx3_in3>;
+ };
+ };
+
+ xbar_amx3_in4_port: port@39 {
+ reg = <0x39>;
+
+ xbar_amx3_in4: endpoint {
+ remote-endpoint = <&amx3_in4>;
+ };
+ };
+
+ port@3a {
+ reg = <0x3a>;
+
+ xbar_amx3_out: endpoint {
+ remote-endpoint = <&amx3_out>;
+ };
+ };
+
+ xbar_amx4_in1_port: port@3b {
+ reg = <0x3b>;
+
+ xbar_amx4_in1: endpoint {
+ remote-endpoint = <&amx4_in1>;
+ };
+ };
+
+ xbar_amx4_in2_port: port@3c {
+ reg = <0x3c>;
+
+ xbar_amx4_in2: endpoint {
+ remote-endpoint = <&amx4_in2>;
+ };
+ };
+
+ xbar_amx4_in3_port: port@3d {
+ reg = <0x3d>;
+
+ xbar_amx4_in3: endpoint {
+ remote-endpoint = <&amx4_in3>;
+ };
+ };
+
+ xbar_amx4_in4_port: port@3e {
+ reg = <0x3e>;
+
+ xbar_amx4_in4: endpoint {
+ remote-endpoint = <&amx4_in4>;
+ };
+ };
+
+ port@3f {
+ reg = <0x3f>;
+
+ xbar_amx4_out: endpoint {
+ remote-endpoint = <&amx4_out>;
+ };
+ };
+
+ xbar_adx1_in_port: port@40 {
+ reg = <0x40>;
+
+ xbar_adx1_in: endpoint {
+ remote-endpoint = <&adx1_in>;
+ };
+ };
+
+ port@41 {
+ reg = <0x41>;
+
+ xbar_adx1_out1: endpoint {
+ remote-endpoint = <&adx1_out1>;
+ };
+ };
+
+ port@42 {
+ reg = <0x42>;
+
+ xbar_adx1_out2: endpoint {
+ remote-endpoint = <&adx1_out2>;
+ };
+ };
+
+ port@43 {
+ reg = <0x43>;
+
+ xbar_adx1_out3: endpoint {
+ remote-endpoint = <&adx1_out3>;
+ };
+ };
+
+ port@44 {
+ reg = <0x44>;
+
+ xbar_adx1_out4: endpoint {
+ remote-endpoint = <&adx1_out4>;
+ };
+ };
+
+ xbar_adx2_in_port: port@45 {
+ reg = <0x45>;
+
+ xbar_adx2_in: endpoint {
+ remote-endpoint = <&adx2_in>;
+ };
+ };
+
+ port@46 {
+ reg = <0x46>;
+
+ xbar_adx2_out1: endpoint {
+ remote-endpoint = <&adx2_out1>;
+ };
+ };
+
+ port@47 {
+ reg = <0x47>;
+
+ xbar_adx2_out2: endpoint {
+ remote-endpoint = <&adx2_out2>;
+ };
+ };
+
+ port@48 {
+ reg = <0x48>;
+
+ xbar_adx2_out3: endpoint {
+ remote-endpoint = <&adx2_out3>;
+ };
+ };
+
+ port@49 {
+ reg = <0x49>;
+
+ xbar_adx2_out4: endpoint {
+ remote-endpoint = <&adx2_out4>;
+ };
+ };
+
+ xbar_adx3_in_port: port@4a {
+ reg = <0x4a>;
+
+ xbar_adx3_in: endpoint {
+ remote-endpoint = <&adx3_in>;
+ };
+ };
+
+ port@4b {
+ reg = <0x4b>;
+
+ xbar_adx3_out1: endpoint {
+ remote-endpoint = <&adx3_out1>;
+ };
+ };
+
+ port@4c {
+ reg = <0x4c>;
+
+ xbar_adx3_out2: endpoint {
+ remote-endpoint = <&adx3_out2>;
+ };
+ };
+
+ port@4d {
+ reg = <0x4d>;
+
+ xbar_adx3_out3: endpoint {
+ remote-endpoint = <&adx3_out3>;
+ };
+ };
+
+ port@4e {
+ reg = <0x4e>;
+
+ xbar_adx3_out4: endpoint {
+ remote-endpoint = <&adx3_out4>;
+ };
+ };
+
+ xbar_adx4_in_port: port@4f {
+ reg = <0x4f>;
+
+ xbar_adx4_in: endpoint {
+ remote-endpoint = <&adx4_in>;
+ };
+ };
+
+ port@50 {
+ reg = <0x50>;
+
+ xbar_adx4_out1: endpoint {
+ remote-endpoint = <&adx4_out1>;
+ };
+ };
+
+ port@51 {
+ reg = <0x51>;
+
+ xbar_adx4_out2: endpoint {
+ remote-endpoint = <&adx4_out2>;
+ };
+ };
+
+ port@52 {
+ reg = <0x52>;
+
+ xbar_adx4_out3: endpoint {
+ remote-endpoint = <&adx4_out3>;
+ };
+ };
+
+ port@53 {
+ reg = <0x53>;
+
+ xbar_adx4_out4: endpoint {
+ remote-endpoint = <&adx4_out4>;
+ };
+ };
+
+ xbar_mix_in1_port: port@54 {
+ reg = <0x54>;
+
+ xbar_mix_in1: endpoint {
+ remote-endpoint = <&mix_in1>;
+ };
+ };
+
+ xbar_mix_in2_port: port@55 {
+ reg = <0x55>;
+
+ xbar_mix_in2: endpoint {
+ remote-endpoint = <&mix_in2>;
+ };
+ };
+
+ xbar_mix_in3_port: port@56 {
+ reg = <0x56>;
+
+ xbar_mix_in3: endpoint {
+ remote-endpoint = <&mix_in3>;
+ };
+ };
+
+ xbar_mix_in4_port: port@57 {
+ reg = <0x57>;
+
+ xbar_mix_in4: endpoint {
+ remote-endpoint = <&mix_in4>;
+ };
+ };
+
+ xbar_mix_in5_port: port@58 {
+ reg = <0x58>;
+
+ xbar_mix_in5: endpoint {
+ remote-endpoint = <&mix_in5>;
+ };
+ };
+
+ xbar_mix_in6_port: port@59 {
+ reg = <0x59>;
+
+ xbar_mix_in6: endpoint {
+ remote-endpoint = <&mix_in6>;
+ };
+ };
+
+ xbar_mix_in7_port: port@5a {
+ reg = <0x5a>;
+
+ xbar_mix_in7: endpoint {
+ remote-endpoint = <&mix_in7>;
+ };
+ };
+
+ xbar_mix_in8_port: port@5b {
+ reg = <0x5b>;
+
+ xbar_mix_in8: endpoint {
+ remote-endpoint = <&mix_in8>;
+ };
+ };
+
+ xbar_mix_in9_port: port@5c {
+ reg = <0x5c>;
+
+ xbar_mix_in9: endpoint {
+ remote-endpoint = <&mix_in9>;
+ };
+ };
+
+ xbar_mix_in10_port: port@5d {
+ reg = <0x5d>;
+
+ xbar_mix_in10: endpoint {
+ remote-endpoint = <&mix_in10>;
+ };
+ };
+
+ port@5e {
+ reg = <0x5e>;
+
+ xbar_mix_out1: endpoint {
+ remote-endpoint = <&mix_out1>;
+ };
+ };
+
+ port@5f {
+ reg = <0x5f>;
+
+ xbar_mix_out2: endpoint {
+ remote-endpoint = <&mix_out2>;
+ };
+ };
+
+ port@60 {
+ reg = <0x60>;
+
+ xbar_mix_out3: endpoint {
+ remote-endpoint = <&mix_out3>;
+ };
+ };
+
+ port@61 {
+ reg = <0x61>;
+
+ xbar_mix_out4: endpoint {
+ remote-endpoint = <&mix_out4>;
+ };
+ };
+
+ port@62 {
+ reg = <0x62>;
+
+ xbar_mix_out5: endpoint {
+ remote-endpoint = <&mix_out5>;
+ };
+ };
+
+ xbar_asrc_in1_port: port@63 {
+ reg = <0x63>;
+
+ xbar_asrc_in1_ep: endpoint {
+ remote-endpoint = <&asrc_in1_ep>;
+ };
+ };
+
+ port@64 {
+ reg = <0x64>;
+
+ xbar_asrc_out1_ep: endpoint {
+ remote-endpoint = <&asrc_out1_ep>;
+ };
+ };
+
+ xbar_asrc_in2_port: port@65 {
+ reg = <0x65>;
+
+ xbar_asrc_in2_ep: endpoint {
+ remote-endpoint = <&asrc_in2_ep>;
+ };
+ };
+
+ port@66 {
+ reg = <0x66>;
+
+ xbar_asrc_out2_ep: endpoint {
+ remote-endpoint = <&asrc_out2_ep>;
+ };
+ };
+
+ xbar_asrc_in3_port: port@67 {
+ reg = <0x67>;
+
+ xbar_asrc_in3_ep: endpoint {
+ remote-endpoint = <&asrc_in3_ep>;
+ };
+ };
+
+ port@68 {
+ reg = <0x68>;
+
+ xbar_asrc_out3_ep: endpoint {
+ remote-endpoint = <&asrc_out3_ep>;
+ };
+ };
+
+ xbar_asrc_in4_port: port@69 {
+ reg = <0x69>;
+
+ xbar_asrc_in4_ep: endpoint {
+ remote-endpoint = <&asrc_in4_ep>;
+ };
+ };
+
+ port@6a {
+ reg = <0x6a>;
+
+ xbar_asrc_out4_ep: endpoint {
+ remote-endpoint = <&asrc_out4_ep>;
+ };
+ };
+
+ xbar_asrc_in5_port: port@6b {
+ reg = <0x6b>;
+
+ xbar_asrc_in5_ep: endpoint {
+ remote-endpoint = <&asrc_in5_ep>;
+ };
+ };
+
+ port@6c {
+ reg = <0x6c>;
+
+ xbar_asrc_out5_ep: endpoint {
+ remote-endpoint = <&asrc_out5_ep>;
+ };
+ };
+
+ xbar_asrc_in6_port: port@6d {
+ reg = <0x6d>;
+
+ xbar_asrc_in6_ep: endpoint {
+ remote-endpoint = <&asrc_in6_ep>;
+ };
+ };
+
+ port@6e {
+ reg = <0x6e>;
+
+ xbar_asrc_out6_ep: endpoint {
+ remote-endpoint = <&asrc_out6_ep>;
+ };
+ };
+
+ xbar_asrc_in7_port: port@6f {
+ reg = <0x6f>;
+
+ xbar_asrc_in7_ep: endpoint {
+ remote-endpoint = <&asrc_in7_ep>;
+ };
+ };
+
+ xbar_ope1_in_port: port@70 {
+ reg = <0x70>;
+
+ xbar_ope1_in_ep: endpoint {
+ remote-endpoint = <&ope1_cif_in_ep>;
+ };
+ };
+
+ port@71 {
+ reg = <0x71>;
+
+ xbar_ope1_out_ep: endpoint {
+ remote-endpoint = <&ope1_cif_out_ep>;
+ };
+ };
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/4] arm64: tegra: Define missing IO ports
2024-02-07 12:05 [PATCH 0/4] Add audio support for Jetson Orin NX and Jetson Sheetal .
2024-02-07 12:05 ` [PATCH 1/4] arm64: tegra: Move AHUB ports to SoC DTSI Sheetal .
@ 2024-02-07 12:05 ` Sheetal .
2024-02-07 12:05 ` [PATCH 3/4] arm64: tegra: Add audio support for Jetson Orin NX and Jetson Orin Nano Sheetal .
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Sheetal . @ 2024-02-07 12:05 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, devicetree, linux-kernel
Cc: thierry.reding, linux-tegra, spujar, jonathanh, mkumard, sheetal
From: sheetal <sheetal@nvidia.com>
I2S3, I2S5, DMIC1, DMIC2, DMIC4, DSPK1 and DSPK2 IO ports are not
defined. Those are not defined earlier because it was inside platform
DT and defined only for supported IOs by the platform.
Now these are part of SoC DTSI, all IOs ports are defined
so that all the ports are available to be used by platforms.
Signed-off-by: sheetal <sheetal@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 205 +++++++++++++++++++++++
1 file changed, 205 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index a01ff6174f74..561d01dfef56 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -272,6 +272,28 @@ tegra_i2s3: i2s@2901200 {
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S3";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s3_cif: endpoint {
+ remote-endpoint = <&xbar_i2s3>;
+ };
+ };
+
+ i2s3_port: port@1 {
+ reg = <1>;
+
+ i2s3_dap: endpoint {
+ dai-format = "i2s";
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_i2s4: i2s@2901300 {
@@ -322,6 +344,28 @@ tegra_i2s5: i2s@2901400 {
assigned-clock-rates = <1536000>;
sound-name-prefix = "I2S5";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s5_cif: endpoint {
+ remote-endpoint = <&xbar_i2s5>;
+ };
+ };
+
+ i2s5_port: port@1 {
+ reg = <1>;
+
+ i2s5_dap: endpoint {
+ dai-format = "i2s";
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_i2s6: i2s@2901500 {
@@ -900,6 +944,27 @@ tegra_dmic1: dmic@2904000 {
assigned-clock-rates = <3072000>;
sound-name-prefix = "DMIC1";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic1_cif: endpoint {
+ remote-endpoint = <&xbar_dmic1>;
+ };
+ };
+
+ dmic1_port: port@1 {
+ reg = <1>;
+
+ dmic1_dap: endpoint {
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_dmic2: dmic@2904100 {
@@ -913,6 +978,27 @@ tegra_dmic2: dmic@2904100 {
assigned-clock-rates = <3072000>;
sound-name-prefix = "DMIC2";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic2_cif: endpoint {
+ remote-endpoint = <&xbar_dmic2>;
+ };
+ };
+
+ dmic2_port: port@1 {
+ reg = <1>;
+
+ dmic2_dap: endpoint {
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_dmic3: dmic@2904200 {
@@ -960,6 +1046,27 @@ tegra_dmic4: dmic@2904300 {
assigned-clock-rates = <3072000>;
sound-name-prefix = "DMIC4";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic4_cif: endpoint {
+ remote-endpoint = <&xbar_dmic4>;
+ };
+ };
+
+ dmic4_port: port@1 {
+ reg = <1>;
+
+ dmic4_dap: endpoint {
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_dspk1: dspk@2905000 {
@@ -973,6 +1080,27 @@ tegra_dspk1: dspk@2905000 {
assigned-clock-rates = <12288000>;
sound-name-prefix = "DSPK1";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk1_cif: endpoint {
+ remote-endpoint = <&xbar_dspk1>;
+ };
+ };
+
+ dspk1_port: port@1 {
+ reg = <1>;
+
+ dspk1_dap: endpoint {
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_dspk2: dspk@2905100 {
@@ -986,6 +1114,27 @@ tegra_dspk2: dspk@2905100 {
assigned-clock-rates = <12288000>;
sound-name-prefix = "DSPK2";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk2_cif: endpoint {
+ remote-endpoint = <&xbar_dspk2>;
+ };
+ };
+
+ dspk2_port: port@1 {
+ reg = <1>;
+
+ dspk2_dap: endpoint {
+ /* placeholder for external codec */
+ };
+ };
+ };
};
tegra_ope1: processing-engine@2908000 {
@@ -1746,6 +1895,14 @@ xbar_i2s2: endpoint {
};
};
+ xbar_i2s3_port: port@16 {
+ reg = <0x16>;
+
+ xbar_i2s3: endpoint {
+ remote-endpoint = <&i2s3_cif>;
+ };
+ };
+
xbar_i2s4_port: port@17 {
reg = <0x17>;
@@ -1754,6 +1911,14 @@ xbar_i2s4: endpoint {
};
};
+ xbar_i2s5_port: port@18 {
+ reg = <0x18>;
+
+ xbar_i2s5: endpoint {
+ remote-endpoint = <&i2s5_cif>;
+ };
+ };
+
xbar_i2s6_port: port@19 {
reg = <0x19>;
@@ -1762,6 +1927,22 @@ xbar_i2s6: endpoint {
};
};
+ xbar_dmic1_port: port@1a {
+ reg = <0x1a>;
+
+ xbar_dmic1: endpoint {
+ remote-endpoint = <&dmic1_cif>;
+ };
+ };
+
+ xbar_dmic2_port: port@1b {
+ reg = <0x1b>;
+
+ xbar_dmic2: endpoint {
+ remote-endpoint = <&dmic2_cif>;
+ };
+ };
+
xbar_dmic3_port: port@1c {
reg = <0x1c>;
@@ -1770,6 +1951,30 @@ xbar_dmic3: endpoint {
};
};
+ xbar_dmic4_port: port@1d {
+ reg = <0x1d>;
+
+ xbar_dmic4: endpoint {
+ remote-endpoint = <&dmic4_cif>;
+ };
+ };
+
+ xbar_dspk1_port: port@1e {
+ reg = <0x1e>;
+
+ xbar_dspk1: endpoint {
+ remote-endpoint = <&dspk1_cif>;
+ };
+ };
+
+ xbar_dspk2_port: port@1f {
+ reg = <0x1f>;
+
+ xbar_dspk2: endpoint {
+ remote-endpoint = <&dspk2_cif>;
+ };
+ };
+
xbar_sfc1_in_port: port@20 {
reg = <0x20>;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/4] arm64: tegra: Add audio support for Jetson Orin NX and Jetson Orin Nano
2024-02-07 12:05 [PATCH 0/4] Add audio support for Jetson Orin NX and Jetson Sheetal .
2024-02-07 12:05 ` [PATCH 1/4] arm64: tegra: Move AHUB ports to SoC DTSI Sheetal .
2024-02-07 12:05 ` [PATCH 2/4] arm64: tegra: Define missing IO ports Sheetal .
@ 2024-02-07 12:05 ` Sheetal .
2024-02-07 12:05 ` [PATCH 4/4] arm64: tegra: Remove Jetson Orin NX and Jetson Orin Nano DTSI Sheetal .
2024-02-22 17:24 ` [PATCH 0/4] Add audio support for Jetson Orin NX and Jetson Thierry Reding
4 siblings, 0 replies; 6+ messages in thread
From: Sheetal . @ 2024-02-07 12:05 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, devicetree, linux-kernel
Cc: thierry.reding, linux-tegra, spujar, jonathanh, mkumard, sheetal
From: sheetal <sheetal@nvidia.com>
Add audio support for the NVIDIA Jetson Orin NX (p3767, SKU0) module and
Jetson Orin Nano (p3767, SKU5) module Developer Kit with P3768 carrier
board.
APE and HDA sound cards are enabled.
Supported IO interfaces: I2S2 and I2S4.
Signed-off-by: sheetal <sheetal@nvidia.com>
---
.../arm64/boot/dts/nvidia/tegra234-p3767.dtsi | 82 +++++++++++++++++++
.../nvidia/tegra234-p3768-0000+p3767-0000.dts | 5 +-
.../nvidia/tegra234-p3768-0000+p3767-0005.dts | 10 +++
3 files changed, 96 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi
index 59c14ded5e9f..1b23d37e4463 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi
@@ -6,6 +6,30 @@ / {
compatible = "nvidia,p3767", "nvidia,tegra234";
bus@0 {
+ aconnect@2900000 {
+ status = "okay";
+
+ ahub@2900800 {
+ status = "okay";
+
+ i2s@2901100 {
+ status = "okay";
+ };
+
+ i2s@2901300 {
+ status = "okay";
+ };
+ };
+
+ dma-controller@2930000 {
+ status = "okay";
+ };
+
+ interrupt-controller@2a40000 {
+ status = "okay";
+ };
+ };
+
i2c@3160000 {
status = "okay";
@@ -127,6 +151,64 @@ vdd_3v3_ao: regulator-vdd-3v3-ao {
vin-supply = <&vdd_5v0_sys>;
};
+ sound {
+ compatible = "nvidia,tegra186-audio-graph-card";
+ status = "okay";
+
+ dais = /* ADMAIF (FE) Ports */
+ <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+ <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
+ <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
+ <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
+ <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
+ /* XBAR Ports */
+ <&xbar_i2s2_port>, <&xbar_i2s4_port>,
+ <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
+ <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
+ <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
+ <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
+ <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
+ <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
+ <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
+ <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
+ <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
+ <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
+ <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
+ <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
+ <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
+ <&xbar_mix_in1_port>, <&xbar_mix_in2_port>,
+ <&xbar_mix_in3_port>, <&xbar_mix_in4_port>,
+ <&xbar_mix_in5_port>, <&xbar_mix_in6_port>,
+ <&xbar_mix_in7_port>, <&xbar_mix_in8_port>,
+ <&xbar_mix_in9_port>, <&xbar_mix_in10_port>,
+ <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
+ <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
+ <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
+ <&xbar_asrc_in7_port>,
+ <&xbar_ope1_in_port>,
+ /* HW accelerators */
+ <&sfc1_out_port>, <&sfc2_out_port>,
+ <&sfc3_out_port>, <&sfc4_out_port>,
+ <&mvc1_out_port>, <&mvc2_out_port>,
+ <&amx1_out_port>, <&amx2_out_port>,
+ <&amx3_out_port>, <&amx4_out_port>,
+ <&adx1_out1_port>, <&adx1_out2_port>,
+ <&adx1_out3_port>, <&adx1_out4_port>,
+ <&adx2_out1_port>, <&adx2_out2_port>,
+ <&adx2_out3_port>, <&adx2_out4_port>,
+ <&adx3_out1_port>, <&adx3_out2_port>,
+ <&adx3_out3_port>, <&adx3_out4_port>,
+ <&adx4_out1_port>, <&adx4_out2_port>,
+ <&adx4_out3_port>, <&adx4_out4_port>,
+ <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>,
+ <&mix_out4_port>, <&mix_out5_port>,
+ <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
+ <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+ <&ope1_out_port>,
+ /* BE I/O Ports */
+ <&i2s2_port>, <&i2s4_port>;
+ };
+
thermal-zones {
tj-thermal {
polling-delay = <1000>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts
index 61b0e69d3d20..4c75dc940e99 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts
@@ -37,7 +37,6 @@ pwm@32a0000 {
hda@3510000 {
nvidia,model = "NVIDIA Jetson Orin NX HDA";
- status = "okay";
};
padctl@3520000 {
@@ -85,6 +84,10 @@ vdd_3v3_pcie: regulator-vdd-3v3-pcie {
enable-active-high;
};
+ sound {
+ label = "NVIDIA Jetson Orin NX APE";
+ };
+
thermal-zones {
tj-thermal {
cooling-maps {
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts
index 9e9bb9ca8be4..ba949203eba0 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts
@@ -11,10 +11,20 @@ / {
compatible = "nvidia,p3768-0000+p3767-0005", "nvidia,p3767-0005", "nvidia,tegra234";
model = "NVIDIA Jetson Orin Nano Developer Kit";
+ bus@0 {
+ hda@3510000 {
+ nvidia,model = "NVIDIA Jetson Orin Nano HDA";
+ };
+ };
+
pwm-fan {
cooling-levels = <0 88 187 255>;
};
+ sound {
+ label = "NVIDIA Jetson Orin Nano APE";
+ };
+
thermal-zones {
tj-thermal {
cooling-maps {
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/4] arm64: tegra: Remove Jetson Orin NX and Jetson Orin Nano DTSI
2024-02-07 12:05 [PATCH 0/4] Add audio support for Jetson Orin NX and Jetson Sheetal .
` (2 preceding siblings ...)
2024-02-07 12:05 ` [PATCH 3/4] arm64: tegra: Add audio support for Jetson Orin NX and Jetson Orin Nano Sheetal .
@ 2024-02-07 12:05 ` Sheetal .
2024-02-22 17:24 ` [PATCH 0/4] Add audio support for Jetson Orin NX and Jetson Thierry Reding
4 siblings, 0 replies; 6+ messages in thread
From: Sheetal . @ 2024-02-07 12:05 UTC (permalink / raw)
To: robh+dt, krzysztof.kozlowski+dt, devicetree, linux-kernel
Cc: thierry.reding, linux-tegra, spujar, jonathanh, mkumard, sheetal
From: sheetal <sheetal@nvidia.com>
Jetson Orin NX and Jetson Orin Nano DTSI files just define the HDA label
and it is already added as part of base DTS files.
Hence, removing these files.
Signed-off-by: sheetal <sheetal@nvidia.com>
---
.../arm64/boot/dts/nvidia/tegra234-p3767-0000.dtsi | 14 --------------
.../arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi | 14 --------------
.../dts/nvidia/tegra234-p3768-0000+p3767-0000.dts | 2 +-
.../dts/nvidia/tegra234-p3768-0000+p3767-0005.dts | 2 +-
4 files changed, 2 insertions(+), 30 deletions(-)
delete mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3767-0000.dtsi
delete mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767-0000.dtsi
deleted file mode 100644
index baf4f69e410d..000000000000
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3767-0000.dtsi
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include "tegra234-p3767.dtsi"
-
-/ {
- compatible = "nvidia,p3767-0000", "nvidia,tegra234";
- model = "NVIDIA Jetson Orin NX";
-
- bus@0 {
- hda@3510000 {
- nvidia,model = "NVIDIA Jetson Orin NX HDA";
- };
- };
-};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi
deleted file mode 100644
index 232fa95ef4ae..000000000000
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include "tegra234-p3767.dtsi"
-
-/ {
- compatible = "nvidia,p3767-0005", "nvidia,tegra234";
- model = "NVIDIA Jetson Orin Nano";
-
- bus@0 {
- hda@3510000 {
- nvidia,model = "NVIDIA Jetson Orin Nano HDA";
- };
- };
-};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts
index 4c75dc940e99..1607ee14216f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts
@@ -4,7 +4,7 @@
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/input/gpio-keys.h>
-#include "tegra234-p3767-0000.dtsi"
+#include "tegra234-p3767.dtsi"
#include "tegra234-p3768-0000.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts
index ba949203eba0..dc2d4bef1e83 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts
@@ -4,7 +4,7 @@
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/input/gpio-keys.h>
-#include "tegra234-p3767-0005.dtsi"
+#include "tegra234-p3767.dtsi"
#include "tegra234-p3768-0000.dtsi"
/ {
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 0/4] Add audio support for Jetson Orin NX and Jetson
2024-02-07 12:05 [PATCH 0/4] Add audio support for Jetson Orin NX and Jetson Sheetal .
` (3 preceding siblings ...)
2024-02-07 12:05 ` [PATCH 4/4] arm64: tegra: Remove Jetson Orin NX and Jetson Orin Nano DTSI Sheetal .
@ 2024-02-22 17:24 ` Thierry Reding
4 siblings, 0 replies; 6+ messages in thread
From: Thierry Reding @ 2024-02-22 17:24 UTC (permalink / raw)
To: Sheetal ., robh+dt, krzysztof.kozlowski+dt, devicetree,
linux-kernel
Cc: linux-tegra, spujar, jonathanh, mkumard
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On Wed Feb 7, 2024 at 1:05 PM CET, Sheetal . wrote:
> From: sheetal <sheetal@nvidia.com>
>
> - Move ports from platform DTS to SoC DTSI.
> - Define missing IO ports in SoC DTSI.
> - Add audio support for Jetson Orin NX (p3767 SKU0) module and Jetson
> Orin Nano (p3767 SKU5) module with p3768 carrier board.
> - Remove the module specific DTSI files as it is already taken
> care in base DTS file.
>
> sheetal (4):
> arm64: tegra: Move AHUB ports to SoC DTSI
> arm64: tegra: Define missing IO ports
> arm64: tegra: Add audio support for Jetson Orin NX and Jetson Orin
> Nano
> arm64: tegra: Remove Jetson Orin NX and Jetson Orin Nano DTSI
>
> .../arm64/boot/dts/nvidia/tegra234-p3701.dtsi | 1948 ---------------
> .../boot/dts/nvidia/tegra234-p3767-0000.dtsi | 14 -
> .../boot/dts/nvidia/tegra234-p3767-0005.dtsi | 14 -
> .../arm64/boot/dts/nvidia/tegra234-p3767.dtsi | 82 +
> .../nvidia/tegra234-p3768-0000+p3767-0000.dts | 7 +-
> .../nvidia/tegra234-p3768-0000+p3767-0005.dts | 12 +-
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2122 ++++++++++++++++-
> 7 files changed, 2198 insertions(+), 2001 deletions(-)
> delete mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3767-0000.dtsi
> delete mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3767-0005.dtsi
Applied, thanks.
Thierry
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^ permalink raw reply [flat|nested] 6+ messages in thread