From: "Nicholas Piggin" <npiggin@gmail.com>
To: "BALATON Zoltan" <balaton@eik.bme.hu>, <qemu-devel@nongnu.org>,
<qemu-ppc@nongnu.org>
Cc: "Daniel Henrique Barboza" <danielhb413@gmail.com>
Subject: Re: [PATCH v2 23/28] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate()
Date: Tue, 07 May 2024 21:51:28 +1000 [thread overview]
Message-ID: <D13E2M3CRFEZ.2CW6QQE6KSL31@gmail.com> (raw)
In-Reply-To: <d0a46ea05b85367f763506bbe12a8e9e146cdab5.1714606359.git.balaton@eik.bme.hu>
On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
> reduce ppc_jumbo_xlate() further.
Nice.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> target/ppc/mmu_common.c | 180 ++++++++++++++++++++++++++++++----------
> 1 file changed, 138 insertions(+), 42 deletions(-)
>
> diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
> index 0ce5c1e841..a1f98f8de4 100644
> --- a/target/ppc/mmu_common.c
> +++ b/target/ppc/mmu_common.c
> @@ -1250,6 +1250,137 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
> env->spr[SPR_BOOKE_MAS0] |= env->last_way << MAS0_NV_SHIFT;
> }
>
> +static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
> + MMUAccessType access_type,
> + hwaddr *raddrp, int *psizep, int *protp,
> + int mmu_idx, bool guest_visible)
> +{
> + CPUState *cs = CPU(cpu);
> + CPUPPCState *env = &cpu->env;
> + mmu_ctx_t ctx;
> + int ret;
> +
> + if (env->mmu_model == POWERPC_MMU_BOOKE206) {
> + ret = mmubooke206_get_physical_address(env, &ctx, eaddr, access_type,
> + mmu_idx);
> + } else {
> + ret = mmubooke_get_physical_address(env, &ctx, eaddr, access_type);
> + }
> + if (ret == 0) {
> + *raddrp = ctx.raddr;
> + *protp = ctx.prot;
> + *psizep = TARGET_PAGE_BITS;
> + return true;
> + } else if (!guest_visible) {
> + return false;
> + }
> +
> + log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
> + if (access_type == MMU_INST_FETCH) {
> + switch (ret) {
> + case -1:
> + /* No matches in page tables or TLB */
> + switch (env->mmu_model) {
> + case POWERPC_MMU_BOOKE206:
> + booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> + /* fall through */
> + case POWERPC_MMU_BOOKE:
> + cs->exception_index = POWERPC_EXCP_ITLB;
> + env->error_code = 0;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + break;
> + case -2:
> + /* Access rights violation */
> + cs->exception_index = POWERPC_EXCP_ISI;
> + env->error_code = 0;
> + break;
> + case -3:
> + /* No execute protection violation */
> + cs->exception_index = POWERPC_EXCP_ISI;
> + env->spr[SPR_BOOKE_ESR] = 0;
> + env->error_code = 0;
> + break;
> + case -4:
> + /* Direct store exception */
> + /* No code fetch is allowed in direct-store areas */
> + cs->exception_index = POWERPC_EXCP_ISI;
> + env->error_code = 0;
> + break;
I don't think BookE has -4 (direct address translation) areas, it's
only 6xx by the looks.
You could put another patch before this to remove the BOOKE tests
from the ret == -4 cases, then avoid copying them in here.
Otherwise I think it looks okay.
Thanks,
Nick
> + }
> + } else {
> + switch (ret) {
> + case -1:
> + /* No matches in page tables or TLB */
> + switch (env->mmu_model) {
> + case POWERPC_MMU_BOOKE206:
> + booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> + /* fall through */
> + case POWERPC_MMU_BOOKE:
> + cs->exception_index = POWERPC_EXCP_DTLB;
> + env->error_code = 0;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + break;
> + case -2:
> + /* Access rights violation */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + env->error_code = 0;
> + env->spr[SPR_BOOKE_DEAR] = eaddr;
> + env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> + break;
> + case -4:
> + /* Direct store exception */
> + switch (env->access_type) {
> + case ACCESS_FLOAT:
> + /* Floating point load/store */
> + cs->exception_index = POWERPC_EXCP_ALIGN;
> + env->error_code = POWERPC_EXCP_ALIGN_FP;
> + env->spr[SPR_DAR] = eaddr;
> + break;
> + case ACCESS_RES:
> + /* lwarx, ldarx or stwcx. */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + env->error_code = 0;
> + env->spr[SPR_DAR] = eaddr;
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_DSISR] = 0x06000000;
> + } else {
> + env->spr[SPR_DSISR] = 0x04000000;
> + }
> + break;
> + case ACCESS_EXT:
> + /* eciwx or ecowx */
> + cs->exception_index = POWERPC_EXCP_DSI;
> + env->error_code = 0;
> + env->spr[SPR_DAR] = eaddr;
> + if (access_type == MMU_DATA_STORE) {
> + env->spr[SPR_DSISR] = 0x06100000;
> + } else {
> + env->spr[SPR_DSISR] = 0x04100000;
> + }
> + break;
> + default:
> + printf("DSI: invalid exception (%d)\n", ret);
> + cs->exception_index = POWERPC_EXCP_PROGRAM;
> + env->error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
> + env->spr[SPR_DAR] = eaddr;
> + break;
> + }
> + break;
> + }
> + }
> + return false;
> +}
> +
> /* Perform address translation */
> /* TODO: Split this by mmu_model. */
> static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> @@ -1302,15 +1433,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> env->spr[SPR_40x_DEAR] = eaddr;
> env->spr[SPR_40x_ESR] = 0x00000000;
> break;
> - case POWERPC_MMU_BOOKE206:
> - booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> - /* fall through */
> - case POWERPC_MMU_BOOKE:
> - cs->exception_index = POWERPC_EXCP_ITLB;
> - env->error_code = 0;
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> - break;
> case POWERPC_MMU_REAL:
> cpu_abort(cs, "PowerPC in real mode should never raise "
> "any MMU exceptions\n");
> @@ -1321,34 +1443,18 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> case -2:
> /* Access rights violation */
> cs->exception_index = POWERPC_EXCP_ISI;
> - if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> - (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> - env->error_code = 0;
> - } else {
> - env->error_code = 0x08000000;
> - }
> + env->error_code = 0x08000000;
> break;
> case -3:
> /* No execute protection violation */
> - if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> - (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> - env->spr[SPR_BOOKE_ESR] = 0x00000000;
> - env->error_code = 0;
> - } else {
> - env->error_code = 0x10000000;
> - }
> cs->exception_index = POWERPC_EXCP_ISI;
> + env->error_code = 0x10000000;
> break;
> case -4:
> /* Direct store exception */
> /* No code fetch is allowed in direct-store areas */
> cs->exception_index = POWERPC_EXCP_ISI;
> - if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> - (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> - env->error_code = 0;
> - } else {
> - env->error_code = 0x10000000;
> - }
> + env->error_code = 0x10000000;
> break;
> }
> } else {
> @@ -1383,15 +1489,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> env->spr[SPR_40x_ESR] = 0x00000000;
> }
> break;
> - case POWERPC_MMU_BOOKE206:
> - booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
> - /* fall through */
> - case POWERPC_MMU_BOOKE:
> - cs->exception_index = POWERPC_EXCP_DTLB;
> - env->error_code = 0;
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> - break;
> case POWERPC_MMU_REAL:
> cpu_abort(cs, "PowerPC in real mode should never raise "
> "any MMU exceptions\n");
> @@ -1408,10 +1505,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
> if (access_type == MMU_DATA_STORE) {
> env->spr[SPR_40x_ESR] |= 0x00800000;
> }
> - } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> - (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> - env->spr[SPR_BOOKE_DEAR] = eaddr;
> - env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
> } else {
> env->spr[SPR_DAR] = eaddr;
> if (access_type == MMU_DATA_STORE) {
> @@ -1490,7 +1583,10 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
> case POWERPC_MMU_32B:
> return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp,
> psizep, protp, mmu_idx, guest_visible);
> -
> + case POWERPC_MMU_BOOKE:
> + case POWERPC_MMU_BOOKE206:
> + return ppc_booke_xlate(cpu, eaddr, access_type, raddrp,
> + psizep, protp, mmu_idx, guest_visible);
> default:
> return ppc_jumbo_xlate(cpu, eaddr, access_type, raddrp,
> psizep, protp, mmu_idx, guest_visible);
next prev parent reply other threads:[~2024-05-07 11:52 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-01 23:43 [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 01/28] target/ppc: Fix gen_sc to use correct nip BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 02/28] target/ppc: Move patching nip from exception handler to helper_scv BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 03/28] target/ppc: Simplify syscall exception handlers BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 04/28] target/ppc: Remove unused helper BALATON Zoltan
2024-05-07 9:18 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 05/28] target/ppc/mmu_common.c: Move calculation of a value closer to its usage BALATON Zoltan
2024-05-07 9:19 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 06/28] " BALATON Zoltan
2024-05-07 9:20 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 07/28] target/ppc/mmu_common.c: Remove unneeded local variable BALATON Zoltan
2024-05-07 9:30 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 08/28] target/ppc/mmu_common.c: Simplify checking for real mode BALATON Zoltan
2024-05-07 9:34 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 09/28] target/ppc/mmu_common.c: Drop cases for unimplemented MPC8xx MMU BALATON Zoltan
2024-05-07 9:36 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 10/28] target/ppc/mmu_common.c: Introduce mmu6xx_get_physical_address() BALATON Zoltan
2024-05-07 9:42 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 11/28] target/ppc/mmu_common.c: Rename get_bat_6xx_tlb() BALATON Zoltan
2024-05-07 9:43 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 12/28] target/ppc/mmu_common.c: Split out BookE cases before checking real mode BALATON Zoltan
2024-05-07 9:50 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 13/28] target/ppc/mmu_common.c: Split off real mode cases in get_physical_address_wtlb() BALATON Zoltan
2024-05-07 9:58 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 14/28] target/ppc/mmu_common.c: Inline and remove check_physical() BALATON Zoltan
2024-05-07 10:00 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 15/28] target/ppc/mmu_common.c: Simplify mmubooke_get_physical_address() BALATON Zoltan
2024-05-07 10:03 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 16/28] target/ppc/mmu_common.c: Simplify mmubooke206_get_physical_address() BALATON Zoltan
2024-05-07 10:04 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 17/28] target/ppc/mmu_common.c: Fix misindented qemu_log_mask() calls BALATON Zoltan
2024-05-07 10:05 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 18/28] target/ppc/mmu_common.c: Deindent ppc_jumbo_xlate() BALATON Zoltan
2024-05-07 10:06 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 19/28] target/ppc/mmu_common.c: Replace hard coded constants in ppc_jumbo_xlate() BALATON Zoltan
2024-05-07 10:11 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 20/28] target/ppc/mmu_common.c: Make get_physical_address_wtlb() static BALATON Zoltan
2024-05-07 10:47 ` Nicholas Piggin
2024-05-07 15:31 ` BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 21/28] target/ppc: Move mmu_ctx_t definition to mmu_common.c BALATON Zoltan
2024-05-07 10:49 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 22/28] target/ppc: Remove ppc_hash32_pp_prot() and reuse common function BALATON Zoltan
2024-05-07 11:35 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 23/28] target/ppc/mmu_common.c: Split off BookE handling from ppc_jumbo_xlate() BALATON Zoltan
2024-05-07 11:51 ` Nicholas Piggin [this message]
2024-05-01 23:43 ` [PATCH v2 24/28] target/ppc/mmu_common.c: Remove BookE handling from get_physical_address_wtlb() BALATON Zoltan
2024-05-07 12:05 ` Nicholas Piggin
2024-05-07 23:40 ` BALATON Zoltan
2024-05-08 12:54 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 25/28] target/ppc/mmu_common.c: Simplify ppc_booke_xlate() BALATON Zoltan
2024-05-07 12:15 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 26/28] target/ppc/mmu_common.c: Move BookE MMU functions together BALATON Zoltan
2024-05-07 12:17 ` Nicholas Piggin
2024-05-07 12:31 ` BALATON Zoltan
2024-05-08 12:30 ` Nicholas Piggin
2024-05-08 23:33 ` BALATON Zoltan
2024-05-09 5:57 ` Nicholas Piggin
2024-05-07 15:54 ` BALATON Zoltan
2024-05-01 23:43 ` [PATCH v2 27/28] target/ppc: Remove id_tlbs flag from CPU env BALATON Zoltan
2024-05-07 12:30 ` Nicholas Piggin
2024-05-07 16:02 ` BALATON Zoltan
2024-05-08 12:37 ` Nicholas Piggin
2024-05-01 23:43 ` [PATCH v2 28/28] target/ppc: Split off common 4xx TLB init BALATON Zoltan
2024-05-07 12:40 ` Nicholas Piggin
2024-05-07 12:45 ` [PATCH v2 00/28] Misc PPC exception and BookE MMU clean ups Nicholas Piggin
2024-05-07 12:51 ` BALATON Zoltan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=D13E2M3CRFEZ.2CW6QQE6KSL31@gmail.com \
--to=npiggin@gmail.com \
--cc=balaton@eik.bme.hu \
--cc=danielhb413@gmail.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.