Re: [PATCH v2 28/28] target/ppc: Split off common 4xx TLB init

["Nicholas Piggin" <npiggin@gmail.com>]

On Thu May 2, 2024 at 9:43 AM AEST, BALATON Zoltan wrote:
> Several 4xx related CPUs have the same TLB settings. Split it off in a
> common function in cpu_init.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
>  target/ppc/cpu_init.c | 46 ++++++++++++++++---------------------------
>  1 file changed, 17 insertions(+), 29 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 07ad788e54..d7e85c1b07 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -2107,18 +2107,22 @@ static int check_pow_hid0_74xx(CPUPPCState *env)
>      return 0;
>  }
>  
> +static void init_tlbs_4xx(CPUPPCState *env)
> +{
> +#ifndef CONFIG_USER_ONLY
> +    env->nb_tlb = 64;
> +    env->nb_ways = 1;
> +    env->tlb_type = TLB_EMB;
> +#endif
> +}

e200 isn't 4xx though is it? Call it init_TLB_EMB()?

Otherwise,

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>

Thanks,
Nick

> +
>  static void init_proc_405(CPUPPCState *env)
>  {
>      register_40x_sprs(env);
>      register_405_sprs(env);
>      register_usprgh_sprs(env);
>  
> -    /* Memory management */
> -#if !defined(CONFIG_USER_ONLY)
> -    env->nb_tlb = 64;
> -    env->nb_ways = 1;
> -    env->tlb_type = TLB_EMB;
> -#endif
> +    init_tlbs_4xx(env);
>      init_excp_4xx(env);
>      env->dcache_line_size = 32;
>      env->icache_line_size = 32;
> @@ -2185,12 +2189,8 @@ static void init_proc_440EP(CPUPPCState *env)
>                   SPR_NOACCESS, SPR_NOACCESS,
>                   &spr_read_generic, &spr_write_generic,
>                   0x00000000);
> -    /* Memory management */
> -#if !defined(CONFIG_USER_ONLY)
> -    env->nb_tlb = 64;
> -    env->nb_ways = 1;
> -    env->tlb_type = TLB_EMB;
> -#endif
> +
> +    init_tlbs_4xx(env);
>      init_excp_BookE(env);
>      env->dcache_line_size = 32;
>      env->icache_line_size = 32;
> @@ -2282,12 +2282,7 @@ static void init_proc_440GP(CPUPPCState *env)
>      register_440_sprs(env);
>      register_usprgh_sprs(env);
>  
> -    /* Memory management */
> -#if !defined(CONFIG_USER_ONLY)
> -    env->nb_tlb = 64;
> -    env->nb_ways = 1;
> -    env->tlb_type = TLB_EMB;
> -#endif
> +    init_tlbs_4xx(env);
>      init_excp_BookE(env);
>      env->dcache_line_size = 32;
>      env->icache_line_size = 32;
> @@ -2355,12 +2350,8 @@ static void init_proc_440x5(CPUPPCState *env)
>                   SPR_NOACCESS, SPR_NOACCESS,
>                   &spr_read_generic, &spr_write_generic,
>                   0x00000000);
> -    /* Memory management */
> -#if !defined(CONFIG_USER_ONLY)
> -    env->nb_tlb = 64;
> -    env->nb_ways = 1;
> -    env->tlb_type = TLB_EMB;
> -#endif
> +
> +    init_tlbs_4xx(env);
>      init_excp_BookE(env);
>      env->dcache_line_size = 32;
>      env->icache_line_size = 32;
> @@ -2717,11 +2708,8 @@ static void init_proc_e200(CPUPPCState *env)
>                   SPR_NOACCESS, SPR_NOACCESS,
>                   &spr_read_generic, &spr_write_generic,
>                   0x00000000);
> -#if !defined(CONFIG_USER_ONLY)
> -    env->nb_tlb = 64;
> -    env->nb_ways = 1;
> -    env->tlb_type = TLB_EMB;
> -#endif
> +
> +    init_tlbs_4xx(env);
>      init_excp_e200(env, 0xFFFF0000UL);
>      env->dcache_line_size = 32;
>      env->icache_line_size = 32;