From: "Nicholas Piggin" <npiggin@gmail.com>
To: "Cédric Le Goater" <clg@kaod.org>, qemu-ppc@nongnu.org
Cc: "Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
qemu-devel@nongnu.org
Subject: Re: [PATCH v2 03/19] ppc/pnv: Move timebase state into PnvCore
Date: Mon, 15 Jul 2024 16:30:17 +1000 [thread overview]
Message-ID: <D2PWGA4AB747.1I96QV6NN0XVQ@gmail.com> (raw)
In-Reply-To: <050c0324-0886-4848-b7eb-039578561ac1@kaod.org>
On Fri Jul 12, 2024 at 11:40 PM AEST, Cédric Le Goater wrote:
> On 7/12/24 14:02, Nicholas Piggin wrote:
> > diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
> > index 39d397416e..52f9e6669c 100644
> > --- a/target/ppc/timebase_helper.c
> > +++ b/target/ppc/timebase_helper.c
> > @@ -19,6 +19,7 @@
> > #include "qemu/osdep.h"
> > #include "cpu.h"
> > #include "hw/ppc/ppc.h"
> > +#include "hw/ppc/pnv_core.h"
>
> I am afraid this header file is pulling too much definitions for
> qemu-user. It breaks compile.
Humph, sorry I obviously wasn't testing it. I might just ifdef it for
now.
Not sure the best way to do it cleanly in the longer term , Power
specific things could go into their own helper.c file, but I don't
necessarily like to move them away from similar/related functions.
Thanks,
Nick
next prev parent reply other threads:[~2024-07-15 6:31 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-12 12:02 [PATCH v2 00/19] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 01/19] target/ppc: Fix msgsnd for POWER8 Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 02/19] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 03/19] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-07-12 13:40 ` Cédric Le Goater
2024-07-15 6:30 ` Nicholas Piggin [this message]
2024-07-12 12:02 ` [PATCH v2 04/19] target/ppc: Move SPR indirect registers " Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 05/19] ppc/pnv: use class attribute to limit SMT threads for different machines Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 06/19] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 07/19] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 08/19] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 09/19] ppc: Add has_smt_siblings property to CPUPPCState Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 10/19] ppc/pnv: Add a big-core mode that joins two regular cores Nicholas Piggin
2024-07-13 7:19 ` Cédric Le Goater
2024-07-15 6:31 ` Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 11/19] ppc/pnv: Add allow for big-core differences in DT generation Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 12/19] ppc/pnv: Implement big-core PVR for Power9/10 Nicholas Piggin
2024-07-13 7:28 ` Cédric Le Goater
2024-07-12 12:02 ` [PATCH v2 13/19] ppc/pnv: Implement Power9 CPU core thread state indirect register Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 14/19] ppc/pnv: Add POWER10 ChipTOD quirk for big-core Nicholas Piggin
2024-07-13 7:22 ` Cédric Le Goater
2024-07-12 12:02 ` [PATCH v2 15/19] ppc/pnv: Add big-core machine property Nicholas Piggin
2024-07-13 7:24 ` Cédric Le Goater
2024-07-15 6:32 ` Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 16/19] system/cpus: Add cpu_pause() function Nicholas Piggin
2024-07-12 14:35 ` Philippe Mathieu-Daudé
2024-07-12 15:25 ` Peter Xu
2024-07-12 12:02 ` [PATCH v2 17/19] ppc/pnv: Add a CPU nmi and resume function Nicholas Piggin
2024-07-13 7:27 ` Cédric Le Goater
2024-07-12 12:02 ` [PATCH v2 18/19] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 19/19] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-07-13 7:27 ` Cédric Le Goater
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