From: "Nicholas Piggin" <npiggin@gmail.com>
To: "Cédric Le Goater" <clg@kaod.org>, qemu-ppc@nongnu.org
Cc: "Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
qemu-devel@nongnu.org
Subject: Re: [PATCH v2 10/19] ppc/pnv: Add a big-core mode that joins two regular cores
Date: Mon, 15 Jul 2024 16:31:17 +1000 [thread overview]
Message-ID: <D2PWH1VZ9PO2.32WUGZQK6YD2U@gmail.com> (raw)
In-Reply-To: <4f0e918b-336f-4423-bc48-25607662eabc@kaod.org>
On Sat Jul 13, 2024 at 5:19 PM AEST, Cédric Le Goater wrote:
> On 7/12/24 14:02, Nicholas Piggin wrote:
> > POWER9 and POWER10 machines come in two variants, big-core and
> > small-core. Big-core machines are SMT8 from software's point of view,
> > but the low level platform topology ("xscom registers and pervasive
> > addressing"), these look more like a pair of small cores ganged
> > together.
> >
> > Presently the way this is modelled is to create one SMT8 PnvCore and add
> > special cases to xscom and pervasive for big-core mode that tries to
> > split this into two small cores, but this is becoming too complicated to
> > manage.
> >
> > A better approach is to create 2 core structures and ganging them
> > together to look like an SMT8 core in TCG. Then the xscom and pervasive
> > models mostly do not need to differentiate big and small core modes.
> >
> > This change adds initial mode bits and QEMU topology handling to
> > split SMT8 cores into 2xSMT4 cores.
> >
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>
>
> Looks good. See some proposal below,
[snip]
All make sense, thank you will do.
Thnaks,
Nick
next prev parent reply other threads:[~2024-07-15 6:32 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-12 12:02 [PATCH v2 00/19] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 01/19] target/ppc: Fix msgsnd for POWER8 Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 02/19] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 03/19] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-07-12 13:40 ` Cédric Le Goater
2024-07-15 6:30 ` Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 04/19] target/ppc: Move SPR indirect registers " Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 05/19] ppc/pnv: use class attribute to limit SMT threads for different machines Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 06/19] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 07/19] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 08/19] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 09/19] ppc: Add has_smt_siblings property to CPUPPCState Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 10/19] ppc/pnv: Add a big-core mode that joins two regular cores Nicholas Piggin
2024-07-13 7:19 ` Cédric Le Goater
2024-07-15 6:31 ` Nicholas Piggin [this message]
2024-07-12 12:02 ` [PATCH v2 11/19] ppc/pnv: Add allow for big-core differences in DT generation Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 12/19] ppc/pnv: Implement big-core PVR for Power9/10 Nicholas Piggin
2024-07-13 7:28 ` Cédric Le Goater
2024-07-12 12:02 ` [PATCH v2 13/19] ppc/pnv: Implement Power9 CPU core thread state indirect register Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 14/19] ppc/pnv: Add POWER10 ChipTOD quirk for big-core Nicholas Piggin
2024-07-13 7:22 ` Cédric Le Goater
2024-07-12 12:02 ` [PATCH v2 15/19] ppc/pnv: Add big-core machine property Nicholas Piggin
2024-07-13 7:24 ` Cédric Le Goater
2024-07-15 6:32 ` Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 16/19] system/cpus: Add cpu_pause() function Nicholas Piggin
2024-07-12 14:35 ` Philippe Mathieu-Daudé
2024-07-12 15:25 ` Peter Xu
2024-07-12 12:02 ` [PATCH v2 17/19] ppc/pnv: Add a CPU nmi and resume function Nicholas Piggin
2024-07-13 7:27 ` Cédric Le Goater
2024-07-12 12:02 ` [PATCH v2 18/19] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-07-12 12:02 ` [PATCH v2 19/19] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-07-13 7:27 ` Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=D2PWH1VZ9PO2.32WUGZQK6YD2U@gmail.com \
--to=npiggin@gmail.com \
--cc=clg@kaod.org \
--cc=fbarrat@linux.ibm.com \
--cc=harshpb@linux.ibm.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.