Re: [PATCH v2 01/14] ppc/xive2: Update NVP save/restore for group attributes

["Nicholas Piggin" <npiggin@gmail.com>]

On Tue Dec 10, 2024 at 10:05 AM AEST, Michael Kowal wrote:
> From: Frederic Barrat <fbarrat@linux.ibm.com>
>
> If the 'H' attribute is set on the NVP structure, the hardware
> automatically saves and restores some attributes from the TIMA in the
> NVP structure.
> The group-specific attributes LSMFB, LGS and T have an extra flag to
> individually control what is saved/restored.
>
> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
> Signed-off-by: Michael Kowal <kowal@linux.ibm.com>

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>

> ---
>  include/hw/ppc/xive2_regs.h | 10 +++++++---
>  hw/intc/xive2.c             | 23 ++++++++++++++++++-----
>  2 files changed, 25 insertions(+), 8 deletions(-)
>
> diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
> index 1d00c8df64..e88d6eab1e 100644
> --- a/include/hw/ppc/xive2_regs.h
> +++ b/include/hw/ppc/xive2_regs.h
> @@ -1,10 +1,9 @@
>  /*
>   * QEMU PowerPC XIVE2 internal structure definitions (POWER10)
>   *
> - * Copyright (c) 2019-2022, IBM Corporation.
> + * Copyright (c) 2019-2024, IBM Corporation.
>   *
> - * This code is licensed under the GPL version 2 or later. See the
> - * COPYING file in the top-level directory.
> + * SPDX-License-Identifier: GPL-2.0-or-later
>   */
>  
>  #ifndef PPC_XIVE2_REGS_H
> @@ -152,6 +151,9 @@ typedef struct Xive2Nvp {
>          uint32_t       w0;
>  #define NVP2_W0_VALID              PPC_BIT32(0)
>  #define NVP2_W0_HW                 PPC_BIT32(7)
> +#define NVP2_W0_L                  PPC_BIT32(8)
> +#define NVP2_W0_G                  PPC_BIT32(9)
> +#define NVP2_W0_T                  PPC_BIT32(10)
>  #define NVP2_W0_ESC_END            PPC_BIT32(25) /* 'N' bit 0:ESB  1:END */
>  #define NVP2_W0_PGOFIRST           PPC_BITMASK32(26, 31)
>          uint32_t       w1;
> @@ -163,6 +165,8 @@ typedef struct Xive2Nvp {
>  #define NVP2_W2_CPPR               PPC_BITMASK32(0, 7)
>  #define NVP2_W2_IPB                PPC_BITMASK32(8, 15)
>  #define NVP2_W2_LSMFB              PPC_BITMASK32(16, 23)
> +#define NVP2_W2_T                  PPC_BIT32(27)
> +#define NVP2_W2_LGS                PPC_BITMASK32(28, 31)
>          uint32_t       w3;
>          uint32_t       w4;
>  #define NVP2_W4_ESC_ESB_BLOCK      PPC_BITMASK32(0, 3)  /* N:0 */
> diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
> index d1df35e9b3..24e504fce1 100644
> --- a/hw/intc/xive2.c
> +++ b/hw/intc/xive2.c
> @@ -1,10 +1,9 @@
>  /*
>   * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
>   *
> - * Copyright (c) 2019-2022, IBM Corporation..
> + * Copyright (c) 2019-2024, IBM Corporation..
>   *
> - * This code is licensed under the GPL version 2 or later. See the
> - * COPYING file in the top-level directory.
> + * SPDX-License-Identifier: GPL-2.0-or-later
>   */
>  
>  #include "qemu/osdep.h"
> @@ -313,7 +312,19 @@ static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
>  
>      nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]);
>      nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]);
> -    nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]);
> +    if (nvp.w0 & NVP2_W0_L) {
> +        /*
> +         * Typically not used. If LSMFB is restored with 0, it will
> +         * force a backlog rescan
> +         */
> +        nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]);
> +    }
> +    if (nvp.w0 & NVP2_W0_G) {
> +        nvp.w2 = xive_set_field32(NVP2_W2_LGS, nvp.w2, regs[TM_LGS]);
> +    }
> +    if (nvp.w0 & NVP2_W0_T) {
> +        nvp.w2 = xive_set_field32(NVP2_W2_T, nvp.w2, regs[TM_T]);
> +    }
>      xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
>  
>      nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0);
> @@ -527,7 +538,9 @@ static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
>      xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2);
>  
>      tctx->regs[TM_QW1_OS + TM_CPPR] = cppr;
> -    /* we don't model LSMFB */
> +    tctx->regs[TM_QW1_OS + TM_LSMFB] = xive_get_field32(NVP2_W2_LSMFB, nvp->w2);
> +    tctx->regs[TM_QW1_OS + TM_LGS] = xive_get_field32(NVP2_W2_LGS, nvp->w2);
> +    tctx->regs[TM_QW1_OS + TM_T] = xive_get_field32(NVP2_W2_T, nvp->w2);
>  
>      nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1);
>      nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1);