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From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Xu Lu" <luxu.kernel@bytedance.com>, <cleger@rivosinc.com>,
	<anup@brainfault.org>, <atish.patra@linux.dev>,
	<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <alex@ghiti.fr>
Cc: <kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] RISC-V: KVM: Delegate kvm unhandled faults to VS mode
Date: Fri, 11 Jul 2025 08:16:22 +0200	[thread overview]
Message-ID: <DB908AUW6N76.3SYAGIFGCDJ27@ventanamicro.com> (raw)
In-Reply-To: <20250710133030.88940-1-luxu.kernel@bytedance.com>

2025-07-10T21:30:30+08:00, Xu Lu <luxu.kernel@bytedance.com>:
> Delegate faults which are not handled by kvm to VS mode to avoid
> unnecessary traps to HS mode. These faults include illegal instruction
> fault, instruction access fault, load access fault and store access
> fault.
>
> The delegation of illegal instruction fault is particularly important
> to guest applications that use vector instructions frequently. In such
> cases, an illegal instruction fault will be raised when guest user thread
> uses vector instruction the first time and then guest kernel will enable
> user thread to execute following vector instructions.

(This optimization will be even more significant when nesting, where it
 would currently go -> HS0 -> HS1 -> HS0 -> VS1, instead of -> VS1.)

> The fw pmu event counters remain undeleted so that guest can still get
> these events via sbi call. Guest will only see zero count on these
> events and know 'firmware' has delegated these faults.
>
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> ---

Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com>

-- 
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv

WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Xu Lu" <luxu.kernel@bytedance.com>, <cleger@rivosinc.com>,
	<anup@brainfault.org>, <atish.patra@linux.dev>,
	<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <alex@ghiti.fr>
Cc: <kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] RISC-V: KVM: Delegate kvm unhandled faults to VS mode
Date: Fri, 11 Jul 2025 08:16:22 +0200	[thread overview]
Message-ID: <DB908AUW6N76.3SYAGIFGCDJ27@ventanamicro.com> (raw)
In-Reply-To: <20250710133030.88940-1-luxu.kernel@bytedance.com>

2025-07-10T21:30:30+08:00, Xu Lu <luxu.kernel@bytedance.com>:
> Delegate faults which are not handled by kvm to VS mode to avoid
> unnecessary traps to HS mode. These faults include illegal instruction
> fault, instruction access fault, load access fault and store access
> fault.
>
> The delegation of illegal instruction fault is particularly important
> to guest applications that use vector instructions frequently. In such
> cases, an illegal instruction fault will be raised when guest user thread
> uses vector instruction the first time and then guest kernel will enable
> user thread to execute following vector instructions.

(This optimization will be even more significant when nesting, where it
 would currently go -> HS0 -> HS1 -> HS0 -> VS1, instead of -> VS1.)

> The fw pmu event counters remain undeleted so that guest can still get
> these events via sbi call. Guest will only see zero count on these
> events and know 'firmware' has delegated these faults.
>
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> ---

Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com>

WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Xu Lu" <luxu.kernel@bytedance.com>, <cleger@rivosinc.com>,
	<anup@brainfault.org>, <atish.patra@linux.dev>,
	<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <alex@ghiti.fr>
Cc: <kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] RISC-V: KVM: Delegate kvm unhandled faults to VS mode
Date: Fri, 11 Jul 2025 08:16:22 +0200	[thread overview]
Message-ID: <DB908AUW6N76.3SYAGIFGCDJ27@ventanamicro.com> (raw)
In-Reply-To: <20250710133030.88940-1-luxu.kernel@bytedance.com>

2025-07-10T21:30:30+08:00, Xu Lu <luxu.kernel@bytedance.com>:
> Delegate faults which are not handled by kvm to VS mode to avoid
> unnecessary traps to HS mode. These faults include illegal instruction
> fault, instruction access fault, load access fault and store access
> fault.
>
> The delegation of illegal instruction fault is particularly important
> to guest applications that use vector instructions frequently. In such
> cases, an illegal instruction fault will be raised when guest user thread
> uses vector instruction the first time and then guest kernel will enable
> user thread to execute following vector instructions.

(This optimization will be even more significant when nesting, where it
 would currently go -> HS0 -> HS1 -> HS0 -> VS1, instead of -> VS1.)

> The fw pmu event counters remain undeleted so that guest can still get
> these events via sbi call. Guest will only see zero count on these
> events and know 'firmware' has delegated these faults.
>
> Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
> ---

Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com>

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2025-07-11  6:16 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-10 13:30 [PATCH v2] RISC-V: KVM: Delegate kvm unhandled faults to VS mode Xu Lu
2025-07-10 13:30 ` Xu Lu
2025-07-10 13:30 ` Xu Lu
2025-07-11  6:16 ` Radim Krčmář [this message]
2025-07-11  6:16   ` Radim Krčmář
2025-07-11  6:16   ` Radim Krčmář
2025-07-11  8:25   ` [External] " Xu Lu
2025-07-11  8:25     ` Xu Lu
2025-07-11  8:25     ` Xu Lu
2025-07-11  8:28 ` Anup Patel
2025-07-11  8:28   ` Anup Patel
2025-07-11  8:28   ` Anup Patel
2025-07-11  8:57   ` [External] " Xu Lu
2025-07-11  8:57     ` Xu Lu
2025-07-11  8:57     ` Xu Lu

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