* [PATCH -next v7 01/10] mach-k3: use minimal memory map for all K3
2025-09-12 12:16 [PATCH -next v7 00/10] Add support for dynamic MMU configuration Anshul Dalal
@ 2025-09-12 12:16 ` Anshul Dalal
2025-09-12 12:16 ` [PATCH -next v7 02/10] mach-k3: use custom enable_cache Anshul Dalal
` (8 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Anshul Dalal @ 2025-09-12 12:16 UTC (permalink / raw)
To: u-boot
Cc: Anshul Dalal, d-gole, b-padhi, vigneshr, trini, nm, robertcnelson,
w.egorov, francesco.dolcini, ggiordano, m-chawdhry, afd, bb,
u-kumar1, devarsht, ilias.apalodimas
The K3 family of SoCs encompasses a wide variety of devices with varying
DDR configurations and memory carveout requirements, the current static
memory map provides basic support for TI EVMs but does not scale well
for newer platforms (such as AM62SiP with 512MiB of RAM).
Therefore this patch replaces the existing memory map with a minimal
one, that could be more easily modified at runtime.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/mach-k3/arm64/arm64-mmu.c | 32 ++++++++++--------------------
1 file changed, 10 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-k3/arm64/arm64-mmu.c b/arch/arm/mach-k3/arm64/arm64-mmu.c
index 0e07b1b7ce0..79650a7e346 100644
--- a/arch/arm/mach-k3/arm64/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64/arm64-mmu.c
@@ -11,42 +11,30 @@
#include <asm/system.h>
#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
struct mm_region k3_mem_map[] = {
- {
+ { /* SoC Peripherals */
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x1e780000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xa0000000UL,
- .phys = 0xa0000000UL,
- .size = 0x60000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x880000000UL,
- .phys = 0x880000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
+ }, { /* Flash Peripherals */
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x380000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
+ }, { /* First DRAM Bank of size 2G */
+ .virt = CFG_SYS_SDRAM_BASE,
+ .phys = CFG_SYS_SDRAM_BASE,
+ .size = SZ_2G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, { /* List terminator */
0,
}
};
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH -next v7 02/10] mach-k3: use custom enable_cache
2025-09-12 12:16 [PATCH -next v7 00/10] Add support for dynamic MMU configuration Anshul Dalal
2025-09-12 12:16 ` [PATCH -next v7 01/10] mach-k3: use minimal memory map for all K3 Anshul Dalal
@ 2025-09-12 12:16 ` Anshul Dalal
2025-09-12 12:16 ` [PATCH -next v7 03/10] arm: armv8: mmu: export mmu_setup Anshul Dalal
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Anshul Dalal @ 2025-09-12 12:16 UTC (permalink / raw)
To: u-boot
Cc: Anshul Dalal, d-gole, b-padhi, vigneshr, trini, nm, robertcnelson,
w.egorov, francesco.dolcini, ggiordano, m-chawdhry, afd, bb,
u-kumar1, devarsht, ilias.apalodimas
U-Boot's provided enable_caches enforces the following sequence:
icache_enable -> mmu_setup (as part of dcache_enable) -> dcache_enable
Whereas for K3 devices, we would like to add entries to the provided
static array (k3_mem_map) as per gd->bd->bi_dram and then call mmu_setup
to configure the MMU but also create carveouts for TFA/TEE before we
enable caches to prevent speculative accesses to the region. Thus the
following desired sequence:
add dram banks -> mmu_setup -> carveout TFA/TEE -> icache/dcache enable
Therefore this patch adds K3's own implementation of enable_cache for
ARM64, allowing for greater control over the cache enablement sequence.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/mach-k3/common.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 5483ac9906c..7f2a4e6260e 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -258,6 +258,12 @@ void board_prep_linux(struct bootm_headers *images)
ROUND(images->os.end,
CONFIG_SYS_CACHELINE_SIZE));
}
+
+void enable_caches(void)
+{
+ icache_enable();
+ dcache_enable();
+}
#endif
void spl_enable_cache(void)
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH -next v7 03/10] arm: armv8: mmu: export mmu_setup
2025-09-12 12:16 [PATCH -next v7 00/10] Add support for dynamic MMU configuration Anshul Dalal
2025-09-12 12:16 ` [PATCH -next v7 01/10] mach-k3: use minimal memory map for all K3 Anshul Dalal
2025-09-12 12:16 ` [PATCH -next v7 02/10] mach-k3: use custom enable_cache Anshul Dalal
@ 2025-09-12 12:16 ` Anshul Dalal
2025-09-12 12:16 ` [PATCH -next v7 04/10] arm: armv8: invalidate dcache entries on dcache_enable Anshul Dalal
` (6 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Anshul Dalal @ 2025-09-12 12:16 UTC (permalink / raw)
To: u-boot
Cc: Anshul Dalal, d-gole, b-padhi, vigneshr, trini, nm, robertcnelson,
w.egorov, francesco.dolcini, ggiordano, m-chawdhry, afd, bb,
u-kumar1, devarsht, ilias.apalodimas
The mmu_setup function configures the page tables based on the board
supplied mem_map struct array. It is called implicitly as part of
dcache_enable but this limits us to only be able to use APIs such as
mmu_change_region_attr only after caches are enabled.
This might lead to speculative accesses before we can unmap a region
that is marked as cacheable in the static memory map.
Therefore this patch exports the mmu_setup function in mmu.h allowing
users to have more control over when the mmu is configured.
For K3 specifically this allows for the following configuration sequence
as part of enable_caches:
static mem_map fixups (TODO) -> mmu_setup -> carveouts using
mmu_change_region_attr (TODO) -> icache/dcache enable
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/include/asm/armv8/mmu.h | 5 +++++
arch/arm/mach-k3/common.c | 3 +++
2 files changed, 8 insertions(+)
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 6af8cd111a4..3807c702fb6 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -197,6 +197,11 @@ struct mm_region {
extern struct mm_region *mem_map;
void setup_pgtables(void);
u64 get_tcr(u64 *pips, u64 *pva_bits);
+
+/**
+ * mmu_setup() - Sets up the mmu page tables as per mem_map
+ */
+void mmu_setup(void);
#endif
#endif /* _ASM_ARMV8_MMU_H_ */
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 7f2a4e6260e..ea287ba1226 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -30,6 +30,7 @@
#include <soc.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
+#include <asm/armv8/mmu.h>
#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
#define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
@@ -261,6 +262,8 @@ void board_prep_linux(struct bootm_headers *images)
void enable_caches(void)
{
+ mmu_setup();
+
icache_enable();
dcache_enable();
}
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH -next v7 04/10] arm: armv8: invalidate dcache entries on dcache_enable
2025-09-12 12:16 [PATCH -next v7 00/10] Add support for dynamic MMU configuration Anshul Dalal
` (2 preceding siblings ...)
2025-09-12 12:16 ` [PATCH -next v7 03/10] arm: armv8: mmu: export mmu_setup Anshul Dalal
@ 2025-09-12 12:16 ` Anshul Dalal
2025-09-12 12:28 ` Heinrich Schuchardt
2025-09-12 12:16 ` [PATCH -next v7 05/10] arm: armv8: mmu: add mem_map_fix_dram_banks Anshul Dalal
` (5 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Anshul Dalal @ 2025-09-12 12:16 UTC (permalink / raw)
To: u-boot
Cc: Anshul Dalal, d-gole, b-padhi, vigneshr, trini, nm, robertcnelson,
w.egorov, francesco.dolcini, ggiordano, m-chawdhry, afd, bb,
u-kumar1, devarsht, ilias.apalodimas
In dcache_enable, currently the dcache entries are only invalidated when
the MMU is not enabled. This causes issues when dcache_enable is called
with the MMU already configured, in such cases the existing dcache
entries are not flushed which might result in un-expected behavior.
This patch invalidates the cache entries on every call of dcache_enable
before enabling dcache (by setting CR_C). This makes dcache_enable
behave similar to icache_enable as well.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/cpu/armv8/cache_v8.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 1c1e33bec24..6e662395a83 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -830,16 +830,15 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
void dcache_enable(void)
{
/* The data cache is not active unless the mmu is enabled */
- if (!(get_sctlr() & CR_M)) {
- invalidate_dcache_all();
- __asm_invalidate_tlb_all();
+ if (!mmu_status())
mmu_setup();
- }
/* Set up page tables only once (it is done also by mmu_setup()) */
if (!gd->arch.tlb_fillptr)
setup_all_pgtables();
+ invalidate_dcache_all();
+ __asm_invalidate_tlb_all();
set_sctlr(get_sctlr() | CR_C);
}
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH -next v7 04/10] arm: armv8: invalidate dcache entries on dcache_enable
2025-09-12 12:16 ` [PATCH -next v7 04/10] arm: armv8: invalidate dcache entries on dcache_enable Anshul Dalal
@ 2025-09-12 12:28 ` Heinrich Schuchardt
2025-09-15 5:05 ` Anshul Dalal
0 siblings, 1 reply; 14+ messages in thread
From: Heinrich Schuchardt @ 2025-09-12 12:28 UTC (permalink / raw)
To: Anshul Dalal
Cc: d-gole, b-padhi, vigneshr, trini, nm, robertcnelson, w.egorov,
francesco.dolcini, ggiordano, m-chawdhry, afd, bb, u-kumar1,
devarsht, ilias.apalodimas, u-boot
On 9/12/25 14:16, Anshul Dalal wrote:
> In dcache_enable, currently the dcache entries are only invalidated when
> the MMU is not enabled. This causes issues when dcache_enable is called
> with the MMU already configured, in such cases the existing dcache
> entries are not flushed which might result in un-expected behavior.
>
> This patch invalidates the cache entries on every call of dcache_enable
> before enabling dcache (by setting CR_C). This makes dcache_enable
> behave similar to icache_enable as well.
>
> Reviewed-by: Dhruva Gole <d-gole@ti.com>
> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
> Signed-off-by: Anshul Dalal <anshuld@ti.com>
> Tested-by: Wadim Egorov <w.egorov@phytec.de>
> ---
> arch/arm/cpu/armv8/cache_v8.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index 1c1e33bec24..6e662395a83 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -830,16 +830,15 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
> void dcache_enable(void)
> {
> /* The data cache is not active unless the mmu is enabled */
> - if (!(get_sctlr() & CR_M)) {
> - invalidate_dcache_all();
> - __asm_invalidate_tlb_all();
> + if (!mmu_status())
You are changing the logic here without describing why in the commit
message:
mmu_status() returns zero if CONFIG_SYS_ICACHE_OFF=y.
Only for CONFIG_SYS_ICACHE_OFF=n it calls get_sctlr().
Please, check if the logic change is intended.
Please, update the commit message.
Best regards
Heinrich
> mmu_setup();
> - }
>
> /* Set up page tables only once (it is done also by mmu_setup()) */
> if (!gd->arch.tlb_fillptr)
> setup_all_pgtables();
>
> + invalidate_dcache_all();
> + __asm_invalidate_tlb_all();
> set_sctlr(get_sctlr() | CR_C);
> }
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH -next v7 04/10] arm: armv8: invalidate dcache entries on dcache_enable
2025-09-12 12:28 ` Heinrich Schuchardt
@ 2025-09-15 5:05 ` Anshul Dalal
2025-09-16 11:26 ` Anshul Dalal
0 siblings, 1 reply; 14+ messages in thread
From: Anshul Dalal @ 2025-09-15 5:05 UTC (permalink / raw)
To: Heinrich Schuchardt
Cc: d-gole, b-padhi, vigneshr, trini, nm, robertcnelson, w.egorov,
francesco.dolcini, ggiordano, m-chawdhry, afd, bb, u-kumar1,
devarsht, ilias.apalodimas, u-boot, patrice.chotard,
patrick.delaunay
Hi Heinrich,
On Fri Sep 12, 2025 at 5:58 PM IST, Heinrich Schuchardt wrote:
> On 9/12/25 14:16, Anshul Dalal wrote:
>> In dcache_enable, currently the dcache entries are only invalidated when
>> the MMU is not enabled. This causes issues when dcache_enable is called
>> with the MMU already configured, in such cases the existing dcache
>> entries are not flushed which might result in un-expected behavior.
>>
>> This patch invalidates the cache entries on every call of dcache_enable
>> before enabling dcache (by setting CR_C). This makes dcache_enable
>> behave similar to icache_enable as well.
>>
>> Reviewed-by: Dhruva Gole <d-gole@ti.com>
>> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
>> Signed-off-by: Anshul Dalal <anshuld@ti.com>
>> Tested-by: Wadim Egorov <w.egorov@phytec.de>
>> ---
>> arch/arm/cpu/armv8/cache_v8.c | 7 +++----
>> 1 file changed, 3 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
>> index 1c1e33bec24..6e662395a83 100644
>> --- a/arch/arm/cpu/armv8/cache_v8.c
>> +++ b/arch/arm/cpu/armv8/cache_v8.c
>> @@ -830,16 +830,15 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
>> void dcache_enable(void)
>> {
>> /* The data cache is not active unless the mmu is enabled */
>> - if (!(get_sctlr() & CR_M)) {
>> - invalidate_dcache_all();
>> - __asm_invalidate_tlb_all();
>> + if (!mmu_status())
>
> You are changing the logic here without describing why in the commit
> message:
>
> mmu_status() returns zero if CONFIG_SYS_ICACHE_OFF=y.
> Only for CONFIG_SYS_ICACHE_OFF=n it calls get_sctlr().
>
> Please, check if the logic change is intended.
> Please, update the commit message.
>
The bheaviour should be the same for all combinations of ICACHE_OFF and
DCACHE_OFF except for when ICACHE_OFF=y and DCACHE_OFF=n, in such cases
there is the concern that mmu_setup will be called everytime on
dcache_enable after my patch.
This was not an intended change, thanks for bringing it to my attention.
I think we should drop the ICACHE_OFF=y definition of mmu_setup which
was added in the commit 268f6ac1f95c ("arm64: Update memcpy_{from,
to}io() helpers"). And only keep the one that calls get_sctlr. If that's
off the table, I can respin the series without the call to mmu_status as
well.
CC+: Patrice Chotard, Patrick Delaunay (the authors of above commit)
Regards,
Anshul
>
>> mmu_setup();
>> - }
>>
>> /* Set up page tables only once (it is done also by mmu_setup()) */
>> if (!gd->arch.tlb_fillptr)
>> setup_all_pgtables();
>>
>> + invalidate_dcache_all();
>> + __asm_invalidate_tlb_all();
>> set_sctlr(get_sctlr() | CR_C);
>> }
>>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH -next v7 04/10] arm: armv8: invalidate dcache entries on dcache_enable
2025-09-15 5:05 ` Anshul Dalal
@ 2025-09-16 11:26 ` Anshul Dalal
0 siblings, 0 replies; 14+ messages in thread
From: Anshul Dalal @ 2025-09-16 11:26 UTC (permalink / raw)
To: Anshul Dalal, Heinrich Schuchardt
Cc: d-gole, b-padhi, vigneshr, trini, nm, robertcnelson, w.egorov,
francesco.dolcini, ggiordano, m-chawdhry, afd, bb, u-kumar1,
devarsht, ilias.apalodimas, u-boot, patrice.chotard,
patrick.delaunay
Hi all,
On Mon Sep 15, 2025 at 10:35 AM IST, Anshul Dalal wrote:
> Hi Heinrich,
>
> On Fri Sep 12, 2025 at 5:58 PM IST, Heinrich Schuchardt wrote:
>> On 9/12/25 14:16, Anshul Dalal wrote:
>>> In dcache_enable, currently the dcache entries are only invalidated when
>>> the MMU is not enabled. This causes issues when dcache_enable is called
>>> with the MMU already configured, in such cases the existing dcache
>>> entries are not flushed which might result in un-expected behavior.
>>>
>>> This patch invalidates the cache entries on every call of dcache_enable
>>> before enabling dcache (by setting CR_C). This makes dcache_enable
>>> behave similar to icache_enable as well.
>>>
>>> Reviewed-by: Dhruva Gole <d-gole@ti.com>
>>> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
>>> Signed-off-by: Anshul Dalal <anshuld@ti.com>
>>> Tested-by: Wadim Egorov <w.egorov@phytec.de>
>>> ---
>>> arch/arm/cpu/armv8/cache_v8.c | 7 +++----
>>> 1 file changed, 3 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
>>> index 1c1e33bec24..6e662395a83 100644
>>> --- a/arch/arm/cpu/armv8/cache_v8.c
>>> +++ b/arch/arm/cpu/armv8/cache_v8.c
>>> @@ -830,16 +830,15 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
>>> void dcache_enable(void)
>>> {
>>> /* The data cache is not active unless the mmu is enabled */
>>> - if (!(get_sctlr() & CR_M)) {
>>> - invalidate_dcache_all();
>>> - __asm_invalidate_tlb_all();
>>> + if (!mmu_status())
>>
>> You are changing the logic here without describing why in the commit
>> message:
>>
>> mmu_status() returns zero if CONFIG_SYS_ICACHE_OFF=y.
>> Only for CONFIG_SYS_ICACHE_OFF=n it calls get_sctlr().
>>
>> Please, check if the logic change is intended.
>> Please, update the commit message.
>>
>
> The bheaviour should be the same for all combinations of ICACHE_OFF and
> DCACHE_OFF except for when ICACHE_OFF=y and DCACHE_OFF=n, in such cases
> there is the concern that mmu_setup will be called everytime on
> dcache_enable after my patch.
>
> This was not an intended change, thanks for bringing it to my attention.
>
> I think we should drop the ICACHE_OFF=y definition of mmu_setup which
> was added in the commit 268f6ac1f95c ("arm64: Update memcpy_{from,
> to}io() helpers"). And only keep the one that calls get_sctlr. If that's
> off the table, I can respin the series without the call to mmu_status as
> well.
>
I have posted the patch[1] removing ICACHE_OFF=y definition of
mmu_status, that patch along with this series should address this
unintended change.
Regards,
Anshul
[1]: https://lore.kernel.org/u-boot/20250916112205.238811-1-anshuld@ti.com/
>>
>>> mmu_setup();
>>> - }
>>>
>>> /* Set up page tables only once (it is done also by mmu_setup()) */
>>> if (!gd->arch.tlb_fillptr)
>>> setup_all_pgtables();
>>>
>>> + invalidate_dcache_all();
>>> + __asm_invalidate_tlb_all();
>>> set_sctlr(get_sctlr() | CR_C);
>>> }
>>>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH -next v7 05/10] arm: armv8: mmu: add mem_map_fix_dram_banks
2025-09-12 12:16 [PATCH -next v7 00/10] Add support for dynamic MMU configuration Anshul Dalal
` (3 preceding siblings ...)
2025-09-12 12:16 ` [PATCH -next v7 04/10] arm: armv8: invalidate dcache entries on dcache_enable Anshul Dalal
@ 2025-09-12 12:16 ` Anshul Dalal
2025-09-12 12:16 ` [PATCH -next v7 06/10] mach-k3: map all banks using mem_map_fix_dram_banks Anshul Dalal
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Anshul Dalal @ 2025-09-12 12:16 UTC (permalink / raw)
To: u-boot
Cc: Anshul Dalal, d-gole, b-padhi, vigneshr, trini, nm, robertcnelson,
w.egorov, francesco.dolcini, ggiordano, m-chawdhry, afd, bb,
u-kumar1, devarsht, ilias.apalodimas
For armv8, U-Boot uses a static map defined as 'mem_map' for configuring
the MMU as part of mmu_setup.
But since the exact configuration of memory banks might not be known at
build time, many platforms such as imx9, versal2 etc. utilize
gd->bd->bi_dram to configure the static map at runtime.
Therefore this patch adds a new API mem_map_fix_dram_banks that modifies
the static map in a similar way. Allowing the caller to map all dram
banks by just passing the index to last entry in their mem_map and it's
length.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/cpu/armv8/cache_v8.c | 28 ++++++++++++++++++++++++++++
arch/arm/include/asm/armv8/mmu.h | 10 ++++++++++
2 files changed, 38 insertions(+)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 6e662395a83..20583bad470 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -58,6 +58,34 @@ static int get_effective_el(void)
return el;
}
+int mem_map_fix_dram_banks(unsigned int index, unsigned int len, u64 attrs)
+{
+ unsigned int i;
+ int ret = fdtdec_setup_memory_banksize();
+
+ if (ret) {
+ printf("%s: Failed to setup dram banks\n", __func__);
+ return ret;
+ }
+
+ if (index + CONFIG_NR_DRAM_BANKS >= len) {
+ printf("%s: Provided mem_map array has insufficient size for DRAM entries\n",
+ __func__);
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ mem_map[index].virt = gd->bd->bi_dram[i].start;
+ mem_map[index].phys = gd->bd->bi_dram[i].start;
+ mem_map[index].size = gd->bd->bi_dram[i].size;
+ mem_map[index].attrs = attrs;
+ index++;
+ }
+
+ memset(&mem_map[index], 0, sizeof(mem_map[index]));
+
+ return 0;
+}
u64 get_tcr(u64 *pips, u64 *pva_bits)
{
int el = get_effective_el();
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 3807c702fb6..257352f216e 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -194,8 +194,18 @@ struct mm_region {
u64 attrs;
};
+/* Used as the memory map for MMU configuration by mmu_setup */
extern struct mm_region *mem_map;
void setup_pgtables(void);
+
+/**
+ * mem_map_fix_dram_banks() - Populate mem_map with entries corresponding to
+ * dram banks as per the gd. This should be called prior to mmu_setup.
+ *
+ * @index: The entry in mem_map to start the over-write
+ * @len: The size of mem_map
+ */
+int mem_map_fix_dram_banks(unsigned int index, unsigned int len, u64 attrs);
u64 get_tcr(u64 *pips, u64 *pva_bits);
/**
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH -next v7 06/10] mach-k3: map all banks using mem_map_fix_dram_banks
2025-09-12 12:16 [PATCH -next v7 00/10] Add support for dynamic MMU configuration Anshul Dalal
` (4 preceding siblings ...)
2025-09-12 12:16 ` [PATCH -next v7 05/10] arm: armv8: mmu: add mem_map_fix_dram_banks Anshul Dalal
@ 2025-09-12 12:16 ` Anshul Dalal
2025-09-12 12:16 ` [PATCH -next v7 07/10] arm: armv8: mmu: add mmu_unmap_reserved_mem Anshul Dalal
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Anshul Dalal @ 2025-09-12 12:16 UTC (permalink / raw)
To: u-boot
Cc: Anshul Dalal, d-gole, b-padhi, vigneshr, trini, nm, robertcnelson,
w.egorov, francesco.dolcini, ggiordano, m-chawdhry, afd, bb,
u-kumar1, devarsht, ilias.apalodimas
The static memory map for K3 (k3_mem_map) only maps the first DRAM bank
and therefore doesn't scale for platforms with multiple memory banks.
This patch modifies enable_caches to add mem_map_fix_dram_banks which
appends all the memory banks to k3_mem_map before calling mmu_setup.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/mach-k3/arm64/arm64-mmu.c | 5 +++--
arch/arm/mach-k3/common.c | 9 +++++++++
arch/arm/mach-k3/include/mach/k3-ddr.h | 6 ++++++
3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-k3/arm64/arm64-mmu.c b/arch/arm/mach-k3/arm64/arm64-mmu.c
index 79650a7e346..479451452a2 100644
--- a/arch/arm/mach-k3/arm64/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64/arm64-mmu.c
@@ -12,8 +12,9 @@
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
+#include <mach/k3-ddr.h>
-struct mm_region k3_mem_map[] = {
+struct mm_region k3_mem_map[K3_MEM_MAP_LEN] = {
{ /* SoC Peripherals */
.virt = 0x0UL,
.phys = 0x0UL,
@@ -28,7 +29,7 @@ struct mm_region k3_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, { /* First DRAM Bank of size 2G */
+ }, [K3_MEM_MAP_FIRST_BANK_IDX] = { /* First DRAM Bank of size 2G */
.virt = CFG_SYS_SDRAM_BASE,
.phys = CFG_SYS_SDRAM_BASE,
.size = SZ_2G,
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index ea287ba1226..0a73b1fa296 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -31,6 +31,7 @@
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <asm/armv8/mmu.h>
+#include <mach/k3-ddr.h>
#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
#define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
@@ -262,6 +263,14 @@ void board_prep_linux(struct bootm_headers *images)
void enable_caches(void)
{
+ int ret;
+
+ ret = mem_map_fix_dram_banks(K3_MEM_MAP_FIRST_BANK_IDX, K3_MEM_MAP_LEN,
+ PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE);
+ if (ret)
+ debug("%s: Failed to setup dram banks\n", __func__);
+
mmu_setup();
icache_enable();
diff --git a/arch/arm/mach-k3/include/mach/k3-ddr.h b/arch/arm/mach-k3/include/mach/k3-ddr.h
index 39e6725bb9b..207e60b2763 100644
--- a/arch/arm/mach-k3/include/mach/k3-ddr.h
+++ b/arch/arm/mach-k3/include/mach/k3-ddr.h
@@ -8,6 +8,12 @@
#include <spl.h>
+/* We need 3 extra entries for:
+ * SoC peripherals, flash and the sentinel value.
+ */
+#define K3_MEM_MAP_LEN ((CONFIG_NR_DRAM_BANKS) + 3)
+#define K3_MEM_MAP_FIRST_BANK_IDX 2
+
int dram_init(void);
int dram_init_banksize(void);
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH -next v7 07/10] arm: armv8: mmu: add mmu_unmap_reserved_mem
2025-09-12 12:16 [PATCH -next v7 00/10] Add support for dynamic MMU configuration Anshul Dalal
` (5 preceding siblings ...)
2025-09-12 12:16 ` [PATCH -next v7 06/10] mach-k3: map all banks using mem_map_fix_dram_banks Anshul Dalal
@ 2025-09-12 12:16 ` Anshul Dalal
2025-09-12 12:16 ` [PATCH -next v7 08/10] spl: split spl_board_fixups to arch/board specific Anshul Dalal
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Anshul Dalal @ 2025-09-12 12:16 UTC (permalink / raw)
To: u-boot
Cc: Anshul Dalal, d-gole, b-padhi, vigneshr, trini, nm, robertcnelson,
w.egorov, francesco.dolcini, ggiordano, m-chawdhry, afd, bb,
u-kumar1, devarsht, ilias.apalodimas
For armv8, U-Boot uses a static map defined as 'mem_map' for configuring
the MMU's page tables, done by mmu_setup.
Though this works well for simpler platforms, it makes creating runtime
carveouts by modifying the static array at runtime exceedingly complex
like in mach-snapdragon/board.c.
Creation of such carveouts are much better handled by APIs such as
mmu_change_region_attr once the page tables are configured. Usually such
carveouts are configured via the device-tree's reserved-memory node
which provides the address and size for the carveout.
Therefore this patch adds mmu_unmap_reserved_mem which acts as a wrapper
over mmu_change_region_attr, helping unmap a reserved-memory region.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/cpu/armv8/cache_v8.c | 23 +++++++++++++++++++++++
arch/arm/include/asm/armv8/mmu.h | 9 +++++++++
2 files changed, 32 insertions(+)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 20583bad470..1dcb6007475 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -86,6 +86,29 @@ int mem_map_fix_dram_banks(unsigned int index, unsigned int len, u64 attrs)
return 0;
}
+
+int mmu_unmap_reserved_mem(const char *name)
+{
+ void *fdt = (void *)gd->fdt_blob;
+ char node_path[128];
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ snprintf(node_path, sizeof(node_path), "/reserved-memory/%s", name);
+ ret = fdt_path_offset(fdt, node_path);
+ if (ret < 0)
+ return ret;
+
+ addr = fdtdec_get_addr_size(fdt, ret, "reg", &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -1;
+
+ mmu_change_region_attr_nobreak(addr, size, PTE_TYPE_FAULT);
+
+ return 0;
+}
+
u64 get_tcr(u64 *pips, u64 *pva_bits)
{
int el = get_effective_el();
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 257352f216e..fbd64e649ff 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -206,6 +206,15 @@ void setup_pgtables(void);
* @len: The size of mem_map
*/
int mem_map_fix_dram_banks(unsigned int index, unsigned int len, u64 attrs);
+
+/**
+ * mmu_unmap_reserved_mem() - Unmaps a reserved-memory node as PTE_TYPE_FAULT
+ * once MMU is configured by mmu_setup.
+ *
+ * @name: The name of the node under "/reserved-memory/" path
+ */
+int mmu_unmap_reserved_mem(const char *name);
+
u64 get_tcr(u64 *pips, u64 *pva_bits);
/**
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH -next v7 08/10] spl: split spl_board_fixups to arch/board specific
2025-09-12 12:16 [PATCH -next v7 00/10] Add support for dynamic MMU configuration Anshul Dalal
` (6 preceding siblings ...)
2025-09-12 12:16 ` [PATCH -next v7 07/10] arm: armv8: mmu: add mmu_unmap_reserved_mem Anshul Dalal
@ 2025-09-12 12:16 ` Anshul Dalal
2025-09-12 12:16 ` [PATCH -next v7 09/10] mach-k3: add reserved memory fixups for next boot stage Anshul Dalal
2025-09-12 12:16 ` [PATCH -next v7 10/10] mach-k3: add carveouts for TFA and optee Anshul Dalal
9 siblings, 0 replies; 14+ messages in thread
From: Anshul Dalal @ 2025-09-12 12:16 UTC (permalink / raw)
To: u-boot
Cc: Anshul Dalal, d-gole, b-padhi, vigneshr, trini, nm, robertcnelson,
w.egorov, francesco.dolcini, ggiordano, m-chawdhry, afd, bb,
u-kumar1, devarsht, ilias.apalodimas
The current spl_board_fixups API allows for modification of spl_image
before the SPL jumps to it. This can be used to modify the DT for the
next boot stage, however the current API only allows either the machine
arch or the board to use it.
This limits the utility of the API as there might be certain fixups that
should be applied to all boards sharing the same machine architecture
with others being board specific.
For TI's K3 specifically, this prevents us from performing architecture
level fixups since a lot of TI boards are already making use of the
spl_board_fixups API.
Therefore this patch splits the API into two to allow both board and the
architecture specific fixups. The order is kept as arch then board to
give board specific fixups the precedence.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/cpu/armv7m/cpu.c | 2 +-
arch/arm/mach-rockchip/spl-boot-order.c | 2 +-
arch/arm/mach-socfpga/spl_soc64.c | 2 +-
board/beagle/beagley-ai/beagley-ai.c | 2 +-
board/dhelectronics/dh_stm32mp1/board.c | 2 +-
board/phytec/phycore_am62x/phycore-am62x.c | 2 +-
board/phytec/phycore_am64x/phycore-am64x.c | 2 +-
board/renesas/sparrowhawk/sparrowhawk.c | 2 +-
board/starfive/visionfive2/spl.c | 2 +-
board/ti/am62ax/evm.c | 2 +-
board/ti/am62px/evm.c | 2 +-
board/ti/am62x/evm.c | 2 +-
board/ti/am64x/evm.c | 2 +-
board/ti/j721e/evm.c | 2 +-
board/ti/j721s2/evm.c | 2 +-
board/ti/j722s/evm.c | 2 +-
board/ti/j784s4/evm.c | 2 +-
common/spl/spl.c | 12 +++++++++---
include/spl.h | 12 +++++++++---
19 files changed, 35 insertions(+), 23 deletions(-)
diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c
index b4440d3f3f8..bea0e1d3263 100644
--- a/arch/arm/cpu/armv7m/cpu.c
+++ b/arch/arm/cpu/armv7m/cpu.c
@@ -57,7 +57,7 @@ void reset_cpu(void)
| V7M_AIRCR_SYSRESET, &V7M_SCB->aircr);
}
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_arch_fixups(struct spl_image_info *spl_image)
{
spl_image->entry_point |= 0x1;
}
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
index 1bfd120adc4..561bddd12a6 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -240,7 +240,7 @@ int spl_decode_boot_device(u32 boot_device, char *buf, size_t buflen)
#endif
}
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_arch_fixups(struct spl_image_info *spl_image)
{
const char *bootrom_ofpath = board_spl_was_booted_from();
void *blob = spl_image_fdt_addr(spl_image);
diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c
index 651d9fc9cb8..fa7b1506ce6 100644
--- a/arch/arm/mach-socfpga/spl_soc64.c
+++ b/arch/arm/mach-socfpga/spl_soc64.c
@@ -130,7 +130,7 @@ u32 spl_boot_mode(const u32 boot_device)
#endif
/* board specific function prior loading SSBL / U-Boot */
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_arch_fixups(struct spl_image_info *spl_image)
{
int ret;
struct udevice *dev;
diff --git a/board/beagle/beagley-ai/beagley-ai.c b/board/beagle/beagley-ai/beagley-ai.c
index 26fa54e27bb..500cc3060c3 100644
--- a/board/beagle/beagley-ai/beagley-ai.c
+++ b/board/beagle/beagley-ai/beagley-ai.c
@@ -32,7 +32,7 @@ int dram_init_banksize(void)
}
#if defined(CONFIG_XPL_BUILD)
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index f7347bbb826..2c79303f5cd 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -776,7 +776,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#endif
#if defined(CONFIG_XPL_BUILD)
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
dh_stm32_ks8851_fixup(spl_image_fdt_addr(spl_image));
}
diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c
index 51da864aa80..3cdcbf2ecc9 100644
--- a/board/phytec/phycore_am62x/phycore-am62x.c
+++ b/board/phytec/phycore_am62x/phycore-am62x.c
@@ -199,7 +199,7 @@ int do_board_detect(void)
#endif
#if IS_ENABLED(CONFIG_XPL_BUILD)
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
if (IS_ENABLED(CONFIG_K3_DDRSS) && IS_ENABLED(CONFIG_K3_INLINE_ECC))
fixup_ddr_driver_for_ecc(spl_image);
diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c
index 33c39376ceb..114aa217023 100644
--- a/board/phytec/phycore_am64x/phycore-am64x.c
+++ b/board/phytec/phycore_am64x/phycore-am64x.c
@@ -118,7 +118,7 @@ int do_board_detect(void)
#endif
#if IS_ENABLED(CONFIG_XPL_BUILD)
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
if (IS_ENABLED(CONFIG_K3_DDRSS) && IS_ENABLED(CONFIG_K3_INLINE_ECC))
fixup_ddr_driver_for_ecc(spl_image);
diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c
index 58de7f25cbd..29a67dae34e 100644
--- a/board/renesas/sparrowhawk/sparrowhawk.c
+++ b/board/renesas/sparrowhawk/sparrowhawk.c
@@ -134,7 +134,7 @@ unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
return CONFIG_SYS_SPI_U_BOOT_OFFS;
}
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
void *blob = spl_image_fdt_addr(spl_image);
int err, offs;
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 3dfa931b655..180b397051d 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define JH7110_CLK_CPU_ROOT_SHIFT 24
#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
/* Update the memory size which read from eeprom or DT */
fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size);
diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c
index a445f983255..da6c31176cd 100644
--- a/board/ti/am62ax/evm.c
+++ b/board/ti/am62ax/evm.c
@@ -17,7 +17,7 @@
#include "../common/fdt_ops.h"
#if defined(CONFIG_XPL_BUILD)
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c
index c06e3878d67..85c332b9339 100644
--- a/board/ti/am62px/evm.c
+++ b/board/ti/am62px/evm.c
@@ -50,7 +50,7 @@ void spl_board_init(void)
#endif
#if defined(CONFIG_XPL_BUILD)
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c
index d7b07a0d34d..c2c7a0216b9 100644
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -91,7 +91,7 @@ void spl_board_init(void)
}
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index 8e89b3b15df..f9bb593e4c6 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -98,7 +98,7 @@ static int fixup_usb_boot(const void *fdt_blob)
}
#endif
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 1527eaf1e16..e030fe7dc87 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -127,7 +127,7 @@ static void __maybe_unused detect_enable_hyperflash(void *blob)
#if defined(CONFIG_XPL_BUILD) && (defined(CONFIG_TARGET_J7200_A72_EVM) || defined(CONFIG_TARGET_J7200_R5_EVM) || \
defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J721E_R5_EVM))
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
detect_enable_hyperflash(spl_image->fdt_addr);
}
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 5d3b84607d8..b6d1964146d 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -40,7 +40,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
}
#if defined(CONFIG_XPL_BUILD)
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c
index 32d767cb7d2..1173adc072b 100644
--- a/board/ti/j722s/evm.c
+++ b/board/ti/j722s/evm.c
@@ -24,7 +24,7 @@ void spl_board_init(void)
#endif
#if defined(CONFIG_XPL_BUILD)
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c
index 6335676081a..cabb3017ee1 100644
--- a/board/ti/j784s4/evm.c
+++ b/board/ti/j784s4/evm.c
@@ -42,7 +42,7 @@ struct efi_capsule_update_info update_info = {
};
#if defined(CONFIG_XPL_BUILD)
-void spl_perform_fixups(struct spl_image_info *spl_image)
+void spl_perform_board_fixups(struct spl_image_info *spl_image)
{
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 55ad497c86d..2b321284b59 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -120,8 +120,13 @@ int __weak booti_setup(ulong image, ulong *relocated_addr, ulong *size, bool for
}
#endif
-/* Weak default function for arch/board-specific fixups to the spl_image_info */
-void __weak spl_perform_fixups(struct spl_image_info *spl_image)
+/* Weak default function for arch specific fixups to the spl_image_info */
+void __weak spl_perform_arch_fixups(struct spl_image_info *spl_image)
+{
+}
+
+/* Weak default function for board specific fixups to the spl_image_info */
+void __weak spl_perform_board_fixups(struct spl_image_info *spl_image)
{
}
@@ -775,7 +780,8 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
hang();
}
- spl_perform_fixups(&spl_image);
+ spl_perform_arch_fixups(&spl_image);
+ spl_perform_board_fixups(&spl_image);
os = spl_image.os;
if (os == IH_OS_U_BOOT) {
diff --git a/include/spl.h b/include/spl.h
index 7c10c7f792e..cf45d411ecb 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -1116,10 +1116,16 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
ulong board_spl_fit_size_align(ulong size);
/**
- * spl_perform_fixups() - arch/board-specific callback before processing
- * the boot-payload
+ * spl_perform_arch_fixups() - arch specific callback before processing the
+ * boot-payload
*/
-void spl_perform_fixups(struct spl_image_info *spl_image);
+void spl_perform_arch_fixups(struct spl_image_info *spl_image);
+
+/**
+ * spl_perform_board_fixups() - board specific callback before processing the
+ * boot-payload
+ */
+void spl_perform_board_fixups(struct spl_image_info *spl_image);
/*
* spl_get_load_buffer() - get buffer for loading partial image data
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH -next v7 09/10] mach-k3: add reserved memory fixups for next boot stage
2025-09-12 12:16 [PATCH -next v7 00/10] Add support for dynamic MMU configuration Anshul Dalal
` (7 preceding siblings ...)
2025-09-12 12:16 ` [PATCH -next v7 08/10] spl: split spl_board_fixups to arch/board specific Anshul Dalal
@ 2025-09-12 12:16 ` Anshul Dalal
2025-09-12 12:16 ` [PATCH -next v7 10/10] mach-k3: add carveouts for TFA and optee Anshul Dalal
9 siblings, 0 replies; 14+ messages in thread
From: Anshul Dalal @ 2025-09-12 12:16 UTC (permalink / raw)
To: u-boot
Cc: Anshul Dalal, d-gole, b-padhi, vigneshr, trini, nm, robertcnelson,
w.egorov, francesco.dolcini, ggiordano, m-chawdhry, afd, bb,
u-kumar1, devarsht, ilias.apalodimas
The boot flow in K3 platforms requires the subsequent boot stages to be
aware of the memory reserved for previous boot binaries. In the regular
boot sequence of:
R5 SPL -> ATF -> OP-TEE -> A-core SPL -> U-Boot -> Kernel,
Both A-core SPL and U-Boot should be made aware of the memory reserved
for ATF and OP-TEE from their device-tree. Currently this information is
absent.
Therefore this patch adds the reserved-memory regions as part of
spl_perform_arch_fixups for the next stage's DT. This is called during
both R5 and A-core SPL which fixes up the DT for their respective next
stages: A-core SPL and U-Boot proper.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/mach-k3/common.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 0a73b1fa296..581a7246630 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -321,6 +321,17 @@ static __maybe_unused void k3_dma_remove(void)
pr_warn("DMA Device not found (err=%d)\n", rc);
}
+void spl_perform_arch_fixups(struct spl_image_info *spl_image)
+{
+ void *fdt = spl_image_fdt_addr(spl_image);
+
+ if (!fdt)
+ return;
+
+ fdt_fixup_reserved(fdt, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000);
+ fdt_fixup_reserved(fdt, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000);
+}
+
void spl_board_prepare_for_boot(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH -next v7 10/10] mach-k3: add carveouts for TFA and optee
2025-09-12 12:16 [PATCH -next v7 00/10] Add support for dynamic MMU configuration Anshul Dalal
` (8 preceding siblings ...)
2025-09-12 12:16 ` [PATCH -next v7 09/10] mach-k3: add reserved memory fixups for next boot stage Anshul Dalal
@ 2025-09-12 12:16 ` Anshul Dalal
9 siblings, 0 replies; 14+ messages in thread
From: Anshul Dalal @ 2025-09-12 12:16 UTC (permalink / raw)
To: u-boot
Cc: Anshul Dalal, d-gole, b-padhi, vigneshr, trini, nm, robertcnelson,
w.egorov, francesco.dolcini, ggiordano, m-chawdhry, afd, bb,
u-kumar1, devarsht, ilias.apalodimas
K3 platforms have reserved memory regions for TFA and OPTEE which should
be unmapped for U-Boot.
Therefore this patch adds the necessary fdt fixups to properly set the
load address for TFA/OPTEE and unmaps both by mmu_unmap_reserved_mem.
Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
---
arch/arm/mach-k3/common.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 581a7246630..83562a07435 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -31,6 +31,7 @@
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <asm/armv8/mmu.h>
+#include <mach/k3-common-fdt.h>
#include <mach/k3-ddr.h>
#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
@@ -263,6 +264,7 @@ void board_prep_linux(struct bootm_headers *images)
void enable_caches(void)
{
+ void *fdt = (void *)gd->fdt_blob;
int ret;
ret = mem_map_fix_dram_banks(K3_MEM_MAP_FIRST_BANK_IDX, K3_MEM_MAP_LEN,
@@ -273,6 +275,30 @@ void enable_caches(void)
mmu_setup();
+ if (CONFIG_K3_ATF_LOAD_ADDR >= CFG_SYS_SDRAM_BASE) {
+ ret = fdt_fixup_reserved(fdt, "tfa", CONFIG_K3_ATF_LOAD_ADDR,
+ 0x80000);
+ if (ret)
+ debug("%s: Failed to perform tfa fixups (%s)\n",
+ __func__, fdt_strerror(ret));
+ ret = mmu_unmap_reserved_mem("tfa");
+ if (ret)
+ debug("%s: Failed to unmap tfa reserved mem (%d)\n",
+ __func__, ret);
+ }
+
+ if (CONFIG_K3_OPTEE_LOAD_ADDR >= CFG_SYS_SDRAM_BASE) {
+ ret = fdt_fixup_reserved(fdt, "optee",
+ CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000);
+ if (ret)
+ debug("%s: Failed to perform optee fixups (%s)\n",
+ __func__, fdt_strerror(ret));
+ ret = mmu_unmap_reserved_mem("optee");
+ if (ret)
+ debug("%s: Failed to unmap optee reserved mem (%d)\n",
+ __func__, ret);
+ }
+
icache_enable();
dcache_enable();
}
--
2.51.0
^ permalink raw reply related [flat|nested] 14+ messages in thread