From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Hui Min Mina Chou" <minachou@andestech.com>,
<anup@brainfault.org>, <atish.patra@linux.dev>, <pjw@kernel.org>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <alex@ghiti.fr>
Cc: <kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<tim609@andestech.com>, <ben717@andestech.com>,
<az70021@gmail.com>,
"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v2] RISC-V: KVM: flush VS-stage TLB after VCPU migration to prevent stale entries
Date: Tue, 21 Oct 2025 12:10:47 +0200 [thread overview]
Message-ID: <DDNX3CCBLWXK.3KMVX9AKL162N@ventanamicro.com> (raw)
In-Reply-To: <20251021083105.4029305-1-minachou@andestech.com>
2025-10-21T16:31:05+08:00, Hui Min Mina Chou <minachou@andestech.com>:
> From: Hui Min Mina Chou <minachou@andestech.com>
>
> If multiple VCPUs of the same Guest/VM run on the same Host CPU,
> hfence.vvma only flushes that Host CPU’s VS-stage TLB. Other Host CPUs
> may retain stale VS-stage entries. When a VCPU later migrates to a
> different Host CPU, it can hit these stale GVA to GPA mappings, causing
> unexpected faults in the Guest.
>
> To fix this, kvm_riscv_gstage_vmid_sanitize() is extended to flush both
> G-stage and VS-stage TLBs whenever a VCPU migrates to a different Host CPU.
> This ensures that no stale VS-stage mappings remain after VCPU migration.
>
> Fixes: 92e450507d56 ("RISC-V: KVM: Cleanup stale TLB entries when host CPU changes")
> Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> ---
The vvma flush is not necessary on implementation that have a single TLB
for the combined mapping, but there is no good way of detecting that,
Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com>
--
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WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Hui Min Mina Chou" <minachou@andestech.com>,
<anup@brainfault.org>, <atish.patra@linux.dev>, <pjw@kernel.org>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <alex@ghiti.fr>
Cc: <kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<tim609@andestech.com>, <ben717@andestech.com>,
<az70021@gmail.com>,
"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v2] RISC-V: KVM: flush VS-stage TLB after VCPU migration to prevent stale entries
Date: Tue, 21 Oct 2025 12:10:47 +0200 [thread overview]
Message-ID: <DDNX3CCBLWXK.3KMVX9AKL162N@ventanamicro.com> (raw)
In-Reply-To: <20251021083105.4029305-1-minachou@andestech.com>
2025-10-21T16:31:05+08:00, Hui Min Mina Chou <minachou@andestech.com>:
> From: Hui Min Mina Chou <minachou@andestech.com>
>
> If multiple VCPUs of the same Guest/VM run on the same Host CPU,
> hfence.vvma only flushes that Host CPU’s VS-stage TLB. Other Host CPUs
> may retain stale VS-stage entries. When a VCPU later migrates to a
> different Host CPU, it can hit these stale GVA to GPA mappings, causing
> unexpected faults in the Guest.
>
> To fix this, kvm_riscv_gstage_vmid_sanitize() is extended to flush both
> G-stage and VS-stage TLBs whenever a VCPU migrates to a different Host CPU.
> This ensures that no stale VS-stage mappings remain after VCPU migration.
>
> Fixes: 92e450507d56 ("RISC-V: KVM: Cleanup stale TLB entries when host CPU changes")
> Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> ---
The vvma flush is not necessary on implementation that have a single TLB
for the combined mapping, but there is no good way of detecting that,
Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com>
WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Hui Min Mina Chou" <minachou@andestech.com>,
<anup@brainfault.org>, <atish.patra@linux.dev>, <pjw@kernel.org>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <alex@ghiti.fr>
Cc: <kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<tim609@andestech.com>, <ben717@andestech.com>,
<az70021@gmail.com>,
"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v2] RISC-V: KVM: flush VS-stage TLB after VCPU migration to prevent stale entries
Date: Tue, 21 Oct 2025 12:10:47 +0200 [thread overview]
Message-ID: <DDNX3CCBLWXK.3KMVX9AKL162N@ventanamicro.com> (raw)
In-Reply-To: <20251021083105.4029305-1-minachou@andestech.com>
2025-10-21T16:31:05+08:00, Hui Min Mina Chou <minachou@andestech.com>:
> From: Hui Min Mina Chou <minachou@andestech.com>
>
> If multiple VCPUs of the same Guest/VM run on the same Host CPU,
> hfence.vvma only flushes that Host CPU’s VS-stage TLB. Other Host CPUs
> may retain stale VS-stage entries. When a VCPU later migrates to a
> different Host CPU, it can hit these stale GVA to GPA mappings, causing
> unexpected faults in the Guest.
>
> To fix this, kvm_riscv_gstage_vmid_sanitize() is extended to flush both
> G-stage and VS-stage TLBs whenever a VCPU migrates to a different Host CPU.
> This ensures that no stale VS-stage mappings remain after VCPU migration.
>
> Fixes: 92e450507d56 ("RISC-V: KVM: Cleanup stale TLB entries when host CPU changes")
> Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> ---
The vvma flush is not necessary on implementation that have a single TLB
for the combined mapping, but there is no good way of detecting that,
Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com>
_______________________________________________
linux-riscv mailing list
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http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2025-10-21 10:12 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-21 8:31 [PATCH v2] RISC-V: KVM: flush VS-stage TLB after VCPU migration to prevent stale entries Hui Min Mina Chou
2025-10-21 8:31 ` Hui Min Mina Chou
2025-10-21 8:31 ` Hui Min Mina Chou
2025-10-21 10:10 ` Radim Krčmář [this message]
2025-10-21 10:10 ` Radim Krčmář
2025-10-21 10:10 ` Radim Krčmář
2025-10-22 20:34 ` kernel test robot
2025-10-22 20:34 ` kernel test robot
2025-10-22 20:34 ` kernel test robot
2025-10-22 21:27 ` kernel test robot
2025-10-22 21:27 ` kernel test robot
2025-10-22 21:27 ` kernel test robot
2025-10-24 3:52 ` Anup Patel
2025-10-24 3:52 ` Anup Patel
2025-10-24 3:52 ` Anup Patel
2025-10-30 8:44 ` Mina Chou
2025-10-30 8:44 ` Mina Chou
2025-10-30 8:44 ` Mina Chou
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