* [PATCH 1/2] KVM: riscv: selftests: Add riscv vm satp modes [not found] <20251017110908650RWBl7sDIk6WUGhkvJSH4L@zte.com.cn> @ 2025-10-17 3:13 ` wu.fei9 2025-10-17 15:38 ` Andrew Jones 2025-10-17 3:15 ` [PATCH 2/2] KVM: riscv: selftests: Detect supported vm modes wu.fei9 1 sibling, 1 reply; 13+ messages in thread From: wu.fei9 @ 2025-10-17 3:13 UTC (permalink / raw) To: kvm-riscv, ajones Current vm modes cannot represent riscv guest modes precisely, here add P41V39, P50V48 and P56V57. Signed-off-by: Wu Fei <wu.fei9@sanechips.com.cn> --- .../testing/selftests/kvm/include/kvm_util.h | 7 ++++++- tools/testing/selftests/kvm/lib/guest_modes.c | 7 +++---- tools/testing/selftests/kvm/lib/kvm_util.c | 15 +++++++++++++ .../selftests/kvm/lib/riscv/processor.c | 21 +++++++++++++++---- 4 files changed, 41 insertions(+), 9 deletions(-) diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h index bee65ca08721..02224bc514d4 100644 --- a/tools/testing/selftests/kvm/include/kvm_util.h +++ b/tools/testing/selftests/kvm/include/kvm_util.h @@ -179,6 +179,11 @@ enum vm_guest_mode { VM_MODE_P36V48_64K, VM_MODE_P47V47_16K, VM_MODE_P36V47_16K, + + VM_MODE_P56V57_4K, /* For riscv64 */ + VM_MODE_P50V48_4K, + VM_MODE_P41V39_4K, + NUM_VM_MODES, }; @@ -229,7 +234,7 @@ extern enum vm_guest_mode vm_mode_default; #error "RISC-V 32-bit kvm selftests not supported" #endif -#define VM_MODE_DEFAULT VM_MODE_P40V48_4K +#define VM_MODE_DEFAULT VM_MODE_P50V48_4K #define MIN_PAGE_SHIFT 12U #define ptes_per_page(page_size) ((page_size) / 8) diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/selftests/kvm/lib/guest_modes.c index b04901e55138..63d0d5479188 100644 --- a/tools/testing/selftests/kvm/lib/guest_modes.c +++ b/tools/testing/selftests/kvm/lib/guest_modes.c @@ -75,10 +75,9 @@ void guest_modes_append_default(void) { unsigned int sz = kvm_check_cap(KVM_CAP_VM_GPA_BITS); - if (sz >= 52) - guest_mode_append(VM_MODE_P52V48_4K, true); - if (sz >= 48) - guest_mode_append(VM_MODE_P48V48_4K, true); + guest_mode_append(VM_MODE_P56V57_4K, sz >= 59); + guest_mode_append(VM_MODE_P50V48_4K, sz >= 50); + guest_mode_append(VM_MODE_P41V39_4K, sz >= 41); } #endif } diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/selftests/kvm/lib/kvm_util.c index a055343a7bf7..4cd69fffa06d 100644 --- a/tools/testing/selftests/kvm/lib/kvm_util.c +++ b/tools/testing/selftests/kvm/lib/kvm_util.c @@ -224,6 +224,9 @@ const char *vm_guest_mode_string(uint32_t i) [VM_MODE_P36V48_64K] = "PA-bits:36, VA-bits:48, 64K pages", [VM_MODE_P47V47_16K] = "PA-bits:47, VA-bits:47, 16K pages", [VM_MODE_P36V47_16K] = "PA-bits:36, VA-bits:47, 16K pages", + [VM_MODE_P56V57_4K] = "PA-bits:56, VA-bits:57, 4K pages", + [VM_MODE_P50V48_4K] = "PA-bits:50, VA-bits:48, 4K pages", + [VM_MODE_P41V39_4K] = "PA-bits:41, VA-bits:39, 4K pages", }; _Static_assert(sizeof(strings)/sizeof(char *) == NUM_VM_MODES, "Missing new mode strings?"); @@ -251,6 +254,9 @@ const struct vm_guest_mode_params vm_guest_mode_params[] = { [VM_MODE_P36V48_64K] = { 36, 48, 0x10000, 16 }, [VM_MODE_P47V47_16K] = { 47, 47, 0x4000, 14 }, [VM_MODE_P36V47_16K] = { 36, 47, 0x4000, 14 }, + [VM_MODE_P56V57_4K] = { 56, 57, 0x1000, 12 }, + [VM_MODE_P50V48_4K] = { 50, 48, 0x1000, 12 }, + [VM_MODE_P41V39_4K] = { 41, 39, 0x1000, 12 }, }; _Static_assert(sizeof(vm_guest_mode_params)/sizeof(struct vm_guest_mode_params) == NUM_VM_MODES, "Missing new mode params?"); @@ -351,6 +357,15 @@ struct kvm_vm *____vm_create(struct vm_shape shape) case VM_MODE_P44V64_4K: vm->pgtable_levels = 5; break; + case VM_MODE_P56V57_4K: + vm->pgtable_levels = 5; + break; + case VM_MODE_P50V48_4K: + vm->pgtable_levels = 4; + break; + case VM_MODE_P41V39_4K: + vm->pgtable_levels = 3; + break; default: TEST_FAIL("Unknown guest mode: 0x%x", vm->mode); } diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c index 2eac7d4b59e9..de84c092f982 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -197,22 +197,35 @@ void riscv_vcpu_mmu_setup(struct kvm_vcpu *vcpu) { struct kvm_vm *vm = vcpu->vm; unsigned long satp; + unsigned long satp_mode; + unsigned long max_satp_mode; /* * The RISC-V Sv48 MMU mode supports 56-bit physical address * for 48-bit virtual address with 4KB last level page size. */ switch (vm->mode) { - case VM_MODE_P52V48_4K: - case VM_MODE_P48V48_4K: - case VM_MODE_P40V48_4K: + case VM_MODE_P56V57_4K: + satp_mode = SATP_MODE_57; + break; + case VM_MODE_P50V48_4K: + satp_mode = SATP_MODE_48; + break; + case VM_MODE_P41V39_4K: + satp_mode = SATP_MODE_39; break; default: TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); } + max_satp_mode = vcpu_get_reg(vcpu, RISCV_CONFIG_REG(satp_mode)); + + if ((satp_mode >> SATP_MODE_SHIFT) > max_satp_mode) + TEST_FAIL("Unable to set satp mode 0x%lx, max mode 0x%lx\n", + satp_mode >> SATP_MODE_SHIFT, max_satp_mode); + satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN; - satp |= SATP_MODE_48; + satp |= satp_mode; vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(satp), satp); } -- 2.43.0 -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] KVM: riscv: selftests: Add riscv vm satp modes 2025-10-17 3:13 ` [PATCH 1/2] KVM: riscv: selftests: Add riscv vm satp modes wu.fei9 @ 2025-10-17 15:38 ` Andrew Jones 2025-10-20 13:09 ` Wu Fei 0 siblings, 1 reply; 13+ messages in thread From: Andrew Jones @ 2025-10-17 15:38 UTC (permalink / raw) To: wu.fei9; +Cc: kvm-riscv On Fri, Oct 17, 2025 at 11:13:33AM +0800, wu.fei9@sanechips.com.cn wrote: > Current vm modes cannot represent riscv guest modes precisely, here add > P41V39, P50V48 and P56V57. > > Signed-off-by: Wu Fei <wu.fei9@sanechips.com.cn> > --- > .../testing/selftests/kvm/include/kvm_util.h | 7 ++++++- > tools/testing/selftests/kvm/lib/guest_modes.c | 7 +++---- > tools/testing/selftests/kvm/lib/kvm_util.c | 15 +++++++++++++ > .../selftests/kvm/lib/riscv/processor.c | 21 +++++++++++++++---- > 4 files changed, 41 insertions(+), 9 deletions(-) > > diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h > index bee65ca08721..02224bc514d4 100644 > --- a/tools/testing/selftests/kvm/include/kvm_util.h > +++ b/tools/testing/selftests/kvm/include/kvm_util.h > @@ -179,6 +179,11 @@ enum vm_guest_mode { > VM_MODE_P36V48_64K, > VM_MODE_P47V47_16K, > VM_MODE_P36V47_16K, > + > + VM_MODE_P56V57_4K, /* For riscv64 */ This should be P59 > + VM_MODE_P50V48_4K, > + VM_MODE_P41V39_4K, > + > NUM_VM_MODES, > }; > > @@ -229,7 +234,7 @@ extern enum vm_guest_mode vm_mode_default; > #error "RISC-V 32-bit kvm selftests not supported" > #endif > > -#define VM_MODE_DEFAULT VM_MODE_P40V48_4K > +#define VM_MODE_DEFAULT VM_MODE_P50V48_4K > #define MIN_PAGE_SHIFT 12U > #define ptes_per_page(page_size) ((page_size) / 8) > > diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/selftests/kvm/lib/guest_modes.c > index b04901e55138..63d0d5479188 100644 > --- a/tools/testing/selftests/kvm/lib/guest_modes.c > +++ b/tools/testing/selftests/kvm/lib/guest_modes.c > @@ -75,10 +75,9 @@ void guest_modes_append_default(void) > { > unsigned int sz = kvm_check_cap(KVM_CAP_VM_GPA_BITS); > > - if (sz >= 52) > - guest_mode_append(VM_MODE_P52V48_4K, true); > - if (sz >= 48) > - guest_mode_append(VM_MODE_P48V48_4K, true); > + guest_mode_append(VM_MODE_P56V57_4K, sz >= 59); > + guest_mode_append(VM_MODE_P50V48_4K, sz >= 50); > + guest_mode_append(VM_MODE_P41V39_4K, sz >= 41); Even when the host doesn't support P59 a guest may still use V57 (and when a host doesn't support P50 a guest may still use V57 or V48). The host simply doesn't describe physical memory with address bit widths greater than its limits to the guest. Then the guest is free to use whatever virtual address width is supported by the MMU. IOW, we need all combinations of P and V widths for modes and then select similarly to how Arm has multiple modes to manage all the different page sizes. Also in order to know the maximum supported virtual bit width we need to get-one-reg satp_mode. We should do that here instead of in riscv_vcpu_mmu_setup() in order to filter out invalid modes when appending them. Thanks, drew > } > #endif > } > diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/selftests/kvm/lib/kvm_util.c > index a055343a7bf7..4cd69fffa06d 100644 > --- a/tools/testing/selftests/kvm/lib/kvm_util.c > +++ b/tools/testing/selftests/kvm/lib/kvm_util.c > @@ -224,6 +224,9 @@ const char *vm_guest_mode_string(uint32_t i) > [VM_MODE_P36V48_64K] = "PA-bits:36, VA-bits:48, 64K pages", > [VM_MODE_P47V47_16K] = "PA-bits:47, VA-bits:47, 16K pages", > [VM_MODE_P36V47_16K] = "PA-bits:36, VA-bits:47, 16K pages", > + [VM_MODE_P56V57_4K] = "PA-bits:56, VA-bits:57, 4K pages", > + [VM_MODE_P50V48_4K] = "PA-bits:50, VA-bits:48, 4K pages", > + [VM_MODE_P41V39_4K] = "PA-bits:41, VA-bits:39, 4K pages", > }; > _Static_assert(sizeof(strings)/sizeof(char *) == NUM_VM_MODES, > "Missing new mode strings?"); > @@ -251,6 +254,9 @@ const struct vm_guest_mode_params vm_guest_mode_params[] = { > [VM_MODE_P36V48_64K] = { 36, 48, 0x10000, 16 }, > [VM_MODE_P47V47_16K] = { 47, 47, 0x4000, 14 }, > [VM_MODE_P36V47_16K] = { 36, 47, 0x4000, 14 }, > + [VM_MODE_P56V57_4K] = { 56, 57, 0x1000, 12 }, > + [VM_MODE_P50V48_4K] = { 50, 48, 0x1000, 12 }, > + [VM_MODE_P41V39_4K] = { 41, 39, 0x1000, 12 }, > }; > _Static_assert(sizeof(vm_guest_mode_params)/sizeof(struct vm_guest_mode_params) == NUM_VM_MODES, > "Missing new mode params?"); > @@ -351,6 +357,15 @@ struct kvm_vm *____vm_create(struct vm_shape shape) > case VM_MODE_P44V64_4K: > vm->pgtable_levels = 5; > break; > + case VM_MODE_P56V57_4K: > + vm->pgtable_levels = 5; > + break; > + case VM_MODE_P50V48_4K: > + vm->pgtable_levels = 4; > + break; > + case VM_MODE_P41V39_4K: > + vm->pgtable_levels = 3; > + break; > default: > TEST_FAIL("Unknown guest mode: 0x%x", vm->mode); > } > diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c > index 2eac7d4b59e9..de84c092f982 100644 > --- a/tools/testing/selftests/kvm/lib/riscv/processor.c > +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c > @@ -197,22 +197,35 @@ void riscv_vcpu_mmu_setup(struct kvm_vcpu *vcpu) > { > struct kvm_vm *vm = vcpu->vm; > unsigned long satp; > + unsigned long satp_mode; > + unsigned long max_satp_mode; > > /* > * The RISC-V Sv48 MMU mode supports 56-bit physical address > * for 48-bit virtual address with 4KB last level page size. > */ > switch (vm->mode) { > - case VM_MODE_P52V48_4K: > - case VM_MODE_P48V48_4K: > - case VM_MODE_P40V48_4K: > + case VM_MODE_P56V57_4K: > + satp_mode = SATP_MODE_57; > + break; > + case VM_MODE_P50V48_4K: > + satp_mode = SATP_MODE_48; > + break; > + case VM_MODE_P41V39_4K: > + satp_mode = SATP_MODE_39; > break; > default: > TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); > } > > + max_satp_mode = vcpu_get_reg(vcpu, RISCV_CONFIG_REG(satp_mode)); > + > + if ((satp_mode >> SATP_MODE_SHIFT) > max_satp_mode) > + TEST_FAIL("Unable to set satp mode 0x%lx, max mode 0x%lx\n", > + satp_mode >> SATP_MODE_SHIFT, max_satp_mode); > + > satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN; > - satp |= SATP_MODE_48; > + satp |= satp_mode; > > vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(satp), satp); > } > -- > 2.43.0 -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] KVM: riscv: selftests: Add riscv vm satp modes 2025-10-17 15:38 ` Andrew Jones @ 2025-10-20 13:09 ` Wu Fei 2025-10-21 23:35 ` Andrew Jones 0 siblings, 1 reply; 13+ messages in thread From: Wu Fei @ 2025-10-20 13:09 UTC (permalink / raw) To: Andrew Jones, wu.fei9; +Cc: kvm-riscv On 10/17/25 23:38, Andrew Jones wrote: > On Fri, Oct 17, 2025 at 11:13:33AM +0800, wu.fei9@sanechips.com.cn wrote: >> Current vm modes cannot represent riscv guest modes precisely, here add >> P41V39, P50V48 and P56V57. >> >> Signed-off-by: Wu Fei <wu.fei9@sanechips.com.cn> >> --- >> .../testing/selftests/kvm/include/kvm_util.h | 7 ++++++- >> tools/testing/selftests/kvm/lib/guest_modes.c | 7 +++---- >> tools/testing/selftests/kvm/lib/kvm_util.c | 15 +++++++++++++ >> .../selftests/kvm/lib/riscv/processor.c | 21 +++++++++++++++---- >> 4 files changed, 41 insertions(+), 9 deletions(-) >> >> diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h >> index bee65ca08721..02224bc514d4 100644 >> --- a/tools/testing/selftests/kvm/include/kvm_util.h >> +++ b/tools/testing/selftests/kvm/include/kvm_util.h >> @@ -179,6 +179,11 @@ enum vm_guest_mode { >> VM_MODE_P36V48_64K, >> VM_MODE_P47V47_16K, >> VM_MODE_P36V47_16K, >> + >> + VM_MODE_P56V57_4K, /* For riscv64 */ > > This should be P59 Although sv57x4 in hgatp does support P59, sv57 itself doesn't, so guest can only address 56bits gpa. > >> + VM_MODE_P50V48_4K, >> + VM_MODE_P41V39_4K, >> + >> NUM_VM_MODES, >> }; >> >> @@ -229,7 +234,7 @@ extern enum vm_guest_mode vm_mode_default; >> #error "RISC-V 32-bit kvm selftests not supported" >> #endif >> >> -#define VM_MODE_DEFAULT VM_MODE_P40V48_4K >> +#define VM_MODE_DEFAULT VM_MODE_P50V48_4K >> #define MIN_PAGE_SHIFT 12U >> #define ptes_per_page(page_size) ((page_size) / 8) >> >> diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/selftests/kvm/lib/guest_modes.c >> index b04901e55138..63d0d5479188 100644 >> --- a/tools/testing/selftests/kvm/lib/guest_modes.c >> +++ b/tools/testing/selftests/kvm/lib/guest_modes.c >> @@ -75,10 +75,9 @@ void guest_modes_append_default(void) >> { >> unsigned int sz = kvm_check_cap(KVM_CAP_VM_GPA_BITS); >> >> - if (sz >= 52) >> - guest_mode_append(VM_MODE_P52V48_4K, true); >> - if (sz >= 48) >> - guest_mode_append(VM_MODE_P48V48_4K, true); >> + guest_mode_append(VM_MODE_P56V57_4K, sz >= 59); >> + guest_mode_append(VM_MODE_P50V48_4K, sz >= 50); >> + guest_mode_append(VM_MODE_P41V39_4K, sz >= 41); > > Even when the host doesn't support P59 a guest may still use V57 (and when > a host doesn't support P50 a guest may still use V57 or V48). The host > simply doesn't describe physical memory with address bit widths greater > than its limits to the guest. Then the guest is free to use whatever > virtual address width is supported by the MMU. IOW, we need all > combinations of P and V widths for modes and then select similarly to how > Arm has multiple modes to manage all the different page sizes. Also in > order to know the maximum supported virtual bit width we need to > get-one-reg satp_mode. We should do that here instead of in > riscv_vcpu_mmu_setup() in order to filter out invalid modes when > appending them. Make sense, modes in satp/hgatp/vsatp are independent, more discussions in next patch. Thanks, Fei. > > Thanks, > drew > >> } >> #endif >> } >> diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/selftests/kvm/lib/kvm_util.c >> index a055343a7bf7..4cd69fffa06d 100644 >> --- a/tools/testing/selftests/kvm/lib/kvm_util.c >> +++ b/tools/testing/selftests/kvm/lib/kvm_util.c >> @@ -224,6 +224,9 @@ const char *vm_guest_mode_string(uint32_t i) >> [VM_MODE_P36V48_64K] = "PA-bits:36, VA-bits:48, 64K pages", >> [VM_MODE_P47V47_16K] = "PA-bits:47, VA-bits:47, 16K pages", >> [VM_MODE_P36V47_16K] = "PA-bits:36, VA-bits:47, 16K pages", >> + [VM_MODE_P56V57_4K] = "PA-bits:56, VA-bits:57, 4K pages", >> + [VM_MODE_P50V48_4K] = "PA-bits:50, VA-bits:48, 4K pages", >> + [VM_MODE_P41V39_4K] = "PA-bits:41, VA-bits:39, 4K pages", >> }; >> _Static_assert(sizeof(strings)/sizeof(char *) == NUM_VM_MODES, >> "Missing new mode strings?"); >> @@ -251,6 +254,9 @@ const struct vm_guest_mode_params vm_guest_mode_params[] = { >> [VM_MODE_P36V48_64K] = { 36, 48, 0x10000, 16 }, >> [VM_MODE_P47V47_16K] = { 47, 47, 0x4000, 14 }, >> [VM_MODE_P36V47_16K] = { 36, 47, 0x4000, 14 }, >> + [VM_MODE_P56V57_4K] = { 56, 57, 0x1000, 12 }, >> + [VM_MODE_P50V48_4K] = { 50, 48, 0x1000, 12 }, >> + [VM_MODE_P41V39_4K] = { 41, 39, 0x1000, 12 }, >> }; >> _Static_assert(sizeof(vm_guest_mode_params)/sizeof(struct vm_guest_mode_params) == NUM_VM_MODES, >> "Missing new mode params?"); >> @@ -351,6 +357,15 @@ struct kvm_vm *____vm_create(struct vm_shape shape) >> case VM_MODE_P44V64_4K: >> vm->pgtable_levels = 5; >> break; >> + case VM_MODE_P56V57_4K: >> + vm->pgtable_levels = 5; >> + break; >> + case VM_MODE_P50V48_4K: >> + vm->pgtable_levels = 4; >> + break; >> + case VM_MODE_P41V39_4K: >> + vm->pgtable_levels = 3; >> + break; >> default: >> TEST_FAIL("Unknown guest mode: 0x%x", vm->mode); >> } >> diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c >> index 2eac7d4b59e9..de84c092f982 100644 >> --- a/tools/testing/selftests/kvm/lib/riscv/processor.c >> +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c >> @@ -197,22 +197,35 @@ void riscv_vcpu_mmu_setup(struct kvm_vcpu *vcpu) >> { >> struct kvm_vm *vm = vcpu->vm; >> unsigned long satp; >> + unsigned long satp_mode; >> + unsigned long max_satp_mode; >> >> /* >> * The RISC-V Sv48 MMU mode supports 56-bit physical address >> * for 48-bit virtual address with 4KB last level page size. >> */ >> switch (vm->mode) { >> - case VM_MODE_P52V48_4K: >> - case VM_MODE_P48V48_4K: >> - case VM_MODE_P40V48_4K: >> + case VM_MODE_P56V57_4K: >> + satp_mode = SATP_MODE_57; >> + break; >> + case VM_MODE_P50V48_4K: >> + satp_mode = SATP_MODE_48; >> + break; >> + case VM_MODE_P41V39_4K: >> + satp_mode = SATP_MODE_39; >> break; >> default: >> TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); >> } >> >> + max_satp_mode = vcpu_get_reg(vcpu, RISCV_CONFIG_REG(satp_mode)); >> + >> + if ((satp_mode >> SATP_MODE_SHIFT) > max_satp_mode) >> + TEST_FAIL("Unable to set satp mode 0x%lx, max mode 0x%lx\n", >> + satp_mode >> SATP_MODE_SHIFT, max_satp_mode); >> + >> satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN; >> - satp |= SATP_MODE_48; >> + satp |= satp_mode; >> >> vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(satp), satp); >> } >> -- >> 2.43.0 > -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] KVM: riscv: selftests: Add riscv vm satp modes 2025-10-20 13:09 ` Wu Fei @ 2025-10-21 23:35 ` Andrew Jones 0 siblings, 0 replies; 13+ messages in thread From: Andrew Jones @ 2025-10-21 23:35 UTC (permalink / raw) To: Wu Fei; +Cc: wu.fei9, kvm-riscv On Mon, Oct 20, 2025 at 09:09:52PM +0800, Wu Fei wrote: > On 10/17/25 23:38, Andrew Jones wrote: > > On Fri, Oct 17, 2025 at 11:13:33AM +0800, wu.fei9@sanechips.com.cn wrote: > > > Current vm modes cannot represent riscv guest modes precisely, here add > > > P41V39, P50V48 and P56V57. > > > > > > Signed-off-by: Wu Fei <wu.fei9@sanechips.com.cn> > > > --- > > > .../testing/selftests/kvm/include/kvm_util.h | 7 ++++++- > > > tools/testing/selftests/kvm/lib/guest_modes.c | 7 +++---- > > > tools/testing/selftests/kvm/lib/kvm_util.c | 15 +++++++++++++ > > > .../selftests/kvm/lib/riscv/processor.c | 21 +++++++++++++++---- > > > 4 files changed, 41 insertions(+), 9 deletions(-) > > > > > > diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h > > > index bee65ca08721..02224bc514d4 100644 > > > --- a/tools/testing/selftests/kvm/include/kvm_util.h > > > +++ b/tools/testing/selftests/kvm/include/kvm_util.h > > > @@ -179,6 +179,11 @@ enum vm_guest_mode { > > > VM_MODE_P36V48_64K, > > > VM_MODE_P47V47_16K, > > > VM_MODE_P36V47_16K, > > > + > > > + VM_MODE_P56V57_4K, /* For riscv64 */ > > > > This should be P59 > > Although sv57x4 in hgatp does support P59, sv57 itself doesn't, so guest can > only address 56bits gpa. Oh, right. Thanks, drew -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/2] KVM: riscv: selftests: Detect supported vm modes [not found] <20251017110908650RWBl7sDIk6WUGhkvJSH4L@zte.com.cn> 2025-10-17 3:13 ` [PATCH 1/2] KVM: riscv: selftests: Add riscv vm satp modes wu.fei9 @ 2025-10-17 3:15 ` wu.fei9 2025-10-17 16:04 ` Andrew Jones 1 sibling, 1 reply; 13+ messages in thread From: wu.fei9 @ 2025-10-17 3:15 UTC (permalink / raw) To: kvm-riscv, ajones The default vm mode on riscv is hardcoded to sv48, which causes tests to fail on platform supporting sv39 only, such as '-cpu rva23s64' on qemu. This patch detects the support vm modes and sets default to the maximum supported one. Signed-off-by: Wu Fei <wu.fei9@sanechips.com.cn> --- .../testing/selftests/kvm/include/kvm_util.h | 4 ++- .../selftests/kvm/include/riscv/processor.h | 2 ++ tools/testing/selftests/kvm/lib/guest_modes.c | 24 +++++++++---- .../selftests/kvm/lib/riscv/processor.c | 36 +++++++++++++++++++ 4 files changed, 59 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h index 02224bc514d4..7bc2ee9f0cad 100644 --- a/tools/testing/selftests/kvm/include/kvm_util.h +++ b/tools/testing/selftests/kvm/include/kvm_util.h @@ -234,7 +234,9 @@ extern enum vm_guest_mode vm_mode_default; #error "RISC-V 32-bit kvm selftests not supported" #endif -#define VM_MODE_DEFAULT VM_MODE_P50V48_4K +extern enum vm_guest_mode vm_mode_default; + +#define VM_MODE_DEFAULT vm_mode_default #define MIN_PAGE_SHIFT 12U #define ptes_per_page(page_size) ((page_size) / 8) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h index 162f303d9daa..2d5a5548e698 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -191,4 +191,6 @@ static inline void local_irq_disable(void) csr_clear(CSR_SSTATUS, SR_SIE); } +unsigned long riscv64_get_satp_mode(void); + #endif /* SELFTEST_KVM_PROCESSOR_H */ diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/selftests/kvm/lib/guest_modes.c index 63d0d5479188..9c4a9e86223e 100644 --- a/tools/testing/selftests/kvm/lib/guest_modes.c +++ b/tools/testing/selftests/kvm/lib/guest_modes.c @@ -4,7 +4,7 @@ */ #include "guest_modes.h" -#ifdef __aarch64__ +#if defined(__aarch64__) || defined(__riscv) #include "processor.h" enum vm_guest_mode vm_mode_default; #endif @@ -13,9 +13,11 @@ struct guest_mode guest_modes[NUM_VM_MODES]; void guest_modes_append_default(void) { -#ifndef __aarch64__ +#if !defined(__aarch64__) && !defined(__riscv) guest_mode_append(VM_MODE_DEFAULT, true); -#else +#endif + +#ifdef __aarch64__ { unsigned int limit = kvm_check_cap(KVM_CAP_ARM_VM_IPA_SIZE); uint32_t ipa4k, ipa16k, ipa64k; @@ -74,10 +76,20 @@ void guest_modes_append_default(void) #ifdef __riscv { unsigned int sz = kvm_check_cap(KVM_CAP_VM_GPA_BITS); + unsigned long satp_mode = riscv64_get_satp_mode() << SATP_MODE_SHIFT; + int i; - guest_mode_append(VM_MODE_P56V57_4K, sz >= 59); - guest_mode_append(VM_MODE_P50V48_4K, sz >= 50); - guest_mode_append(VM_MODE_P41V39_4K, sz >= 41); + guest_mode_append(VM_MODE_P56V57_4K, satp_mode >= SATP_MODE_57 && sz >= 59); + guest_mode_append(VM_MODE_P50V48_4K, satp_mode >= SATP_MODE_48 && sz >= 50); + guest_mode_append(VM_MODE_P41V39_4K, satp_mode >= SATP_MODE_39 && sz >= 41); + + // set the first (maximum) supported mode as default + vm_mode_default = NUM_VM_MODES; + for (i = 0; vm_mode_default == NUM_VM_MODES && i < NUM_VM_MODES; i++) { + if (guest_modes[i].supported && guest_modes[i].enabled) + vm_mode_default = i; + } + TEST_ASSERT(vm_mode_default != NUM_VM_MODES, "No supported mode!"); } #endif } diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c index de84c092f982..eac67cb21f50 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -8,6 +8,7 @@ #include <linux/compiler.h> #include <assert.h> +#include "guest_modes.h" #include "kvm_util.h" #include "processor.h" #include "ucall_common.h" @@ -528,3 +529,38 @@ unsigned long get_host_sbi_spec_version(void) return ret.value; } + +void kvm_selftest_arch_init(void) +{ + /* + * riscv64 doesn't have a true default mode, so start by detecting the + * supported vm mode. + */ + guest_modes_append_default(); +} + +unsigned long riscv64_get_satp_mode(void) +{ + int kvm_fd, vm_fd, vcpu_fd, err; + uint64_t val; + struct kvm_one_reg reg = { + .id = RISCV_CONFIG_REG(satp_mode), + .addr = (uint64_t)&val, + }; + + kvm_fd = open_kvm_dev_path_or_exit(); + vm_fd = __kvm_ioctl(kvm_fd, KVM_CREATE_VM, NULL); + TEST_ASSERT(vm_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VM, vm_fd)); + + vcpu_fd = ioctl(vm_fd, KVM_CREATE_VCPU, 0); + TEST_ASSERT(vcpu_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VCPU, vcpu_fd)); + + err = ioctl(vcpu_fd, KVM_GET_ONE_REG, ®); + TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd)); + + close(vcpu_fd); + close(vm_fd); + close(kvm_fd); + + return val; +} -- 2.43.0 -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] KVM: riscv: selftests: Detect supported vm modes 2025-10-17 3:15 ` [PATCH 2/2] KVM: riscv: selftests: Detect supported vm modes wu.fei9 @ 2025-10-17 16:04 ` Andrew Jones 2025-10-20 13:26 ` Wu Fei 0 siblings, 1 reply; 13+ messages in thread From: Andrew Jones @ 2025-10-17 16:04 UTC (permalink / raw) To: wu.fei9; +Cc: kvm-riscv On Fri, Oct 17, 2025 at 11:15:57AM +0800, wu.fei9@sanechips.com.cn wrote: > The default vm mode on riscv is hardcoded to sv48, which causes tests to > fail on platform supporting sv39 only, such as '-cpu rva23s64' on qemu. > This patch detects the support vm modes and sets default to the maximum > supported one. > > Signed-off-by: Wu Fei <wu.fei9@sanechips.com.cn> > --- > .../testing/selftests/kvm/include/kvm_util.h | 4 ++- > .../selftests/kvm/include/riscv/processor.h | 2 ++ > tools/testing/selftests/kvm/lib/guest_modes.c | 24 +++++++++---- > .../selftests/kvm/lib/riscv/processor.c | 36 +++++++++++++++++++ > 4 files changed, 59 insertions(+), 7 deletions(-) > > diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h > index 02224bc514d4..7bc2ee9f0cad 100644 > --- a/tools/testing/selftests/kvm/include/kvm_util.h > +++ b/tools/testing/selftests/kvm/include/kvm_util.h > @@ -234,7 +234,9 @@ extern enum vm_guest_mode vm_mode_default; > #error "RISC-V 32-bit kvm selftests not supported" > #endif > > -#define VM_MODE_DEFAULT VM_MODE_P50V48_4K > +extern enum vm_guest_mode vm_mode_default; We can just move this declaration out of the #ifdef __aarch64__ region. It shouldn't harm other architectures. > + > +#define VM_MODE_DEFAULT vm_mode_default > #define MIN_PAGE_SHIFT 12U > #define ptes_per_page(page_size) ((page_size) / 8) > > diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h > index 162f303d9daa..2d5a5548e698 100644 > --- a/tools/testing/selftests/kvm/include/riscv/processor.h > +++ b/tools/testing/selftests/kvm/include/riscv/processor.h > @@ -191,4 +191,6 @@ static inline void local_irq_disable(void) > csr_clear(CSR_SSTATUS, SR_SIE); > } > > +unsigned long riscv64_get_satp_mode(void); > + > #endif /* SELFTEST_KVM_PROCESSOR_H */ > diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/selftests/kvm/lib/guest_modes.c > index 63d0d5479188..9c4a9e86223e 100644 > --- a/tools/testing/selftests/kvm/lib/guest_modes.c > +++ b/tools/testing/selftests/kvm/lib/guest_modes.c > @@ -4,7 +4,7 @@ > */ > #include "guest_modes.h" > > -#ifdef __aarch64__ > +#if defined(__aarch64__) || defined(__riscv) > #include "processor.h" > enum vm_guest_mode vm_mode_default; > #endif > @@ -13,9 +13,11 @@ struct guest_mode guest_modes[NUM_VM_MODES]; > > void guest_modes_append_default(void) > { > -#ifndef __aarch64__ > +#if !defined(__aarch64__) && !defined(__riscv) > guest_mode_append(VM_MODE_DEFAULT, true); > -#else > +#endif > + > +#ifdef __aarch64__ > { > unsigned int limit = kvm_check_cap(KVM_CAP_ARM_VM_IPA_SIZE); > uint32_t ipa4k, ipa16k, ipa64k; > @@ -74,10 +76,20 @@ void guest_modes_append_default(void) > #ifdef __riscv > { > unsigned int sz = kvm_check_cap(KVM_CAP_VM_GPA_BITS); > + unsigned long satp_mode = riscv64_get_satp_mode() << SATP_MODE_SHIFT; > + int i; > > - guest_mode_append(VM_MODE_P56V57_4K, sz >= 59); > - guest_mode_append(VM_MODE_P50V48_4K, sz >= 50); > - guest_mode_append(VM_MODE_P41V39_4K, sz >= 41); > + guest_mode_append(VM_MODE_P56V57_4K, satp_mode >= SATP_MODE_57 && sz >= 59); > + guest_mode_append(VM_MODE_P50V48_4K, satp_mode >= SATP_MODE_48 && sz >= 50); > + guest_mode_append(VM_MODE_P41V39_4K, satp_mode >= SATP_MODE_39 && sz >= 41); Something along these lines was what I was suggesting in the last patch, but where we select from many more combinations of P and V for modes. VM_MODE_P41V39_4K VM_MODE_P41V48_4K VM_MODE_P41V57_4K VM_MODE_P50V48_4K VM_MODE_P50V57_4K VM_MODE_P59V57_4K > + > + // set the first (maximum) supported mode as default Please, no C++ comments, and don't we want a V39 mode to be the default? In fact, VM_MODE_P41V39_4K should always be supported, so we can just set VM_MODE_DEFAULT to that. Thanks, drew > + vm_mode_default = NUM_VM_MODES; > + for (i = 0; vm_mode_default == NUM_VM_MODES && i < NUM_VM_MODES; i++) { > + if (guest_modes[i].supported && guest_modes[i].enabled) > + vm_mode_default = i; > + } > + TEST_ASSERT(vm_mode_default != NUM_VM_MODES, "No supported mode!"); > } > #endif > } > diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c > index de84c092f982..eac67cb21f50 100644 > --- a/tools/testing/selftests/kvm/lib/riscv/processor.c > +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c > @@ -8,6 +8,7 @@ > #include <linux/compiler.h> > #include <assert.h> > > +#include "guest_modes.h" > #include "kvm_util.h" > #include "processor.h" > #include "ucall_common.h" > @@ -528,3 +529,38 @@ unsigned long get_host_sbi_spec_version(void) > > return ret.value; > } > + > +void kvm_selftest_arch_init(void) > +{ > + /* > + * riscv64 doesn't have a true default mode, so start by detecting the > + * supported vm mode. > + */ > + guest_modes_append_default(); > +} > + > +unsigned long riscv64_get_satp_mode(void) > +{ > + int kvm_fd, vm_fd, vcpu_fd, err; > + uint64_t val; > + struct kvm_one_reg reg = { > + .id = RISCV_CONFIG_REG(satp_mode), > + .addr = (uint64_t)&val, > + }; > + > + kvm_fd = open_kvm_dev_path_or_exit(); > + vm_fd = __kvm_ioctl(kvm_fd, KVM_CREATE_VM, NULL); > + TEST_ASSERT(vm_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VM, vm_fd)); > + > + vcpu_fd = ioctl(vm_fd, KVM_CREATE_VCPU, 0); > + TEST_ASSERT(vcpu_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VCPU, vcpu_fd)); > + > + err = ioctl(vcpu_fd, KVM_GET_ONE_REG, ®); > + TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd)); > + > + close(vcpu_fd); > + close(vm_fd); > + close(kvm_fd); > + > + return val; > +} > -- > 2.43.0 -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] KVM: riscv: selftests: Detect supported vm modes 2025-10-17 16:04 ` Andrew Jones @ 2025-10-20 13:26 ` Wu Fei 2025-10-20 19:32 ` Radim Krčmář 0 siblings, 1 reply; 13+ messages in thread From: Wu Fei @ 2025-10-20 13:26 UTC (permalink / raw) To: Andrew Jones, wu.fei9; +Cc: kvm-riscv On 10/18/25 00:04, Andrew Jones wrote: > On Fri, Oct 17, 2025 at 11:15:57AM +0800, wu.fei9@sanechips.com.cn wrote: >> The default vm mode on riscv is hardcoded to sv48, which causes tests to >> fail on platform supporting sv39 only, such as '-cpu rva23s64' on qemu. >> This patch detects the support vm modes and sets default to the maximum >> supported one. >> >> Signed-off-by: Wu Fei <wu.fei9@sanechips.com.cn> >> --- >> .../testing/selftests/kvm/include/kvm_util.h | 4 ++- >> .../selftests/kvm/include/riscv/processor.h | 2 ++ >> tools/testing/selftests/kvm/lib/guest_modes.c | 24 +++++++++---- >> .../selftests/kvm/lib/riscv/processor.c | 36 +++++++++++++++++++ >> 4 files changed, 59 insertions(+), 7 deletions(-) >> >> diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h >> index 02224bc514d4..7bc2ee9f0cad 100644 >> --- a/tools/testing/selftests/kvm/include/kvm_util.h >> +++ b/tools/testing/selftests/kvm/include/kvm_util.h >> @@ -234,7 +234,9 @@ extern enum vm_guest_mode vm_mode_default; >> #error "RISC-V 32-bit kvm selftests not supported" >> #endif >> >> -#define VM_MODE_DEFAULT VM_MODE_P50V48_4K >> +extern enum vm_guest_mode vm_mode_default; > > We can just move this declaration out of the #ifdef __aarch64__ region. > It shouldn't harm other architectures. OK. > >> + >> +#define VM_MODE_DEFAULT vm_mode_default >> #define MIN_PAGE_SHIFT 12U >> #define ptes_per_page(page_size) ((page_size) / 8) >> >> diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h >> index 162f303d9daa..2d5a5548e698 100644 >> --- a/tools/testing/selftests/kvm/include/riscv/processor.h >> +++ b/tools/testing/selftests/kvm/include/riscv/processor.h >> @@ -191,4 +191,6 @@ static inline void local_irq_disable(void) >> csr_clear(CSR_SSTATUS, SR_SIE); >> } >> >> +unsigned long riscv64_get_satp_mode(void); >> + >> #endif /* SELFTEST_KVM_PROCESSOR_H */ >> diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/selftests/kvm/lib/guest_modes.c >> index 63d0d5479188..9c4a9e86223e 100644 >> --- a/tools/testing/selftests/kvm/lib/guest_modes.c >> +++ b/tools/testing/selftests/kvm/lib/guest_modes.c >> @@ -4,7 +4,7 @@ >> */ >> #include "guest_modes.h" >> >> -#ifdef __aarch64__ >> +#if defined(__aarch64__) || defined(__riscv) >> #include "processor.h" >> enum vm_guest_mode vm_mode_default; >> #endif >> @@ -13,9 +13,11 @@ struct guest_mode guest_modes[NUM_VM_MODES]; >> >> void guest_modes_append_default(void) >> { >> -#ifndef __aarch64__ >> +#if !defined(__aarch64__) && !defined(__riscv) >> guest_mode_append(VM_MODE_DEFAULT, true); >> -#else >> +#endif >> + >> +#ifdef __aarch64__ >> { >> unsigned int limit = kvm_check_cap(KVM_CAP_ARM_VM_IPA_SIZE); >> uint32_t ipa4k, ipa16k, ipa64k; >> @@ -74,10 +76,20 @@ void guest_modes_append_default(void) >> #ifdef __riscv >> { >> unsigned int sz = kvm_check_cap(KVM_CAP_VM_GPA_BITS); >> + unsigned long satp_mode = riscv64_get_satp_mode() << SATP_MODE_SHIFT; >> + int i; >> >> - guest_mode_append(VM_MODE_P56V57_4K, sz >= 59); >> - guest_mode_append(VM_MODE_P50V48_4K, sz >= 50); >> - guest_mode_append(VM_MODE_P41V39_4K, sz >= 41); >> + guest_mode_append(VM_MODE_P56V57_4K, satp_mode >= SATP_MODE_57 && sz >= 59); >> + guest_mode_append(VM_MODE_P50V48_4K, satp_mode >= SATP_MODE_48 && sz >= 50); >> + guest_mode_append(VM_MODE_P41V39_4K, satp_mode >= SATP_MODE_39 && sz >= 41); > > Something along these lines was what I was suggesting in the last patch, > but where we select from many more combinations of P and V for modes. > > VM_MODE_P41V39_4K > VM_MODE_P41V48_4K > VM_MODE_P41V57_4K > VM_MODE_P50V48_4K > VM_MODE_P50V57_4K > VM_MODE_P59V57_4K Do we need more? e.g. for sv39, there could be P50V39 and P56V39. > >> + >> + // set the first (maximum) supported mode as default > > Please, no C++ comments, and don't we want a V39 mode to be the default? > In fact, VM_MODE_P41V39_4K should always be supported, so we can just set > VM_MODE_DEFAULT to that. It's likely the maximum supported mode is the most common configuration on production? Thanks, Fei. > > Thanks, > drew > >> + vm_mode_default = NUM_VM_MODES; >> + for (i = 0; vm_mode_default == NUM_VM_MODES && i < NUM_VM_MODES; i++) { >> + if (guest_modes[i].supported && guest_modes[i].enabled) >> + vm_mode_default = i; >> + } >> + TEST_ASSERT(vm_mode_default != NUM_VM_MODES, "No supported mode!"); >> } >> #endif >> } >> diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c >> index de84c092f982..eac67cb21f50 100644 >> --- a/tools/testing/selftests/kvm/lib/riscv/processor.c >> +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c >> @@ -8,6 +8,7 @@ >> #include <linux/compiler.h> >> #include <assert.h> >> >> +#include "guest_modes.h" >> #include "kvm_util.h" >> #include "processor.h" >> #include "ucall_common.h" >> @@ -528,3 +529,38 @@ unsigned long get_host_sbi_spec_version(void) >> >> return ret.value; >> } >> + >> +void kvm_selftest_arch_init(void) >> +{ >> + /* >> + * riscv64 doesn't have a true default mode, so start by detecting the >> + * supported vm mode. >> + */ >> + guest_modes_append_default(); >> +} >> + >> +unsigned long riscv64_get_satp_mode(void) >> +{ >> + int kvm_fd, vm_fd, vcpu_fd, err; >> + uint64_t val; >> + struct kvm_one_reg reg = { >> + .id = RISCV_CONFIG_REG(satp_mode), >> + .addr = (uint64_t)&val, >> + }; >> + >> + kvm_fd = open_kvm_dev_path_or_exit(); >> + vm_fd = __kvm_ioctl(kvm_fd, KVM_CREATE_VM, NULL); >> + TEST_ASSERT(vm_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VM, vm_fd)); >> + >> + vcpu_fd = ioctl(vm_fd, KVM_CREATE_VCPU, 0); >> + TEST_ASSERT(vcpu_fd >= 0, KVM_IOCTL_ERROR(KVM_CREATE_VCPU, vcpu_fd)); >> + >> + err = ioctl(vcpu_fd, KVM_GET_ONE_REG, ®); >> + TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd)); >> + >> + close(vcpu_fd); >> + close(vm_fd); >> + close(kvm_fd); >> + >> + return val; >> +} >> -- >> 2.43.0 > -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] KVM: riscv: selftests: Detect supported vm modes 2025-10-20 13:26 ` Wu Fei @ 2025-10-20 19:32 ` Radim Krčmář 2025-10-21 23:55 ` Andrew Jones 0 siblings, 1 reply; 13+ messages in thread From: Radim Krčmář @ 2025-10-20 19:32 UTC (permalink / raw) To: Wu Fei, Andrew Jones, wu.fei9; +Cc: kvm-riscv, kvm-riscv 2025-10-20T21:26:18+08:00, Wu Fei <atwufei@163.com>: > On 10/18/25 00:04, Andrew Jones wrote: >>> - guest_mode_append(VM_MODE_P56V57_4K, sz >= 59); >>> - guest_mode_append(VM_MODE_P50V48_4K, sz >= 50); >>> - guest_mode_append(VM_MODE_P41V39_4K, sz >= 41); >>> + guest_mode_append(VM_MODE_P56V57_4K, satp_mode >= SATP_MODE_57 && sz >= 59); >>> + guest_mode_append(VM_MODE_P50V48_4K, satp_mode >= SATP_MODE_48 && sz >= 50); >>> + guest_mode_append(VM_MODE_P41V39_4K, satp_mode >= SATP_MODE_39 && sz >= 41); >> >> Something along these lines was what I was suggesting in the last patch, >> but where we select from many more combinations of P and V for modes. >> >> VM_MODE_P41V39_4K >> VM_MODE_P41V48_4K >> VM_MODE_P41V57_4K >> VM_MODE_P50V48_4K >> VM_MODE_P50V57_4K >> VM_MODE_P59V57_4K > > Do we need more? e.g. for sv39, there could be P50V39 and P56V39. Bare is probably the most important first stage mode, as it's the only one that might fully test the two extra bits of Sv57x4. I think a single combination per "x4" mode might be sufficient, since all non-bare first stages generate 56-bit physical addresses anyway, but it makes sense to have all of them if we're doing more than one. >> >>> + >>> + // set the first (maximum) supported mode as default >> >> Please, no C++ comments, and don't we want a V39 mode to be the default? >> In fact, VM_MODE_P41V39_4K should always be supported, so we can just set >> VM_MODE_DEFAULT to that. > > It's likely the maximum supported mode is the most common configuration > on production? Yes, KVM currently picks the widest mode, although I think the optimal choice of hgatp is the smallest one that fully covers the whole guest physical address space. (e.g. if all guest memory is mapped below 2 TiB, KVM should pick Sv39x4 for its hgatp, regardless of what is the widest supported mode.) -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] KVM: riscv: selftests: Detect supported vm modes 2025-10-20 19:32 ` Radim Krčmář @ 2025-10-21 23:55 ` Andrew Jones 2025-10-22 13:13 ` Wu Fei 0 siblings, 1 reply; 13+ messages in thread From: Andrew Jones @ 2025-10-21 23:55 UTC (permalink / raw) To: Radim Krčmář; +Cc: Wu Fei, wu.fei9, kvm-riscv, kvm-riscv On Mon, Oct 20, 2025 at 09:32:57PM +0200, Radim Krčmář wrote: > 2025-10-20T21:26:18+08:00, Wu Fei <atwufei@163.com>: > > On 10/18/25 00:04, Andrew Jones wrote: > >>> - guest_mode_append(VM_MODE_P56V57_4K, sz >= 59); > >>> - guest_mode_append(VM_MODE_P50V48_4K, sz >= 50); > >>> - guest_mode_append(VM_MODE_P41V39_4K, sz >= 41); > >>> + guest_mode_append(VM_MODE_P56V57_4K, satp_mode >= SATP_MODE_57 && sz >= 59); > >>> + guest_mode_append(VM_MODE_P50V48_4K, satp_mode >= SATP_MODE_48 && sz >= 50); > >>> + guest_mode_append(VM_MODE_P41V39_4K, satp_mode >= SATP_MODE_39 && sz >= 41); > >> > >> Something along these lines was what I was suggesting in the last patch, > >> but where we select from many more combinations of P and V for modes. > >> > >> VM_MODE_P41V39_4K > >> VM_MODE_P41V48_4K > >> VM_MODE_P41V57_4K > >> VM_MODE_P50V48_4K > >> VM_MODE_P50V57_4K > >> VM_MODE_P59V57_4K > > > > Do we need more? e.g. for sv39, there could be P50V39 and P56V39. > > Bare is probably the most important first stage mode, as it's the only > one that might fully test the two extra bits of Sv57x4. Indeed, but for that we need a mode named something like VM_MODE_BARE59. > > I think a single combination per "x4" mode might be sufficient, since > all non-bare first stages generate 56-bit physical addresses anyway, but > it makes sense to have all of them if we're doing more than one. Yeah, might as well. > > >> > >>> + > >>> + // set the first (maximum) supported mode as default > >> > >> Please, no C++ comments, and don't we want a V39 mode to be the default? > >> In fact, VM_MODE_P41V39_4K should always be supported, so we can just set > >> VM_MODE_DEFAULT to that. > > > > It's likely the maximum supported mode is the most common configuration > > on production? > > Yes, KVM currently picks the widest mode, although I think the optimal > choice of hgatp is the smallest one that fully covers the whole guest > physical address space. > > (e.g. if all guest memory is mapped below 2 TiB, KVM should pick Sv39x4 > for its hgatp, regardless of what is the widest supported mode.) Yes, and for the tests, I think the guest config can just default to the minimal. Tests that need particular modes can select them when supported. We ensure tests run the same code on all hosts this way when the mode selected isn't what's under test. Thanks, drew -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] KVM: riscv: selftests: Detect supported vm modes 2025-10-21 23:55 ` Andrew Jones @ 2025-10-22 13:13 ` Wu Fei 2025-10-22 14:26 ` Radim Krčmář 0 siblings, 1 reply; 13+ messages in thread From: Wu Fei @ 2025-10-22 13:13 UTC (permalink / raw) To: Andrew Jones, Radim Krčmář; +Cc: wu.fei9, kvm-riscv, kvm-riscv On 10/22/25 07:55, Andrew Jones wrote: > On Mon, Oct 20, 2025 at 09:32:57PM +0200, Radim Krčmář wrote: >> 2025-10-20T21:26:18+08:00, Wu Fei <atwufei@163.com>: >>> On 10/18/25 00:04, Andrew Jones wrote: >>>>> - guest_mode_append(VM_MODE_P56V57_4K, sz >= 59); >>>>> - guest_mode_append(VM_MODE_P50V48_4K, sz >= 50); >>>>> - guest_mode_append(VM_MODE_P41V39_4K, sz >= 41); >>>>> + guest_mode_append(VM_MODE_P56V57_4K, satp_mode >= SATP_MODE_57 && sz >= 59); >>>>> + guest_mode_append(VM_MODE_P50V48_4K, satp_mode >= SATP_MODE_48 && sz >= 50); >>>>> + guest_mode_append(VM_MODE_P41V39_4K, satp_mode >= SATP_MODE_39 && sz >= 41); >>>> >>>> Something along these lines was what I was suggesting in the last patch, >>>> but where we select from many more combinations of P and V for modes. >>>> >>>> VM_MODE_P41V39_4K >>>> VM_MODE_P41V48_4K >>>> VM_MODE_P41V57_4K >>>> VM_MODE_P50V48_4K >>>> VM_MODE_P50V57_4K >>>> VM_MODE_P59V57_4K >>> >>> Do we need more? e.g. for sv39, there could be P50V39 and P56V39. >> >> Bare is probably the most important first stage mode, as it's the only >> one that might fully test the two extra bits of Sv57x4. > > Indeed, but for that we need a mode named something like VM_MODE_BARE59. The current code has some assumption on non-bare mode, such as virt_map. It looks not trivial to support BARE mode. Is it okay to focus on non-bare mode in this series, and leave bare mode support to another patchset?> >> >> I think a single combination per "x4" mode might be sufficient, since >> all non-bare first stages generate 56-bit physical addresses anyway, but >> it makes sense to have all of them if we're doing more than one. > > Yeah, might as well. Add all of them? > >> >>>> >>>>> + >>>>> + // set the first (maximum) supported mode as default >>>> >>>> Please, no C++ comments, and don't we want a V39 mode to be the default? >>>> In fact, VM_MODE_P41V39_4K should always be supported, so we can just set >>>> VM_MODE_DEFAULT to that. >>> >>> It's likely the maximum supported mode is the most common configuration >>> on production? >> >> Yes, KVM currently picks the widest mode, although I think the optimal >> choice of hgatp is the smallest one that fully covers the whole guest >> physical address space. >> >> (e.g. if all guest memory is mapped below 2 TiB, KVM should pick Sv39x4 >> for its hgatp, regardless of what is the widest supported mode.) > > Yes, and for the tests, I think the guest config can just default to the > minimal. Tests that need particular modes can select them when supported. > We ensure tests run the same code on all hosts this way when the mode > selected isn't what's under test. OK. Thanks, Fei. > > Thanks, > drew -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] KVM: riscv: selftests: Detect supported vm modes 2025-10-22 13:13 ` Wu Fei @ 2025-10-22 14:26 ` Radim Krčmář 2025-10-24 13:48 ` Wu Fei 0 siblings, 1 reply; 13+ messages in thread From: Radim Krčmář @ 2025-10-22 14:26 UTC (permalink / raw) To: Wu Fei, Andrew Jones; +Cc: wu.fei9, kvm-riscv, kvm-riscv 2025-10-22T21:13:08+08:00, Wu Fei <atwufei@163.com>: > On 10/22/25 07:55, Andrew Jones wrote: >> On Mon, Oct 20, 2025 at 09:32:57PM +0200, Radim Krčmář wrote: >>> 2025-10-20T21:26:18+08:00, Wu Fei <atwufei@163.com>: >>>> On 10/18/25 00:04, Andrew Jones wrote: >>>>>> - guest_mode_append(VM_MODE_P56V57_4K, sz >= 59); >>>>>> - guest_mode_append(VM_MODE_P50V48_4K, sz >= 50); >>>>>> - guest_mode_append(VM_MODE_P41V39_4K, sz >= 41); >>>>>> + guest_mode_append(VM_MODE_P56V57_4K, satp_mode >= SATP_MODE_57 && sz >= 59); >>>>>> + guest_mode_append(VM_MODE_P50V48_4K, satp_mode >= SATP_MODE_48 && sz >= 50); >>>>>> + guest_mode_append(VM_MODE_P41V39_4K, satp_mode >= SATP_MODE_39 && sz >= 41); >>>>> >>>>> Something along these lines was what I was suggesting in the last patch, >>>>> but where we select from many more combinations of P and V for modes. >>>>> >>>>> VM_MODE_P41V39_4K >>>>> VM_MODE_P41V48_4K >>>>> VM_MODE_P41V57_4K >>>>> VM_MODE_P50V48_4K >>>>> VM_MODE_P50V57_4K >>>>> VM_MODE_P59V57_4K >>>> >>>> Do we need more? e.g. for sv39, there could be P50V39 and P56V39. >>> >>> Bare is probably the most important first stage mode, as it's the only >>> one that might fully test the two extra bits of Sv57x4. >> >> Indeed, but for that we need a mode named something like VM_MODE_BARE59. > > The current code has some assumption on non-bare mode, such as virt_map. > It looks not trivial to support BARE mode. Is it okay to focus on > non-bare mode in this series, and leave bare mode support to another > patchset?> Of course. There is no point in adding symbols that are not used. >>> I think a single combination per "x4" mode might be sufficient, since >>> all non-bare first stages generate 56-bit physical addresses anyway, but >>> it makes sense to have all of them if we're doing more than one. >> >> Yeah, might as well. > > Add all of them? Tests cannot choose hgatp; KVM just tells us that the physical width is. This means that we must support the following: VM_MODE_P41V39_4K VM_MODE_P50V39_4K VM_MODE_P59V39_4K I don't think it's correct to assume that when SvABx4 is supported, then SvAB is supported, hence we must have Sv39 for each hgatp mode that KVM supports. And shouldn't it be invalid to pick VM_MODE_P41V39_4K when KVM is using Sv48x4? For tests that that don't care about physical width, we could add: VM_MODE_PXXV39_4K It doesn't seem necessary to support more than that, but if our tests want larger virtual address space, we can add V48 and V57 variants. Thanks. -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] KVM: riscv: selftests: Detect supported vm modes 2025-10-22 14:26 ` Radim Krčmář @ 2025-10-24 13:48 ` Wu Fei 2025-10-24 15:59 ` Radim Krčmář 0 siblings, 1 reply; 13+ messages in thread From: Wu Fei @ 2025-10-24 13:48 UTC (permalink / raw) To: Radim Krčmář, Andrew Jones; +Cc: wu.fei9, kvm-riscv, kvm-riscv On 10/22/25 22:26, Radim Krčmář wrote: > 2025-10-22T21:13:08+08:00, Wu Fei <atwufei@163.com>: >> On 10/22/25 07:55, Andrew Jones wrote: >>> On Mon, Oct 20, 2025 at 09:32:57PM +0200, Radim Krčmář wrote: >>>> 2025-10-20T21:26:18+08:00, Wu Fei <atwufei@163.com>: >>>>> On 10/18/25 00:04, Andrew Jones wrote: >>>>>>> - guest_mode_append(VM_MODE_P56V57_4K, sz >= 59); >>>>>>> - guest_mode_append(VM_MODE_P50V48_4K, sz >= 50); >>>>>>> - guest_mode_append(VM_MODE_P41V39_4K, sz >= 41); >>>>>>> + guest_mode_append(VM_MODE_P56V57_4K, satp_mode >= SATP_MODE_57 && sz >= 59); >>>>>>> + guest_mode_append(VM_MODE_P50V48_4K, satp_mode >= SATP_MODE_48 && sz >= 50); >>>>>>> + guest_mode_append(VM_MODE_P41V39_4K, satp_mode >= SATP_MODE_39 && sz >= 41); >>>>>> >>>>>> Something along these lines was what I was suggesting in the last patch, >>>>>> but where we select from many more combinations of P and V for modes. >>>>>> >>>>>> VM_MODE_P41V39_4K >>>>>> VM_MODE_P41V48_4K >>>>>> VM_MODE_P41V57_4K >>>>>> VM_MODE_P50V48_4K >>>>>> VM_MODE_P50V57_4K >>>>>> VM_MODE_P59V57_4K >>>>> >>>>> Do we need more? e.g. for sv39, there could be P50V39 and P56V39. >>>> >>>> Bare is probably the most important first stage mode, as it's the only >>>> one that might fully test the two extra bits of Sv57x4. >>> >>> Indeed, but for that we need a mode named something like VM_MODE_BARE59. >> >> The current code has some assumption on non-bare mode, such as virt_map. >> It looks not trivial to support BARE mode. Is it okay to focus on >> non-bare mode in this series, and leave bare mode support to another >> patchset?> > > Of course. There is no point in adding symbols that are not used. > >>>> I think a single combination per "x4" mode might be sufficient, since >>>> all non-bare first stages generate 56-bit physical addresses anyway, but >>>> it makes sense to have all of them if we're doing more than one. >>> >>> Yeah, might as well. >> >> Add all of them? > > Tests cannot choose hgatp; KVM just tells us that the physical width is. > This means that we must support the following: > > VM_MODE_P41V39_4K > VM_MODE_P50V39_4K > VM_MODE_P59V39_4K > > I don't think it's correct to assume that when SvABx4 is supported, then > SvAB is supported, hence we must have Sv39 for each hgatp mode that KVM > supports. Agreed. > > And shouldn't it be invalid to pick VM_MODE_P41V39_4K when KVM is using > Sv48x4? Agreed, P41 is not a good candidate for Sv48x4. > For tests that that don't care about physical width, we could > add: > > VM_MODE_PXXV39_4K Intel adds VM_MODE_PXXV48_4K because "x86_64 machines are having various physical address width rather than some static values" according to commit 567a9f1e9de, and x86 has to probe the real gpa width on vm creation. RISC-V has 3 fixed gpa widths, so maybe we can use the explicit widths? > > It doesn't seem necessary to support more than that, but if our tests > want larger virtual address space, we can add V48 and V57 variants. I think V48/V57 is necessary, if a machine is designed to have SV48 guests, it's better to test it. So is it okay to have the combination of all 9 modes? P(41, 50, 56) x V(39, 48, 57) But only several ones are picked up for a specific machine, just as mentioned above, we won't select P41V39 for Sv48x4 etc. Thanks, Fei. > > Thanks. -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] KVM: riscv: selftests: Detect supported vm modes 2025-10-24 13:48 ` Wu Fei @ 2025-10-24 15:59 ` Radim Krčmář 0 siblings, 0 replies; 13+ messages in thread From: Radim Krčmář @ 2025-10-24 15:59 UTC (permalink / raw) To: Wu Fei, Andrew Jones; +Cc: wu.fei9, kvm-riscv, kvm-riscv 2025-10-24T21:48:01+08:00, Wu Fei <atwufei@163.com>: > On 10/22/25 22:26, Radim Krčmář wrote: >> For tests that that don't care about physical width, we could >> add: >> >> VM_MODE_PXXV39_4K > > Intel adds VM_MODE_PXXV48_4K because "x86_64 machines are having various > physical address width rather than some static values" according to > commit 567a9f1e9de, and x86 has to probe the real gpa width on vm > creation. RISC-V has 3 fixed gpa widths, so maybe we can use the > explicit widths? Makes sense. >> It doesn't seem necessary to support more than that, but if our tests >> want larger virtual address space, we can add V48 and V57 variants. > > I think V48/V57 is necessary, if a machine is designed to have SV48 > guests, it's better to test it. Right. We also get information about available guest satp modes from KVM, so we ought to test that it was correct. > So is it okay to have the combination of all 9 modes? > P(41, 50, 56) x V(39, 48, 57) > But only several ones are picked up for a specific machine, just as > mentioned above, we won't select P41V39 for Sv48x4 etc. Sounds good, thanks. -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv ^ permalink raw reply [flat|nested] 13+ messages in thread
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2025-10-17 3:13 ` [PATCH 1/2] KVM: riscv: selftests: Add riscv vm satp modes wu.fei9
2025-10-17 15:38 ` Andrew Jones
2025-10-20 13:09 ` Wu Fei
2025-10-21 23:35 ` Andrew Jones
2025-10-17 3:15 ` [PATCH 2/2] KVM: riscv: selftests: Detect supported vm modes wu.fei9
2025-10-17 16:04 ` Andrew Jones
2025-10-20 13:26 ` Wu Fei
2025-10-20 19:32 ` Radim Krčmář
2025-10-21 23:55 ` Andrew Jones
2025-10-22 13:13 ` Wu Fei
2025-10-22 14:26 ` Radim Krčmář
2025-10-24 13:48 ` Wu Fei
2025-10-24 15:59 ` Radim Krčmář
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