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From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Benedikt Freisen" <b.freisen@gmx.net>, <opensbi@lists.infradead.org>
Cc: "opensbi" <opensbi-bounces@lists.infradead.org>
Subject: Re: [PATCH 2/5] lib: sbi: Workaround for FENCE(.I) errata on C906, C910.
Date: Mon, 27 Oct 2025 12:16:46 +0100	[thread overview]
Message-ID: <DDT294QB5R6U.1SC7974LHM7K6@ventanamicro.com> (raw)
In-Reply-To: <20251026202416.23550-3-b.freisen@gmx.net>

2025-10-26T21:21:56+01:00, Benedikt Freisen <b.freisen@gmx.net>:
> According to the RISCVuzz paper by Thomas et al., the T-Head/Xuantie C906
> and C910 cores fail to ignore reserved fields in the "fence" and "fence.i"
> encodings and trigger illegal instruction traps if these fields are non-zero,
> so address that in the illegal instruction trap handler.
>
> Signed-off-by: Benedikt Freisen <b.freisen@gmx.net>
> ---
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> @@ -944,8 +944,12 @@
> +#define INSN_MASK_FENCE			0xf000707f

Bits 31, 30, 29, and 28 should not be a part of the mask, because any
reserved value there must be treated as 0b0000.

> +#define INSN_MATCH_FENCE		0x0000000f
>  #define INSN_MASK_FENCE_TSO		0xffffffff

(Related: INSN_MASK_FENCE_TSO should ignore the reserved rs1/rd fields,
 but covering that encoding with the new IORW fence is acceptable.)

>  #define INSN_MATCH_FENCE_TSO		0x8330000f
> +#define INSN_MASK_FENCE_I		0x0000707f
> +#define INSN_MATCH_FENCE_I		0x0000100f
> diff --git a/lib/sbi/sbi_illegal_insn.c b/lib/sbi/sbi_illegal_insn.c
> @@ -42,6 +42,21 @@ static int misc_mem_opcode_insn(ulong insn, struct sbi_trap_regs *regs)
> +	/* Errata workaround: C906, C910 fail to ignore reserved fields
> +	 * in the `fence` and `fence.i` encodings. [Thomas2024RISCVuzz] */
> +	if ((insn & INSN_MASK_FENCE) == INSN_MATCH_FENCE) {
> +		/* NOTE: Emulation should ideally preserve the `pred` and
> +		 * `succ` fields, but that is not easily possible here. */
> +		mb();
> +		regs->mepc += 4;
> +		return 0;
> +	}
> +	if ((insn & INSN_MASK_FENCE_I) == INSN_MATCH_FENCE_I) {
> +		RISCV_FENCE_I;
> +		regs->mepc += 4;
> +		return 0;
> +	}

Don't we want to hide these workarounds behind a config, so the code
doesn't have to be included in builds for other platorms?

Thanks.

-- 
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  reply	other threads:[~2025-10-27 11:17 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-26 20:21 [PATCH] Add trap-based ISA extension emulation Benedikt Freisen
2025-10-26 20:21 ` [PATCH 1/5] include: sbi: Fix tab alignment Benedikt Freisen
2025-10-26 20:21 ` [PATCH 2/5] lib: sbi: Workaround for FENCE(.I) errata on C906, C910 Benedikt Freisen
2025-10-27 11:16   ` Radim Krčmář [this message]
2025-10-26 20:21 ` [PATCH 3/5] include: sbi: Make "s8" actually signed Benedikt Freisen
2025-10-27 11:18   ` Radim Krčmář
2025-10-26 20:21 ` [PATCH 4/5] lib: sbi: ISA extension emulation Benedikt Freisen
2025-10-27 22:41   ` Inochi Amaoto
2025-10-30  2:51   ` Xiang W
2025-10-26 20:21 ` [PATCH 5/5] doc: Add isa-ext-emu documentation block to README Benedikt Freisen
2025-10-27 10:02 ` [PATCH] Add trap-based ISA extension emulation Xiang W
2025-10-27 11:09   ` Benedikt Freisen
2025-10-27 22:56 ` Bo Gan

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