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From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Yunhui Cui" <cuiyunhui@bytedance.com>, <conor@kernel.org>,
	<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <alex@ghiti.fr>,
	<luxu.kernel@bytedance.com>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <jassisinghbrar@gmail.com>,
	<conor.dooley@microchip.com>,
	<valentina.fernandezalanis@microchip.com>,
	<catalin.marinas@arm.com>, <will@kernel.org>, <maz@kernel.org>,
	<timothy.hayes@arm.com>, <lpieralisi@kernel.org>, <arnd@arndb.de>,
	<kees@kernel.org>, <tglx@linutronix.de>,
	<viresh.kumar@linaro.org>, <boqun.feng@gmail.com>,
	<linux-arm-kernel@lists.infradead.org>, <cleger@rivosinc.com>,
	<atishp@rivosinc.com>, <ajones@ventanamicro.com>
Cc: "linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v3 5/8] riscv: smp: use NMI for CPU stop
Date: Thu, 04 Dec 2025 13:07:20 +0900	[thread overview]
Message-ID: <DEP4X1DAIOU5.2WLIV4BMWLMRR@ventanamicro.com> (raw)
In-Reply-To: <20251127125305.89961-6-cuiyunhui@bytedance.com>

2025-11-27T20:53:02+08:00, Yunhui Cui <cuiyunhui@bytedance.com>:
> Use NMI instead of IPI for CPU stop if RISC-V SSE NMI is supported.
>
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> ---
> diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware/riscv/riscv_sse_nmi.c
> @@ -58,6 +58,7 @@ static int local_nmi_handler(u32 evt, void *arg, struct pt_regs *regs)
>  	type = atomic_read(this_cpu_ptr(&local_nmi));
>  
>  	NMI_HANDLE(LOCAL_NMI_CRASH, cpu_crash_stop, cpu, regs);
> +	NMI_HANDLE(LOCAL_NMI_STOP, cpu_stop);

Please document the intended preemption design for all SSE events,
because it will be a nightmare if we forget some assumptions in the
coming years.  (That includes the relative priorities of RAS/PMU/...)

Thanks.


WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Yunhui Cui" <cuiyunhui@bytedance.com>, <conor@kernel.org>,
	<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <alex@ghiti.fr>,
	<luxu.kernel@bytedance.com>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <jassisinghbrar@gmail.com>,
	<conor.dooley@microchip.com>,
	<valentina.fernandezalanis@microchip.com>,
	<catalin.marinas@arm.com>, <will@kernel.org>, <maz@kernel.org>,
	<timothy.hayes@arm.com>, <lpieralisi@kernel.org>, <arnd@arndb.de>,
	<kees@kernel.org>, <tglx@linutronix.de>,
	<viresh.kumar@linaro.org>, <boqun.feng@gmail.com>,
	<linux-arm-kernel@lists.infradead.org>, <cleger@rivosinc.com>,
	<atishp@rivosinc.com>, <ajones@ventanamicro.com>
Cc: "linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v3 5/8] riscv: smp: use NMI for CPU stop
Date: Thu, 04 Dec 2025 13:07:20 +0900	[thread overview]
Message-ID: <DEP4X1DAIOU5.2WLIV4BMWLMRR@ventanamicro.com> (raw)
In-Reply-To: <20251127125305.89961-6-cuiyunhui@bytedance.com>

2025-11-27T20:53:02+08:00, Yunhui Cui <cuiyunhui@bytedance.com>:
> Use NMI instead of IPI for CPU stop if RISC-V SSE NMI is supported.
>
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> ---
> diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware/riscv/riscv_sse_nmi.c
> @@ -58,6 +58,7 @@ static int local_nmi_handler(u32 evt, void *arg, struct pt_regs *regs)
>  	type = atomic_read(this_cpu_ptr(&local_nmi));
>  
>  	NMI_HANDLE(LOCAL_NMI_CRASH, cpu_crash_stop, cpu, regs);
> +	NMI_HANDLE(LOCAL_NMI_STOP, cpu_stop);

Please document the intended preemption design for all SSE events,
because it will be a nightmare if we forget some assumptions in the
coming years.  (That includes the relative priorities of RAS/PMU/...)

Thanks.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2025-12-04  4:07 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-27 12:52 [PATCH v3 0/8] Add NMI Support to RISC-V via SSE Yunhui Cui
2025-11-27 12:52 ` Yunhui Cui
2025-11-27 12:52 ` [PATCH v3 1/8] drivers: firmware: riscv: add SSE NMI support Yunhui Cui
2025-11-27 12:52   ` Yunhui Cui
2025-11-27 12:52 ` [PATCH v3 2/8] riscv: smp: move ipi_cpu_crash_stop() declaration to smp.h Yunhui Cui
2025-11-27 12:52   ` Yunhui Cui
2025-11-27 12:53 ` [PATCH v3 3/8] smp: move num_other_online_cpus() into smp.h Yunhui Cui
2025-11-27 12:53   ` Yunhui Cui
2025-11-27 12:53 ` [PATCH v3 4/8] riscv: smp: use NMI for crash stop Yunhui Cui
2025-11-27 12:53   ` Yunhui Cui
2025-11-27 12:53 ` [PATCH v3 5/8] riscv: smp: use NMI for CPU stop Yunhui Cui
2025-11-27 12:53   ` Yunhui Cui
2025-12-04  4:07   ` Radim Krčmář [this message]
2025-12-04  4:07     ` Radim Krčmář
2025-12-04  5:28     ` [External] " yunhui cui
2025-12-04  5:28       ` yunhui cui
2025-12-04 13:16       ` Radim Krčmář
2025-12-04 13:16         ` Radim Krčmář
2025-12-08 11:40         ` yunhui cui
2025-12-08 11:40           ` yunhui cui
2025-12-10 14:22           ` Radim Krčmář
2025-12-10 14:22             ` Radim Krčmář
2025-12-12  3:09             ` yunhui cui
2025-12-12  3:09               ` yunhui cui
2025-11-27 12:53 ` [PATCH v3 6/8] riscv: smp: use NMI for backtrace Yunhui Cui
2025-11-27 12:53   ` Yunhui Cui
2025-11-27 12:53 ` [PATCH v3 7/8] riscv: smp: kgdb: use NMI for CPU roundup Yunhui Cui
2025-11-27 12:53   ` Yunhui Cui
2025-11-27 12:53 ` [PATCH v3 8/8] drivers: firmware: riscv: add unknown nmi support Yunhui Cui
2025-11-27 12:53   ` Yunhui Cui
2025-12-04  4:11   ` Radim Krčmář
2025-12-04  4:11     ` Radim Krčmář
2025-12-04  5:18     ` [External] " yunhui cui
2025-12-04  5:18       ` yunhui cui
2025-12-04 13:26       ` Radim Krčmář
2025-12-04 13:26         ` Radim Krčmář

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