From: "Diederik de Haas" <diederik@cknow-tech.com>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>,
"Andrew Lunn" <andrew@lunn.ch>
Cc: "Yao Zi" <me@ziyao.cc>, "Heiko Stuebner" <heiko@sntech.de>,
"Heiner Kallweit" <hkallweit1@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
"Eric Dumazet" <edumazet@google.com>,
"Jakub Kicinski" <kuba@kernel.org>,
"Paolo Abeni" <pabeni@redhat.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>, <netdev@vger.kernel.org>,
<linux-rockchip@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>
Subject: Re: Problematic understanding of phy-mode in Rockchip DWMAC driver
Date: Mon, 16 Feb 2026 18:21:13 +0100 [thread overview]
Message-ID: <DGGK56T574F0.TJSLQL9P1SM@cknow-tech.com> (raw)
In-Reply-To: <aZMxKdkl2Qa7e1WU@shell.armlinux.org.uk>
On Mon Feb 16, 2026 at 4:00 PM CET, Russell King (Oracle) wrote:
> On Mon, Feb 16, 2026 at 02:57:48AM +0100, Andrew Lunn wrote:
>> On Sat, Feb 14, 2026 at 07:02:08PM +0000, Russell King (Oracle) wrote:
>> > On Sat, Feb 14, 2026 at 05:50:15PM +0100, Andrew Lunn wrote:
>> > > Rockchip have recently started adding support for a new version, and
>> > > appear to of listened to what we have been saying. So it could be the
>> > > next generation of chips get this correct.
>> >
>> > Have you seen any proposed code from Rockchip for their new scheme?
>>
>> There was a patch, including a rather odd formulae to convert register
>> value to delay. I gave some feedback, but it has been silence
>> afterwards.
>
> Searching lore's netdev archive doesn't seem to bring anything up.
https://patch.msgid.link/b25d6eb2-e105-4060-86fa-c1a06396ca92@lunn.ch/
WARNING: multiple messages have this Message-ID (diff)
From: "Diederik de Haas" <diederik@cknow-tech.com>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>,
"Andrew Lunn" <andrew@lunn.ch>
Cc: "Yao Zi" <me@ziyao.cc>, "Heiko Stuebner" <heiko@sntech.de>,
"Heiner Kallweit" <hkallweit1@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
"Eric Dumazet" <edumazet@google.com>,
"Jakub Kicinski" <kuba@kernel.org>,
"Paolo Abeni" <pabeni@redhat.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>, <netdev@vger.kernel.org>,
<linux-rockchip@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>
Subject: Re: Problematic understanding of phy-mode in Rockchip DWMAC driver
Date: Mon, 16 Feb 2026 18:21:13 +0100 [thread overview]
Message-ID: <DGGK56T574F0.TJSLQL9P1SM@cknow-tech.com> (raw)
In-Reply-To: <aZMxKdkl2Qa7e1WU@shell.armlinux.org.uk>
On Mon Feb 16, 2026 at 4:00 PM CET, Russell King (Oracle) wrote:
> On Mon, Feb 16, 2026 at 02:57:48AM +0100, Andrew Lunn wrote:
>> On Sat, Feb 14, 2026 at 07:02:08PM +0000, Russell King (Oracle) wrote:
>> > On Sat, Feb 14, 2026 at 05:50:15PM +0100, Andrew Lunn wrote:
>> > > Rockchip have recently started adding support for a new version, and
>> > > appear to of listened to what we have been saying. So it could be the
>> > > next generation of chips get this correct.
>> >
>> > Have you seen any proposed code from Rockchip for their new scheme?
>>
>> There was a patch, including a rather odd formulae to convert register
>> value to delay. I gave some feedback, but it has been silence
>> afterwards.
>
> Searching lore's netdev archive doesn't seem to bring anything up.
https://patch.msgid.link/b25d6eb2-e105-4060-86fa-c1a06396ca92@lunn.ch/
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2026-02-16 17:21 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-13 18:26 Problematic understanding of phy-mode in Rockchip DWMAC driver Yao Zi
2026-02-13 18:26 ` Yao Zi
2026-02-13 18:47 ` Russell King (Oracle)
2026-02-13 18:47 ` Russell King (Oracle)
2026-02-14 16:50 ` Andrew Lunn
2026-02-14 16:50 ` Andrew Lunn
2026-02-14 19:02 ` Russell King (Oracle)
2026-02-14 19:02 ` Russell King (Oracle)
2026-02-16 1:57 ` Andrew Lunn
2026-02-16 1:57 ` Andrew Lunn
2026-02-16 15:00 ` Russell King (Oracle)
2026-02-16 15:00 ` Russell King (Oracle)
2026-02-16 17:21 ` Diederik de Haas [this message]
2026-02-16 17:21 ` Diederik de Haas
2026-02-24 2:08 ` Chaoyi Chen
2026-02-24 2:08 ` Chaoyi Chen
2026-02-16 4:44 ` Yao Zi
2026-02-16 4:44 ` Yao Zi
2026-02-16 15:48 ` Andrew Lunn
2026-02-16 15:48 ` Andrew Lunn
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