From: Alejandro Vallejo <alejandro.garciavallejo@amd.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
"Roger Pau Monné" <roger.pau@citrix.com>,
"Jason Andryuk" <jason.andryuk@amd.com>,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH v3 2/4] x86/hvm: Disable cross-vendor handling in #UD handler
Date: Wed, 11 Mar 2026 13:40:44 +0100 [thread overview]
Message-ID: <DGZYKZ2PYXJU.1F5BZQKPFZOTF@amd.com> (raw)
In-Reply-To: <66926b3b-82e0-4595-b54f-e73cef396ea2@suse.com>
On Wed Mar 11, 2026 at 12:06 PM CET, Jan Beulich wrote:
> On 11.03.2026 11:21, Alejandro Vallejo wrote:
>> On Wed Mar 11, 2026 at 10:30 AM CET, Jan Beulich wrote:
>>> On 11.03.2026 10:25, Alejandro Vallejo wrote:
>>>> On Wed Mar 11, 2026 at 9:35 AM CET, Jan Beulich wrote:
>>>>> On 13.02.2026 12:42, Alejandro Vallejo wrote:
>>>>>> - if ( opt_hvm_fep )
>>>>>> - {
>>>>>> - const struct segment_register *cs = &ctxt.seg_reg[x86_seg_cs];
>>>>>> - uint32_t walk = ((ctxt.seg_reg[x86_seg_ss].dpl == 3)
>>>>>> - ? PFEC_user_mode : 0) | PFEC_insn_fetch;
>>>>>
>>>>> Why is this initializer not retained?
>>>>
>>>> It is, it's just that the diff is terrible. An unfortunate side effect of the
>>>> removal of the braces. The scope collapsing forces it on top of the function,
>>>> before the emulation context is initialised.
>>>>
>>>> It's set up in steps. walk is unconditionally initialised as isnsn_fetch, and
>>>> later (after emulate_init_once()), OR'd with PFEC_user_mode for DPL == 3. See...
>>>>
>>>>>
>>>>>> - unsigned long addr;
>>>>>> - char sig[5]; /* ud2; .ascii "xen" */
>>>>>> -
>>>>>> - if ( hvm_virtual_to_linear_addr(x86_seg_cs, cs, regs->rip,
>>>>>> - sizeof(sig), hvm_access_insn_fetch,
>>>>>> - cs, &addr) &&
>>>>>> - (hvm_copy_from_guest_linear(sig, addr, sizeof(sig),
>>>>>> - walk, NULL) == HVMTRANS_okay) &&
>>>>>> - (memcmp(sig, "\xf\xb" "xen", sizeof(sig)) == 0) )
>>>>>> - {
>>>>>> - regs->rip += sizeof(sig);
>>>>>> - regs->eflags &= ~X86_EFLAGS_RF;
>>>>>> + hvm_emulate_init_once(&ctxt, NULL, regs);
>>>>>>
>>>>>> - /* Zero the upper 32 bits of %rip if not in 64bit mode. */
>>>>>> - if ( !(hvm_long_mode_active(cur) && cs->l) )
>>>>>> - regs->rip = (uint32_t)regs->rip;
>>>>>> + if ( ctxt.seg_reg[x86_seg_ss].dpl == 3 )
>>>>>> + walk |= PFEC_user_mode;
>>>>
>>>> ... here.
>>>
>>> But that's the point of my question: Why did you split it? All you mean to
>>> do is re-indentation.
>>
>> Because I need to declare "walk" ahead of the statements. Thus this...
>>
>> uint32_t walk = ((ctxt.seg_reg[x86_seg_ss].dpl == 3)
>> ? PFEC_user_mode : 0) | PFEC_insn_fetch;
>>
>> must (by necessity) have the declaration placed on top before the emulator
>> context initialisation. The options are...
>>
>> uint32_t walk;
>> [... lines ...]
>> walk = ((ctxt.seg_reg[x86_seg_ss].dpl == 3)
>> ? PFEC_user_mode : 0) | PFEC_insn_fetch;
>>
>> ... or...
>>
>> uint32_t walk = PFEC_insn_fetch;
>> [... lines ...]
>> if ( ctxt.seg_reg[x86_seg_ss].dpl == 3 )
>> walk |= PFEC_user_mode;
>>
>> Line count remains at 3 in both cases, but in the former case there's a
>> comparison, a ternary operator and an OR all adding cognitive load to the
>> same statement. In the latter case there's an assignment in the 1st statement,
>> an if+comparison in a separate line, and a separate OR in the final statement.
>> It's just simpler to meantally parse because the complexity is evenly
>> distributed.
>>
>> I can see how the current form was preferred to avoid a third line (and
>> then a forth due to the required newline, doubling the total). But with the
>> rearrangement that's no longer relevant.
>>
>> If you have a very strong preference for the prior form I could keep it, though
>> I do have a preference myself for the latter out of improved readability.
>
> Strong preference or not - readability is subjective. I prefer the present
> form, where the variable obtains it final value right away. More generally,
> with subjective aspects it may often be better to leave mechanical changes
> (here: re-indentation) as purely mechanical. Things are different with
> objective aspects, like style violations which of course can (and imo
> preferably should) be corrected on such occasions.
Ack
Cheers,
Alejandro
next prev parent reply other threads:[~2026-03-11 12:41 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-13 11:42 [PATCH v3 0/4] x86: Drop cross-vendor support Alejandro Vallejo
2026-02-13 11:42 ` [PATCH v3 1/4] x86: Reject CPU policies with vendors other than the host's Alejandro Vallejo
2026-03-11 8:26 ` Jan Beulich
2026-03-11 12:43 ` Alejandro Vallejo
2026-02-13 11:42 ` [PATCH v3 2/4] x86/hvm: Disable cross-vendor handling in #UD handler Alejandro Vallejo
2026-03-11 8:35 ` Jan Beulich
2026-03-11 9:25 ` Alejandro Vallejo
2026-03-11 9:30 ` Jan Beulich
2026-03-11 10:21 ` Alejandro Vallejo
2026-03-11 11:06 ` Jan Beulich
2026-03-11 12:40 ` Alejandro Vallejo [this message]
2026-02-13 11:42 ` [PATCH v3 3/4] x86/hvm: Remove cross-vendor checks from MSR handlers Alejandro Vallejo
2026-03-11 8:39 ` Jan Beulich
2026-02-13 11:42 ` [PATCH v3 4/4] x86/svm: Drop emulation of Intel's SYSENTER behaviour on AMD systems Alejandro Vallejo
2026-03-11 8:46 ` Jan Beulich
2026-03-11 9:27 ` Alejandro Vallejo
2026-03-11 8:54 ` [PATCH v3 0/4] x86: Drop cross-vendor support Jan Beulich
2026-03-11 9:46 ` Alejandro Vallejo
2026-03-11 10:11 ` Jan Beulich
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