All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Eliot Courtney" <ecourtney@nvidia.com>
To: "Alexandre Courbot" <acourbot@nvidia.com>,
	"Danilo Krummrich" <dakr@kernel.org>,
	"Alice Ryhl" <aliceryhl@google.com>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"Miguel Ojeda" <ojeda@kernel.org>,
	"Boqun Feng" <boqun@kernel.org>, "Gary Guo" <gary@garyguo.net>,
	"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
	"Benno Lossin" <lossin@kernel.org>,
	"Andreas Hindborg" <a.hindborg@kernel.org>,
	"Trevor Gross" <tmgross@umich.edu>
Cc: "John Hubbard" <jhubbard@nvidia.com>,
	"Alistair Popple" <apopple@nvidia.com>,
	"Joel Fernandes" <joelagnelf@nvidia.com>,
	"Timur Tabi" <ttabi@nvidia.com>, "Zhi Wang" <zhiw@nvidia.com>,
	"Eliot Courtney" <ecourtney@nvidia.com>,
	<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-doc@vger.kernel.org>,
	<rust-for-linux@vger.kernel.org>
Subject: Re: [PATCH 4/8] gpu: nova-core: convert GC6 registers to kernel register macro
Date: Thu, 19 Mar 2026 11:07:03 +0900	[thread overview]
Message-ID: <DH6E45B9EBWR.1MAR230QYC2HG@nvidia.com> (raw)
In-Reply-To: <20260318-b4-nova-register-v1-4-22a358aa4c63@nvidia.com>

On Wed Mar 18, 2026 at 5:06 PM JST, Alexandre Courbot wrote:
> Convert all GC6 registers to use the kernel's register macro and update
> the code accordingly.
>
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
>  impl NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT {
>      /// Returns `true` if GFW boot is completed.
> @@ -252,16 +253,17 @@ pub(crate) fn completed(self) -> bool {
>      }
>  }
>  
> -register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 @ 0x001183a4 {
> -    31:0    value as u32;
> -});
> -
> -register!(
> -    NV_USABLE_FB_SIZE_IN_MB => NV_PGC6_AON_SECURE_SCRATCH_GROUP_42,
> -    "Scratch group 42 register used as framebuffer size" {
> -        31:0    value as u32, "Usable framebuffer size, in megabytes";
> +nv_reg! {
> +    NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 @ 0x001183a4 {
> +        31:0    value;
>      }
> -);
> +
> +    /// Scratch group 42 register used as framebuffer size.
> +    NV_USABLE_FB_SIZE_IN_MB => NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 {
> +        /// Usable framebuffer size, in megabytes.
> +        31:0    value;
> +    }
> +}

This is not an issue with your series, but why do we have
`NV_PGC6_AON_SECURE_SCRATCH_GROUP_42` which is aliased to
`NV_USABLE_FB_SIZE_IN_MB` and not used for anything else?

Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>


WARNING: multiple messages have this Message-ID (diff)
From: "Eliot Courtney" <ecourtney@nvidia.com>
To: "Alexandre Courbot" <acourbot@nvidia.com>,
	"Danilo Krummrich" <dakr@kernel.org>,
	"Alice Ryhl" <aliceryhl@google.com>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"Miguel Ojeda" <ojeda@kernel.org>,
	"Boqun Feng" <boqun@kernel.org>, "Gary Guo" <gary@garyguo.net>,
	"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
	"Benno Lossin" <lossin@kernel.org>,
	"Andreas Hindborg" <a.hindborg@kernel.org>,
	"Trevor Gross" <tmgross@umich.edu>
Cc: "John Hubbard" <jhubbard@nvidia.com>,
	"Alistair Popple" <apopple@nvidia.com>,
	"Joel Fernandes" <joelagnelf@nvidia.com>,
	"Timur Tabi" <ttabi@nvidia.com>, "Zhi Wang" <zhiw@nvidia.com>,
	"Eliot Courtney" <ecourtney@nvidia.com>,
	<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-doc@vger.kernel.org>,
	<rust-for-linux@vger.kernel.org>
Subject: Re: [PATCH 4/8] gpu: nova-core: convert GC6 registers to kernel register macro
Date: Thu, 19 Mar 2026 11:07:03 +0900	[thread overview]
Message-ID: <DH6E45B9EBWR.1MAR230QYC2HG@nvidia.com> (raw)
In-Reply-To: <20260318-b4-nova-register-v1-4-22a358aa4c63@nvidia.com>

On Wed Mar 18, 2026 at 5:06 PM JST, Alexandre Courbot wrote:
> Convert all GC6 registers to use the kernel's register macro and update
> the code accordingly.
>
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
>  impl NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT {
>      /// Returns `true` if GFW boot is completed.
> @@ -252,16 +253,17 @@ pub(crate) fn completed(self) -> bool {
>      }
>  }
>  
> -register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 @ 0x001183a4 {
> -    31:0    value as u32;
> -});
> -
> -register!(
> -    NV_USABLE_FB_SIZE_IN_MB => NV_PGC6_AON_SECURE_SCRATCH_GROUP_42,
> -    "Scratch group 42 register used as framebuffer size" {
> -        31:0    value as u32, "Usable framebuffer size, in megabytes";
> +nv_reg! {
> +    NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 @ 0x001183a4 {
> +        31:0    value;
>      }
> -);
> +
> +    /// Scratch group 42 register used as framebuffer size.
> +    NV_USABLE_FB_SIZE_IN_MB => NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 {
> +        /// Usable framebuffer size, in megabytes.
> +        31:0    value;
> +    }
> +}

This is not an issue with your series, but why do we have
`NV_PGC6_AON_SECURE_SCRATCH_GROUP_42` which is aliased to
`NV_USABLE_FB_SIZE_IN_MB` and not used for anything else?

Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2026-03-19  2:07 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-18  8:05 [PATCH 0/8] gpu: nova-core: convert registers to use the kernel register macro Alexandre Courbot
2026-03-18  8:05 ` Alexandre Courbot
2026-03-18  8:05 ` [PATCH 1/8] gpu: nova-core: convert PMC registers to " Alexandre Courbot
2026-03-18  8:05   ` Alexandre Courbot
2026-03-18 13:28   ` Gary Guo
2026-03-18 13:28     ` Gary Guo
2026-03-19 14:39     ` Alexandre Courbot
2026-03-19 14:39       ` Alexandre Courbot
2026-03-19  1:42   ` Eliot Courtney
2026-03-19  1:42     ` Eliot Courtney
2026-03-19  2:07     ` Alexandre Courbot
2026-03-19  2:07       ` Alexandre Courbot
2026-03-19  2:16       ` Eliot Courtney
2026-03-19  2:16         ` Eliot Courtney
2026-03-19 14:18         ` Alexandre Courbot
2026-03-19 14:18           ` Alexandre Courbot
2026-03-18  8:06 ` [PATCH 2/8] gpu: nova-core: convert PBUS " Alexandre Courbot
2026-03-18  8:06   ` Alexandre Courbot
2026-03-19  1:43   ` Eliot Courtney
2026-03-19  1:43     ` Eliot Courtney
2026-03-18  8:06 ` [PATCH 3/8] gpu: nova-core: convert PFB " Alexandre Courbot
2026-03-18  8:06   ` Alexandre Courbot
2026-03-19  1:51   ` Eliot Courtney
2026-03-19  1:51     ` Eliot Courtney
2026-03-18  8:06 ` [PATCH 4/8] gpu: nova-core: convert GC6 " Alexandre Courbot
2026-03-18  8:06   ` Alexandre Courbot
2026-03-19  2:07   ` Eliot Courtney [this message]
2026-03-19  2:07     ` Eliot Courtney
2026-03-19 14:19     ` Alexandre Courbot
2026-03-19 14:19       ` Alexandre Courbot
2026-03-18  8:06 ` [PATCH 5/8] gpu: nova-core: convert FUSE " Alexandre Courbot
2026-03-18  8:06   ` Alexandre Courbot
2026-03-19  2:17   ` Eliot Courtney
2026-03-19  2:17     ` Eliot Courtney
2026-03-19 14:24     ` Alexandre Courbot
2026-03-19 14:24       ` Alexandre Courbot
2026-03-18  8:06 ` [PATCH 6/8] gpu: nova-core: convert PDISP " Alexandre Courbot
2026-03-18  8:06   ` Alexandre Courbot
2026-03-19  2:18   ` Eliot Courtney
2026-03-19  2:18     ` Eliot Courtney
2026-03-18  8:06 ` [PATCH 7/8] gpu: nova-core: convert falcon " Alexandre Courbot
2026-03-18  8:06   ` Alexandre Courbot
2026-03-19  5:35   ` Eliot Courtney
2026-03-19  5:35     ` Eliot Courtney
2026-03-19 14:34     ` Alexandre Courbot
2026-03-19 14:34       ` Alexandre Courbot
2026-03-18  8:06 ` [PATCH 8/8] Documentation: nova: remove register abstraction task Alexandre Courbot
2026-03-18  8:06   ` Alexandre Courbot
2026-03-19  2:20   ` Eliot Courtney
2026-03-19  2:20     ` Eliot Courtney

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=DH6E45B9EBWR.1MAR230QYC2HG@nvidia.com \
    --to=ecourtney@nvidia.com \
    --cc=a.hindborg@kernel.org \
    --cc=acourbot@nvidia.com \
    --cc=airlied@gmail.com \
    --cc=aliceryhl@google.com \
    --cc=apopple@nvidia.com \
    --cc=bjorn3_gh@protonmail.com \
    --cc=boqun@kernel.org \
    --cc=dakr@kernel.org \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=gary@garyguo.net \
    --cc=jhubbard@nvidia.com \
    --cc=joelagnelf@nvidia.com \
    --cc=linux-doc@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=lossin@kernel.org \
    --cc=maarten.lankhorst@linux.intel.com \
    --cc=mripard@kernel.org \
    --cc=ojeda@kernel.org \
    --cc=rust-for-linux@vger.kernel.org \
    --cc=simona@ffwll.ch \
    --cc=tmgross@umich.edu \
    --cc=ttabi@nvidia.com \
    --cc=tzimmermann@suse.de \
    --cc=zhiw@nvidia.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.