[PATCH 0/6] drm/nouveau: fix GA100 issues

[PATCH 0/6] drm/nouveau: fix GA100 issues

[Timur Tabi]

The previous commit that claimed to add GA100 support, 20e0c197802c
("drm/nouveau/gsp: add support for GA100"), actually had quite a
few problems.  It falsely claimed that there was no VBIOS.  GA100
does have a VBIOS, but it has no display engine, so it cannot use
the PRAMIN method the read VBIOS, so it has to fall back to PROM.
For whatever reason, the VBIOS on GA100 has an "Init-from-ROM"
(IFR) header where the PCI Expansion ROM would normally be found.
So to find that ROM, Nouveau needs to parse the IFR header.

The previous commit also claimed that there is no graphics (GR)
engine.  That is also false.

This patch set adds the IFR header parsing and a few other missing
pieces to allow GA100 to actually boot and shut down GSP-RM
properly.

Timur Tabi (6):
  drm/nouveau: check for GA100 specifically when calculating FRTS size
  drm/nouveau/bios: specify correct display fuse register for Ampere and
    Ada
  drm/nouveau/bios: skip the IFR header if present
  drm/nouveau/gsp: require GSP-RM for GA100 support
  drm/nouveau: parse the VBIOS on GA100
  drm/nouveau/gsp: enable FWSEC-SB on GA100

 .../gpu/drm/nouveau/nvkm/engine/device/base.c |   1 +
 .../nouveau/nvkm/subdev/bios/shadowramin.c    |   3 +-
 .../drm/nouveau/nvkm/subdev/bios/shadowrom.c  | 110 ++++++++++++++++--
 .../gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c   |   4 +-
 .../gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c   |  10 +-
 5 files changed, 112 insertions(+), 16 deletions(-)


base-commit: dc2d30e7db8321a6696d266838f7af7e9d1c7155
-- 
2.53.0

[PATCH 1/6] drm/nouveau: check for GA100 specifically when calculating FRTS size

[Timur Tabi]

When booting with GSP-RM, the FRTS data region normally needs to be
allocated.  However, on GA100, this region is not used and so its
size needs to be set to zero.  The current method of looking at
device->bios is not valid, as GA100 actually does have a VBIOS.

The truth is that GA100 is just special, and the simplest way to
determine the proper FRTS data region size is to check for this
GPU specifically.

Fixes: 20e0c197802c ("drm/nouveau/gsp: add support for GA100")
Signed-off-by: Timur Tabi <ttabi@nvidia.com>
---
 drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c
index dd82c76b8b9a..815be8d0ecf2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c
@@ -319,12 +319,12 @@ tu102_gsp_oneinit(struct nvkm_gsp *gsp)
 		return ret;
 
 	/*
-	 * Calculate FB layout. FRTS is a memory region created by the FWSEC-FRTS firmware.
-	 * FWSEC comes from VBIOS.  So on systems with no VBIOS (e.g. GA100), the FRTS does
-	 * not exist.  Therefore, use the existence of VBIOS to determine whether to reserve
-	 * an FRTS region.
+	 * Calculate FB layout. FRTS is a memory region created by running the FWSEC-FRTS
+	 * command, which writes power management data into WPR2. On GA100, the booter
+	 * firmware handles WPR2 setup directly and FRTS data is not needed, so no FRTS
+	 * region is reserved.
 	 */
-	gsp->fb.wpr2.frts.size = device->bios ? 0x100000 : 0;
+	gsp->fb.wpr2.frts.size = device->chipset == 0x170 ? 0 : 0x100000;
 	gsp->fb.wpr2.frts.addr = ALIGN_DOWN(gsp->fb.bios.addr, 0x20000) - gsp->fb.wpr2.frts.size;
 
 	gsp->fb.wpr2.boot.size = gsp->boot.fw.size;
-- 
2.53.0

[PATCH 2/6] drm/nouveau/bios: specify correct display fuse register for Ampere and Ada

[Timur Tabi]

The NV_FUSE_STATUS_OPT_DISPLAY register is used to determine whether
the GPU has display hardware.  The current code that normally reads
this register is instead hard-coded to check for GA100 vs later GPUs.
Since this function is called only on pre-Hopper GPUs, and this
if-statement applies only to GA100 and later, the check works
because GA100 is the only non-display Ampere and Ada GPU.

However, there actually is a register that can be read, so we should
use it.

Fixes: a34632482f1e ("drm/nouveau/bios/ga10[024]: initial support")
Signed-off-by: Timur Tabi <ttabi@nvidia.com>
---
 drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
index d5411d176e3a..0d9e6cdd6119 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c
@@ -65,13 +65,14 @@ pramin_init(struct nvkm_bios *bios, const char *name)
 
 	/* we can't get the bios image pointer without PDISP */
 	if (device->card_type >= GA100)
-		addr = device->chipset == 0x170; /*XXX: find the fuse reg for this */
+		addr = nvkm_rd32(device, 0x820c04);
 	else
 	if (device->card_type >= GM100)
 		addr = nvkm_rd32(device, 0x021c04);
 	else
 	if (device->card_type >= NV_C0)
 		addr = nvkm_rd32(device, 0x022500);
+
 	if (addr & 0x00000001) {
 		nvkm_debug(subdev, "... display disabled\n");
 		return ERR_PTR(-ENODEV);
-- 
2.53.0

[PATCH 3/6] drm/nouveau/bios: skip the IFR header if present

[Timur Tabi]

The GPU's ROM may begin with an Init-from-ROM (IFR) header that precedes
the PCI Expansion ROM images (VBIOS).  When present, the PROM shadow
method must parse this header to determine the offset where the PCI ROM
images actually begin, and adjust all subsequent reads accordingly.

On most GPUs this is not needed because either the PRAMIN shadow method
(which reads from VRAM via the display engine) succeeds first, or the IFR
microcode has already applied the ROM offset so that PROM reads
transparently skip the header.  However, on GA100 neither of these
applies: GA100 has no display engine (so PRAMIN is unavailable), and the
IFR offset is not applied to PROM reads on this GPU.

Signed-off-by: Timur Tabi <ttabi@nvidia.com>
---
 .../drm/nouveau/nvkm/subdev/bios/shadowrom.c  | 110 ++++++++++++++++--
 1 file changed, 101 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c
index 39144ceb117b..9e171b1bad73 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c
@@ -24,34 +24,126 @@
 
 #include <subdev/pci.h>
 
+#define NV_PBUS_IFR_FMT_FIXED0_SIGNATURE_VALUE 0x4947564E	/* "NVGI" */
+#define NV_ROM_DIRECTORY_IDENTIFIER 0x44524652			/* "RFRD" */
+
+struct priv {
+	struct nvkm_device *device;
+	u32 pci_rom_offset;
+};
+
 static u32
 nvbios_prom_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios)
 {
-	struct nvkm_device *device = data;
+	struct priv *priv = data;
+	struct nvkm_device *device = priv->device;
 	u32 i;
-	if (offset + length <= 0x00100000) {
-		for (i = offset; i < offset + length; i += 4)
-			*(u32 *)&bios->data[i] = nvkm_rd32(device, 0x300000 + i);
-		return length;
-	}
-	return 0;
+
+	/* Make sure we don't try to read past the end of data[] */
+	if (offset + length > bios->size)
+		return 0;
+
+	/* Make sure the read falls within the 1MB PROM window */
+	if (offset + priv->pci_rom_offset + length > 0x00100000)
+		return 0;
+
+	for (i = offset; i < offset + length; i += 4)
+		*(u32 *)&bios->data[i] = nvkm_rd32(device, 0x300000 + priv->pci_rom_offset + i);
+	return length;
 }
 
 static void
 nvbios_prom_fini(void *data)
 {
-	struct nvkm_device *device = data;
+	struct priv *priv = data;
+	struct nvkm_device *device = priv->device;
+
 	nvkm_pci_rom_shadow(device->pci, true);
+
+	kfree(data);
 }
 
 static void *
 nvbios_prom_init(struct nvkm_bios *bios, const char *name)
 {
 	struct nvkm_device *device = bios->subdev.device;
+	struct priv *priv;
+	u32 fixed0;
+
+	/* There is no PROM on NV4x iGPUs */
 	if (device->card_type == NV_40 && device->chipset >= 0x4c)
 		return ERR_PTR(-ENODEV);
+
+	priv = kzalloc_obj(*priv);
+	if (!priv)
+		return ERR_PTR(-ENOMEM);
+
+	/* Disable the PCI ROM shadow so that we can read PROM. */
 	nvkm_pci_rom_shadow(device->pci, false);
-	return device;
+
+	/*
+	 * Check for an IFR header. If present, parse it to find the actual PCI ROM header.
+	 *
+	 * The IFR header is documented in Documentation/gpu/nova/core/vbios.rst
+	 */
+	fixed0 = nvkm_rd32(device, 0x300000);
+	if (fixed0 == NV_PBUS_IFR_FMT_FIXED0_SIGNATURE_VALUE) {
+		u32 fixed1 = nvkm_rd32(device, 0x300004);
+		u8 version = (fixed1 >> 8) & 0xff;
+		u32 fixed2, data_size, offset, signature;
+
+		switch (version) {
+		case 1:
+		case 2:
+			data_size = (fixed1 >> 16) & 0x7fff;
+			priv->pci_rom_offset = nvkm_rd32(device, 0x300000 + data_size + 4);
+			break;
+		case 3:
+			fixed2 = nvkm_rd32(device, 0x300008);
+			data_size = fixed2 & 0x000fffff;
+
+			/* ROM directory offset */
+			offset = nvkm_rd32(device, 0x300000 + data_size) + 4096;
+
+			signature = nvkm_rd32(device, 0x300000 + offset);
+			if (signature != NV_ROM_DIRECTORY_IDENTIFIER) {
+				nvkm_error(&bios->subdev, "could not find IFR ROM directory\n");
+				goto fail;
+			}
+
+			priv->pci_rom_offset = nvkm_rd32(device, 0x300000 + offset + 8);
+
+			break;
+		default:
+			nvkm_error(&bios->subdev, "unsupported IFR header version %u\n",
+				   version);
+			goto fail;
+		}
+
+		/* Double-check that the offset is valid */
+		if (priv->pci_rom_offset >= 0x00100000) {
+			nvkm_error(&bios->subdev,
+				   "PCI ROM offset of 0x%x is too large\n", priv->pci_rom_offset);
+			goto fail;
+		}
+
+		/* If there is an IFR header, there must also be a PCI ROM header. */
+		signature = nvkm_rd32(device, 0x300000 + priv->pci_rom_offset) & 0xffff;
+		if (signature != 0xaa55) {
+			nvkm_error(&bios->subdev,
+				   "could not find PCI ROM signature at offset 0x%x\n",
+				   priv->pci_rom_offset);
+			goto fail;
+		}
+	}
+
+	priv->device = device;
+	return priv;
+
+fail:
+	nvkm_pci_rom_shadow(device->pci, true);
+	kfree(priv);
+	return ERR_PTR(-ENODEV);
 }
 
 const struct nvbios_source
-- 
2.53.0

[PATCH 4/6] drm/nouveau/gsp: require GSP-RM for GA100 support

[Timur Tabi]

Nouveau supports Turing and Ampere GPUs with or without GSP-RM.
Support without GSP-RM is mostly academic, since GSP-RM is
needed to run the GPU at full clocks.  It is also the default
mode for these GPUs.

GA100 is a special case, however.  The current code has some support
for running GA100 without GSP-RM, but several features are missing.
More importantly, some required firmware images like ucode_ahesasc.bin
are not available and would need to be provided by Nvidia.

To prevent Nouveau from even trying to boot on GA100 without GSP-RM,
remove the non-GSP fallback option in the ga100_gsps[] array.

Signed-off-by: Timur Tabi <ttabi@nvidia.com>
---
 drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c
index fdd820eeef81..cc57de99e59e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c
@@ -59,7 +59,6 @@ static struct nvkm_gsp_fwif
 ga100_gsps[] = {
 	{  1, tu102_gsp_load, &ga100_gsp, &r570_rm_tu102, "570.144" },
 	{  0, tu102_gsp_load, &ga100_gsp, &r535_rm_tu102, "535.113.01" },
-	{ -1, gv100_gsp_nofw, &gv100_gsp },
 	{}
 };
 
-- 
2.53.0

[PATCH 5/6] drm/nouveau: parse the VBIOS on GA100

[Timur Tabi]

Now that the IFR header is properly parsed on systems that expose it,
re-enable VBIOS parsing on GA100.

The previous commit that disabled it [1] incorrectly stated that there
is no VBIOS on GA100.

[1] Commit 20e0c197802c ("drm/nouveau/gsp: add support for GA100")

Signed-off-by: Timur Tabi <ttabi@nvidia.com>
---
 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 72848ed80df7..9c0b58f57922 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -2513,6 +2513,7 @@ static const struct nvkm_device_chip
 nv170_chipset = {
 	.name = "GA100",
 	.bar      = { 0x00000001, tu102_bar_new },
+	.bios	  = { 0x00000001, nvkm_bios_new },
 	.devinit  = { 0x00000001, ga100_devinit_new },
 	.fault    = { 0x00000001, tu102_fault_new },
 	.fb       = { 0x00000001, ga100_fb_new },
-- 
2.53.0

[PATCH 6/6] drm/nouveau/gsp: enable FWSEC-SB on GA100

[Timur Tabi]

Now that the VBIOS is correctly parsed on GA100 (via IFR header
support in the PROM shadow method), re-enable the FWSEC function
pointers that were removed in commit 20e0c197802c ("drm/nouveau/gsp:
add support for GA100").

FWSEC-SB is constructed during GSP-RM boot by parsing the FWSEC ucode
from the VBIOS, and is executed during teardown to restore PreOsApps.
Without these pointers, driver unload or suspend triggers a NULL
pointer dereference when tu102_gsp_fini() attempts to run FWSEC-SB
with an uninitialized firmware struct.

This requires the acr/bl.bin firmware (the generic falcon bootloader)
to be available for GA100, which is the same binary used by Turing.
A symlink for this file was recently added to the linux-firmware
repository, so an updated linux-firmware package is required.

Signed-off-by: Timur Tabi <ttabi@nvidia.com>
---
 drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c
index cc57de99e59e..d953f913f949 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c
@@ -41,10 +41,13 @@ ga100_gsp_flcn = {
 static const struct nvkm_gsp_func
 ga100_gsp = {
 	.flcn = &ga100_gsp_flcn,
+	.fwsec = &tu102_gsp_fwsec,
 
 	.sig_section = ".fwsignature_ga100",
 
 	.booter.ctor = tu102_gsp_booter_ctor,
+	.fwsec_sb.ctor = tu102_gsp_fwsec_sb_ctor,
+	.fwsec_sb.dtor = tu102_gsp_fwsec_sb_dtor,
 
 	.dtor = r535_gsp_dtor,
 	.oneinit = tu102_gsp_oneinit,
-- 
2.53.0

Re: [PATCH 0/6] drm/nouveau: fix GA100 issues

[lyude]

Reviewed-by: Lyude Paul <lyude@redhat.com>

Thank you!

On Tue, 2026-04-07 at 14:21 -0500, Timur Tabi wrote:
> The previous commit that claimed to add GA100 support, 20e0c197802c
> ("drm/nouveau/gsp: add support for GA100"), actually had quite a
> few problems.  It falsely claimed that there was no VBIOS.  GA100
> does have a VBIOS, but it has no display engine, so it cannot use
> the PRAMIN method the read VBIOS, so it has to fall back to PROM.
> For whatever reason, the VBIOS on GA100 has an "Init-from-ROM"
> (IFR) header where the PCI Expansion ROM would normally be found.
> So to find that ROM, Nouveau needs to parse the IFR header.
> 
> The previous commit also claimed that there is no graphics (GR)
> engine.  That is also false.
> 
> This patch set adds the IFR header parsing and a few other missing
> pieces to allow GA100 to actually boot and shut down GSP-RM
> properly.
> 
> Timur Tabi (6):
>   drm/nouveau: check for GA100 specifically when calculating FRTS
> size
>   drm/nouveau/bios: specify correct display fuse register for Ampere
> and
>     Ada
>   drm/nouveau/bios: skip the IFR header if present
>   drm/nouveau/gsp: require GSP-RM for GA100 support
>   drm/nouveau: parse the VBIOS on GA100
>   drm/nouveau/gsp: enable FWSEC-SB on GA100
> 
>  .../gpu/drm/nouveau/nvkm/engine/device/base.c |   1 +
>  .../nouveau/nvkm/subdev/bios/shadowramin.c    |   3 +-
>  .../drm/nouveau/nvkm/subdev/bios/shadowrom.c  | 110
> ++++++++++++++++--
>  .../gpu/drm/nouveau/nvkm/subdev/gsp/ga100.c   |   4 +-
>  .../gpu/drm/nouveau/nvkm/subdev/gsp/tu102.c   |  10 +-
>  5 files changed, 112 insertions(+), 16 deletions(-)
> 
> 
> base-commit: dc2d30e7db8321a6696d266838f7af7e9d1c7155

Re: [PATCH 0/6] drm/nouveau: fix GA100 issues

[Danilo Krummrich]

On Tue Apr 7, 2026 at 9:21 PM CEST, Timur Tabi wrote:
> Timur Tabi (6):
>   drm/nouveau: check for GA100 specifically when calculating FRTS size
>   drm/nouveau/bios: specify correct display fuse register for Ampere and
>     Ada
>   drm/nouveau/bios: skip the IFR header if present
>   drm/nouveau/gsp: require GSP-RM for GA100 support
>   drm/nouveau: parse the VBIOS on GA100
>   drm/nouveau/gsp: enable FWSEC-SB on GA100

Hm...this is five times the size of the patch adding GA100 support in the first
place, i.e. it doesn't feel like -fixes material, but more like deferred -next
material.

Thus, can you please send a revert for commit 20e0c197802c ("drm/nouveau/gsp:
add support for GA100") and make this a new clean series adding GA100 support
for v7.2?

Thanks,
Danilo

Re: [PATCH 0/6] drm/nouveau: fix GA100 issues

[Timur Tabi]

On Tue, 2026-04-28 at 17:07 +0200, Danilo Krummrich wrote:
> On Tue Apr 7, 2026 at 9:21 PM CEST, Timur Tabi wrote:
> > Timur Tabi (6):
> >   drm/nouveau: check for GA100 specifically when calculating FRTS size
> >   drm/nouveau/bios: specify correct display fuse register for Ampere and
> >     Ada
> >   drm/nouveau/bios: skip the IFR header if present
> >   drm/nouveau/gsp: require GSP-RM for GA100 support
> >   drm/nouveau: parse the VBIOS on GA100
> >   drm/nouveau/gsp: enable FWSEC-SB on GA100
> 
> Hm...this is five times the size of the patch adding GA100 support in the first
> place, i.e. it doesn't feel like -fixes material, but more like deferred -next
> material.
> 
> Thus, can you please send a revert for commit 20e0c197802c ("drm/nouveau/gsp:
> add support for GA100") and make this a new clean series adding GA100 support
> for v7.2?

Sure.