* [PATCH v3 00/23] mtd: spi-nor: QE handling cleanup + fixup reworks + Winbond RV chips addition
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
Hello,
Following my "software protection" enhancement series, there were
several comments about the need to simplify and reorganize the handling
of the QE bits, which is strongly impacted by the various read/write
status register capabilities.
The third patch is all about this. It is a massive cleanup, everything
is explained inside, the how and the why. This is a commit that must be
tested, so if you have a SPI NOR chip with one of the not yet tested
SFDP QER configuration, please consider applying that patch (just patch
1 is enough) and boot. If your chip is recognized, it's probably all
good.
Since it was pointed that the legacy .name fields were part of the ABI,
my previous deletion was no longer possible, so I now propose a
(writable) indirection for accessing this field, which will allow
developers to hide that name using fixups.
Talking about fixups, I continued with another rework that has been
asked for: changing the way fixups are listed. I am now creating a table
of fixups, which can be matched by ID and/or with a match function, as
per Michael Walle's suggestion. This cleans quite a bit the fixup lists
in the winbond driver, especially because of the new name hiding fixup,
so thanks for the suggestion!
Then I add support for JESD216 revision F and its new QER field.
Finally, I rework a bit the fixups in the Winbond driver, which allows
a clean addition of the new Winbond RV chips.
All chips I will ever be able to test are now listed and proof of
testing is below the commit message.
Thanks,
Miquèl
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
Changes in v3:
- Added support for two new chips that I could test (W25Q51RV-M and
W25Q02RV-Q/N). Edited the last commit which is now only adding the
256M-bit densities without the possibility to test, since I will not
receive any of these any time soon.
- Reworked completely the way fixups are now being applied.
- Re-instated the legacy .names, created a way to overwrite them and
enabled a fixup for that.
- Link to v2: https://lore.kernel.org/r/20260807-winbond-v7-1-spi-nor-rv-addition-v2-0-7797642dfc40@bootlin.com
Changes in v2:
- Added support for more chips that I received and could test. The main
logic in the first patches is completely untouched.
- Fixed the name of a parameter (s/sr2/srs/) in the low level read status
registers helper.
- Decided that there was no specific handling of the WP pin being
strapped wrt the read check over the SR content. This would be new,
and I don't think it is wide to handle it in the verify helper, but
instead this should be let to the caller to decide whether it needs
to hard fail or just degrade into single mode (typically if the QE
bit has not been written). But this would require an extra DT
property indicating the WP strap state which cannot be read back by
software.
- Created a structure to store the flash specific opcodes.
- Proposed a rename of BFPT_DWORD15_QER_SR2_BIT1_BUGGY in favour of
the _NO_1B_WR suffix.
- After checking, decided that the .name field is legacy and not part
of any stable API, thus it can be removed. So added back a commit
for that, removing the names for the whole JV family.
- Exposed all opcodes through debugfs, including the QE bit position.
- OTP and SWP writes are now read back like before.
- 2 known deviations are now explicitely stated in the commit log.
- I changed a little bit the QER field parsing in the sfdp.c driver, to
limit deviations, as much as my understanding would allow me.
- Link to v1: https://lore.kernel.org/r/20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com
---
Miquel Raynal (23):
mtd: spi-nor: Rename BFPT_DWORD15_QER_SR2_BIT1_BUGGY
mtd: spi-nor: Create a structure containing the flash opcodes
mtd: spi-nor: Refactor Read Status/Write Status support
mtd: spi-nor: Add support for the new JESD216 rev F QER field
mtd: spi-nor: Create the concept of fixup table with match function
mtd: spi-nor: Create an indirection on the part name
mtd: spi-nor: Move the SFDP header structure to a C header
mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-Q/N parts
mtd: spi-nor: winbond: Add support for W25Q32RV-Q/N
mtd: spi-nor: winbond: Add support for W25Q64RV-Q/N
mtd: spi-nor: winbond: Add support for W25Q12RV-Q/N
mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N
mtd: spi-nor: winbond: Add support for W25Q01RV-Q/N
mtd: spi-nor: winbond: Add support for W25Q02RV-Q/N
mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-M parts
mtd: spi-nor: winbond: Add support for W25Q32RV-M
mtd: spi-nor: winbond: Add support for W25Q64RV-M
mtd: spi-nor: winbond: Add support for W25Q12RV-M
mtd: spi-nor: winbond: Add support for W25Q51RV-M
mtd: spi-nor: winbond: Add support for W25Q01RV-M
mtd: spi-nor: winbond: Add support for W25Q02RV-M
mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N/M
mtd: spi-nor: debugfs: Expose SR opcodes and QE mask
Documentation/driver-api/mtd/spi-nor.rst | 2 +-
drivers/mtd/spi-nor/atmel.c | 75 ++-
drivers/mtd/spi-nor/core.c | 875 ++++++++++++-------------------
drivers/mtd/spi-nor/core.h | 94 ++--
drivers/mtd/spi-nor/debugfs.c | 22 +-
drivers/mtd/spi-nor/everspin.c | 7 +-
drivers/mtd/spi-nor/gigadevice.c | 13 +-
drivers/mtd/spi-nor/issi.c | 25 +-
drivers/mtd/spi-nor/macronix.c | 35 +-
drivers/mtd/spi-nor/micron-st.c | 51 +-
drivers/mtd/spi-nor/otp.c | 16 +-
drivers/mtd/spi-nor/sfdp.c | 114 ++--
drivers/mtd/spi-nor/sfdp.h | 21 +-
drivers/mtd/spi-nor/spansion.c | 61 ++-
drivers/mtd/spi-nor/sst.c | 16 +-
drivers/mtd/spi-nor/swp.c | 58 +-
drivers/mtd/spi-nor/sysfs.c | 4 +-
drivers/mtd/spi-nor/winbond.c | 106 +++-
include/linux/mtd/spi-nor.h | 6 +-
19 files changed, 802 insertions(+), 799 deletions(-)
---
base-commit: 728e68a889bcf257b1e67298b12c360e5c3a13e0
change-id: 20260529-winbond-v7-1-spi-nor-rv-addition-cea2f1f158be
prerequisite-message-id: <20260805-winbond-v7-1-spi-nor-jv-cleanup-v5-0-87238e577794@bootlin.com>
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prerequisite-patch-id: 07059d14bb516ba19fc0a678a96b3224f91caf24
prerequisite-patch-id: 1e221a9bbfb1fc53982beaf75bccf48baaba491f
prerequisite-patch-id: 20ce5105adc4c7f8ebc6c779b107fd54def4f1f8
prerequisite-patch-id: cd8fddc6d97316419b52997207a198037b41b32d
prerequisite-patch-id: 759f747940c26df6ec85fecb4779fd54e0ea3735
prerequisite-patch-id: eaeebc9df5221bab68a6cabc64a97e9c2608899b
Best regards,
--
Miquel Raynal <miquel.raynal@bootlin.com>
^ permalink raw reply [flat|nested] 92+ messages in thread
* [PATCH v3 00/23] mtd: spi-nor: QE handling cleanup + fixup reworks + Winbond RV chips addition
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
Hello,
Following my "software protection" enhancement series, there were
several comments about the need to simplify and reorganize the handling
of the QE bits, which is strongly impacted by the various read/write
status register capabilities.
The third patch is all about this. It is a massive cleanup, everything
is explained inside, the how and the why. This is a commit that must be
tested, so if you have a SPI NOR chip with one of the not yet tested
SFDP QER configuration, please consider applying that patch (just patch
1 is enough) and boot. If your chip is recognized, it's probably all
good.
Since it was pointed that the legacy .name fields were part of the ABI,
my previous deletion was no longer possible, so I now propose a
(writable) indirection for accessing this field, which will allow
developers to hide that name using fixups.
Talking about fixups, I continued with another rework that has been
asked for: changing the way fixups are listed. I am now creating a table
of fixups, which can be matched by ID and/or with a match function, as
per Michael Walle's suggestion. This cleans quite a bit the fixup lists
in the winbond driver, especially because of the new name hiding fixup,
so thanks for the suggestion!
Then I add support for JESD216 revision F and its new QER field.
Finally, I rework a bit the fixups in the Winbond driver, which allows
a clean addition of the new Winbond RV chips.
All chips I will ever be able to test are now listed and proof of
testing is below the commit message.
Thanks,
Miquèl
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
Changes in v3:
- Added support for two new chips that I could test (W25Q51RV-M and
W25Q02RV-Q/N). Edited the last commit which is now only adding the
256M-bit densities without the possibility to test, since I will not
receive any of these any time soon.
- Reworked completely the way fixups are now being applied.
- Re-instated the legacy .names, created a way to overwrite them and
enabled a fixup for that.
- Link to v2: https://lore.kernel.org/r/20260807-winbond-v7-1-spi-nor-rv-addition-v2-0-7797642dfc40@bootlin.com
Changes in v2:
- Added support for more chips that I received and could test. The main
logic in the first patches is completely untouched.
- Fixed the name of a parameter (s/sr2/srs/) in the low level read status
registers helper.
- Decided that there was no specific handling of the WP pin being
strapped wrt the read check over the SR content. This would be new,
and I don't think it is wide to handle it in the verify helper, but
instead this should be let to the caller to decide whether it needs
to hard fail or just degrade into single mode (typically if the QE
bit has not been written). But this would require an extra DT
property indicating the WP strap state which cannot be read back by
software.
- Created a structure to store the flash specific opcodes.
- Proposed a rename of BFPT_DWORD15_QER_SR2_BIT1_BUGGY in favour of
the _NO_1B_WR suffix.
- After checking, decided that the .name field is legacy and not part
of any stable API, thus it can be removed. So added back a commit
for that, removing the names for the whole JV family.
- Exposed all opcodes through debugfs, including the QE bit position.
- OTP and SWP writes are now read back like before.
- 2 known deviations are now explicitely stated in the commit log.
- I changed a little bit the QER field parsing in the sfdp.c driver, to
limit deviations, as much as my understanding would allow me.
- Link to v1: https://lore.kernel.org/r/20260529-winbond-v7-1-spi-nor-rv-addition-v1-0-f3ae18502d5a@bootlin.com
---
Miquel Raynal (23):
mtd: spi-nor: Rename BFPT_DWORD15_QER_SR2_BIT1_BUGGY
mtd: spi-nor: Create a structure containing the flash opcodes
mtd: spi-nor: Refactor Read Status/Write Status support
mtd: spi-nor: Add support for the new JESD216 rev F QER field
mtd: spi-nor: Create the concept of fixup table with match function
mtd: spi-nor: Create an indirection on the part name
mtd: spi-nor: Move the SFDP header structure to a C header
mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-Q/N parts
mtd: spi-nor: winbond: Add support for W25Q32RV-Q/N
mtd: spi-nor: winbond: Add support for W25Q64RV-Q/N
mtd: spi-nor: winbond: Add support for W25Q12RV-Q/N
mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N
mtd: spi-nor: winbond: Add support for W25Q01RV-Q/N
mtd: spi-nor: winbond: Add support for W25Q02RV-Q/N
mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-M parts
mtd: spi-nor: winbond: Add support for W25Q32RV-M
mtd: spi-nor: winbond: Add support for W25Q64RV-M
mtd: spi-nor: winbond: Add support for W25Q12RV-M
mtd: spi-nor: winbond: Add support for W25Q51RV-M
mtd: spi-nor: winbond: Add support for W25Q01RV-M
mtd: spi-nor: winbond: Add support for W25Q02RV-M
mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N/M
mtd: spi-nor: debugfs: Expose SR opcodes and QE mask
Documentation/driver-api/mtd/spi-nor.rst | 2 +-
drivers/mtd/spi-nor/atmel.c | 75 ++-
drivers/mtd/spi-nor/core.c | 875 ++++++++++++-------------------
drivers/mtd/spi-nor/core.h | 94 ++--
drivers/mtd/spi-nor/debugfs.c | 22 +-
drivers/mtd/spi-nor/everspin.c | 7 +-
drivers/mtd/spi-nor/gigadevice.c | 13 +-
drivers/mtd/spi-nor/issi.c | 25 +-
drivers/mtd/spi-nor/macronix.c | 35 +-
drivers/mtd/spi-nor/micron-st.c | 51 +-
drivers/mtd/spi-nor/otp.c | 16 +-
drivers/mtd/spi-nor/sfdp.c | 114 ++--
drivers/mtd/spi-nor/sfdp.h | 21 +-
drivers/mtd/spi-nor/spansion.c | 61 ++-
drivers/mtd/spi-nor/sst.c | 16 +-
drivers/mtd/spi-nor/swp.c | 58 +-
drivers/mtd/spi-nor/sysfs.c | 4 +-
drivers/mtd/spi-nor/winbond.c | 106 +++-
include/linux/mtd/spi-nor.h | 6 +-
19 files changed, 802 insertions(+), 799 deletions(-)
---
base-commit: 728e68a889bcf257b1e67298b12c360e5c3a13e0
change-id: 20260529-winbond-v7-1-spi-nor-rv-addition-cea2f1f158be
prerequisite-message-id: <20260805-winbond-v7-1-spi-nor-jv-cleanup-v5-0-87238e577794@bootlin.com>
prerequisite-patch-id: b4c64eddd0cbb8a67a3ceb3d5a8fb7118ee8bbd3
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prerequisite-patch-id: 07059d14bb516ba19fc0a678a96b3224f91caf24
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prerequisite-patch-id: eaeebc9df5221bab68a6cabc64a97e9c2608899b
Best regards,
--
Miquel Raynal <miquel.raynal@bootlin.com>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* [PATCH v3 01/23] mtd: spi-nor: Rename BFPT_DWORD15_QER_SR2_BIT1_BUGGY
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
The _BUGGY suffix is not super accurate. There is a behavior that indeed
seems strange, but it is somewhat documented. The fact is, with this QER
field the status register is considered 16-bit wide and if one writes
the first 8 bits (SR1) without the next 8 bits (SR2) then the content of
SR2 will be assumed to be 0x00 and will be cleared.
Rename it BFPT_DWORD15_QER_SR2_BIT1_NO_1B_WR to align with the other
namings (_NO_RD) and clarify the meaning of this field.
No functional change.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/sfdp.c | 2 +-
drivers/mtd/spi-nor/sfdp.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index cf0e2dc7c120..526763c79f55 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -567,7 +567,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
params->quad_enable = NULL;
break;
- case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
+ case BFPT_DWORD15_QER_SR2_BIT1_NO_1B_WR:
/*
* Writing only one byte to the Status Register has the
* side-effect of clearing Status Register 2.
diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h
index f74a0eb339ea..d976c6c9a4ad 100644
--- a/drivers/mtd/spi-nor/sfdp.h
+++ b/drivers/mtd/spi-nor/sfdp.h
@@ -84,7 +84,7 @@ struct sfdp_bfpt {
*/
#define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
-#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
+#define BFPT_DWORD15_QER_SR2_BIT1_NO_1B_WR (0x1UL << 20)
#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 01/23] mtd: spi-nor: Rename BFPT_DWORD15_QER_SR2_BIT1_BUGGY
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
The _BUGGY suffix is not super accurate. There is a behavior that indeed
seems strange, but it is somewhat documented. The fact is, with this QER
field the status register is considered 16-bit wide and if one writes
the first 8 bits (SR1) without the next 8 bits (SR2) then the content of
SR2 will be assumed to be 0x00 and will be cleared.
Rename it BFPT_DWORD15_QER_SR2_BIT1_NO_1B_WR to align with the other
namings (_NO_RD) and clarify the meaning of this field.
No functional change.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/sfdp.c | 2 +-
drivers/mtd/spi-nor/sfdp.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index cf0e2dc7c120..526763c79f55 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -567,7 +567,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
params->quad_enable = NULL;
break;
- case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
+ case BFPT_DWORD15_QER_SR2_BIT1_NO_1B_WR:
/*
* Writing only one byte to the Status Register has the
* side-effect of clearing Status Register 2.
diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h
index f74a0eb339ea..d976c6c9a4ad 100644
--- a/drivers/mtd/spi-nor/sfdp.h
+++ b/drivers/mtd/spi-nor/sfdp.h
@@ -84,7 +84,7 @@ struct sfdp_bfpt {
*/
#define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
-#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
+#define BFPT_DWORD15_QER_SR2_BIT1_NO_1B_WR (0x1UL << 20)
#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 02/23] mtd: spi-nor: Create a structure containing the flash opcodes
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
Create a structure named opcodes in the flash parameters structures to
store all the flash specific opcodes. They are typically discovered
dynamically through SFDP parsing. Move the die_erase opcode
inside. Later on we will add new fields there, like the supported
opcodes for accessing the status registers, which are almost vendor
specific.
No fonctional change.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/core.c | 6 +++---
drivers/mtd/spi-nor/core.h | 14 +++++++++++---
drivers/mtd/spi-nor/debugfs.c | 2 +-
drivers/mtd/spi-nor/micron-st.c | 4 ++--
drivers/mtd/spi-nor/spansion.c | 4 ++--
5 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index fef7f426a3a2..29b8fe3d1c65 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -1140,7 +1140,7 @@ static int spi_nor_erase_die(struct spi_nor *nor, loff_t addr, size_t die_size)
if (nor->spimem) {
struct spi_mem_op op =
- SPI_NOR_DIE_ERASE_OP(nor->params->die_erase_opcode,
+ SPI_NOR_DIE_ERASE_OP(nor->params->opcodes.die_erase,
nor->addr_nbytes, addr, multi_die);
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
@@ -3030,8 +3030,8 @@ static int spi_nor_late_init_params(struct spi_nor *nor)
return ret;
}
- if (!nor->params->die_erase_opcode)
- nor->params->die_erase_opcode = SPINOR_OP_CHIP_ERASE;
+ if (!nor->params->opcodes.die_erase)
+ nor->params->opcodes.die_erase = SPINOR_OP_CHIP_ERASE;
/* Default method kept for backward compatibility. */
if (!params->set_4byte_addr_mode)
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index ba2d1a862c9d..2cc0c80da3fa 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -340,6 +340,16 @@ struct spi_nor_otp {
const struct spi_nor_otp_ops *ops;
};
+/**
+ * struct spi_nor_opcodes - SPI NOR flash specific opcodes.
+ * List of variable opcodes used by the chip.
+ *
+ * @die_erase: opcode for erasing a die, defaults to SPINOR_OP_CHIP_ERASE
+ */
+struct spi_nor_opcodes {
+ u8 die_erase;
+};
+
/**
* struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
* Includes legacy flash parameters and settings that can be overwritten
@@ -362,7 +372,6 @@ struct spi_nor_otp {
* command in octal DTR mode.
* @n_banks: number of banks.
* @n_dice: number of dice in the flash memory.
- * @die_erase_opcode: die erase opcode. Defaults to SPINOR_OP_CHIP_ERASE.
* @vreg_offset: volatile register offset for each die.
* @hwcaps: describes the read and page program hardware
* capabilities.
@@ -393,13 +402,12 @@ struct spi_nor_flash_parameter {
u8 rdsr_addr_nbytes;
u8 n_banks;
u8 n_dice;
- u8 die_erase_opcode;
u32 *vreg_offset;
struct spi_nor_hwcaps hwcaps;
struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
-
+ struct spi_nor_opcodes opcodes;
struct spi_nor_erase_map erase_map;
struct spi_nor_otp otp;
diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
index 288e2866daed..ef6f0ffcd6bb 100644
--- a/drivers/mtd/spi-nor/debugfs.c
+++ b/drivers/mtd/spi-nor/debugfs.c
@@ -146,7 +146,7 @@ static int spi_nor_params_show(struct seq_file *s, void *data)
if (!(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
string_get_size(params->size, 1, STRING_UNITS_2, buf, sizeof(buf));
- seq_printf(s, " %02x (%s)\n", params->die_erase_opcode, buf);
+ seq_printf(s, " %02x (%s)\n", params->opcodes.die_erase, buf);
}
seq_puts(s, "\nsector map\n");
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index c75b0a1cd567..031cf887318c 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -131,7 +131,7 @@ static int micron_st_nor_four_die_late_init(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = nor->params;
- params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+ params->opcodes.die_erase = SPINOR_OP_MT_DIE_ERASE;
params->n_dice = 4;
/*
@@ -147,7 +147,7 @@ static int micron_st_nor_two_die_late_init(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = nor->params;
- params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+ params->opcodes.die_erase = SPINOR_OP_MT_DIE_ERASE;
params->n_dice = 2;
/*
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 15dcec09332a..2a8238c707e1 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -675,7 +675,7 @@ static int s25hx_t_late_init(struct spi_nor *nor)
cypress_nor_ecc_init(nor);
if (params->n_dice > 1)
- params->die_erase_opcode = SPINOR_OP_CYPRESS_DIE_ERASE;
+ params->opcodes.die_erase = SPINOR_OP_CYPRESS_DIE_ERASE;
return 0;
}
@@ -763,7 +763,7 @@ static int s28hx_t_late_init(struct spi_nor *nor)
cypress_nor_ecc_init(nor);
if (params->n_dice > 1)
- params->die_erase_opcode = SPINOR_OP_CYPRESS_DIE_ERASE;
+ params->opcodes.die_erase = SPINOR_OP_CYPRESS_DIE_ERASE;
return 0;
}
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 02/23] mtd: spi-nor: Create a structure containing the flash opcodes
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
Create a structure named opcodes in the flash parameters structures to
store all the flash specific opcodes. They are typically discovered
dynamically through SFDP parsing. Move the die_erase opcode
inside. Later on we will add new fields there, like the supported
opcodes for accessing the status registers, which are almost vendor
specific.
No fonctional change.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/core.c | 6 +++---
drivers/mtd/spi-nor/core.h | 14 +++++++++++---
drivers/mtd/spi-nor/debugfs.c | 2 +-
drivers/mtd/spi-nor/micron-st.c | 4 ++--
drivers/mtd/spi-nor/spansion.c | 4 ++--
5 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index fef7f426a3a2..29b8fe3d1c65 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -1140,7 +1140,7 @@ static int spi_nor_erase_die(struct spi_nor *nor, loff_t addr, size_t die_size)
if (nor->spimem) {
struct spi_mem_op op =
- SPI_NOR_DIE_ERASE_OP(nor->params->die_erase_opcode,
+ SPI_NOR_DIE_ERASE_OP(nor->params->opcodes.die_erase,
nor->addr_nbytes, addr, multi_die);
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
@@ -3030,8 +3030,8 @@ static int spi_nor_late_init_params(struct spi_nor *nor)
return ret;
}
- if (!nor->params->die_erase_opcode)
- nor->params->die_erase_opcode = SPINOR_OP_CHIP_ERASE;
+ if (!nor->params->opcodes.die_erase)
+ nor->params->opcodes.die_erase = SPINOR_OP_CHIP_ERASE;
/* Default method kept for backward compatibility. */
if (!params->set_4byte_addr_mode)
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index ba2d1a862c9d..2cc0c80da3fa 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -340,6 +340,16 @@ struct spi_nor_otp {
const struct spi_nor_otp_ops *ops;
};
+/**
+ * struct spi_nor_opcodes - SPI NOR flash specific opcodes.
+ * List of variable opcodes used by the chip.
+ *
+ * @die_erase: opcode for erasing a die, defaults to SPINOR_OP_CHIP_ERASE
+ */
+struct spi_nor_opcodes {
+ u8 die_erase;
+};
+
/**
* struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
* Includes legacy flash parameters and settings that can be overwritten
@@ -362,7 +372,6 @@ struct spi_nor_otp {
* command in octal DTR mode.
* @n_banks: number of banks.
* @n_dice: number of dice in the flash memory.
- * @die_erase_opcode: die erase opcode. Defaults to SPINOR_OP_CHIP_ERASE.
* @vreg_offset: volatile register offset for each die.
* @hwcaps: describes the read and page program hardware
* capabilities.
@@ -393,13 +402,12 @@ struct spi_nor_flash_parameter {
u8 rdsr_addr_nbytes;
u8 n_banks;
u8 n_dice;
- u8 die_erase_opcode;
u32 *vreg_offset;
struct spi_nor_hwcaps hwcaps;
struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
-
+ struct spi_nor_opcodes opcodes;
struct spi_nor_erase_map erase_map;
struct spi_nor_otp otp;
diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
index 288e2866daed..ef6f0ffcd6bb 100644
--- a/drivers/mtd/spi-nor/debugfs.c
+++ b/drivers/mtd/spi-nor/debugfs.c
@@ -146,7 +146,7 @@ static int spi_nor_params_show(struct seq_file *s, void *data)
if (!(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
string_get_size(params->size, 1, STRING_UNITS_2, buf, sizeof(buf));
- seq_printf(s, " %02x (%s)\n", params->die_erase_opcode, buf);
+ seq_printf(s, " %02x (%s)\n", params->opcodes.die_erase, buf);
}
seq_puts(s, "\nsector map\n");
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index c75b0a1cd567..031cf887318c 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -131,7 +131,7 @@ static int micron_st_nor_four_die_late_init(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = nor->params;
- params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+ params->opcodes.die_erase = SPINOR_OP_MT_DIE_ERASE;
params->n_dice = 4;
/*
@@ -147,7 +147,7 @@ static int micron_st_nor_two_die_late_init(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = nor->params;
- params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+ params->opcodes.die_erase = SPINOR_OP_MT_DIE_ERASE;
params->n_dice = 2;
/*
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 15dcec09332a..2a8238c707e1 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -675,7 +675,7 @@ static int s25hx_t_late_init(struct spi_nor *nor)
cypress_nor_ecc_init(nor);
if (params->n_dice > 1)
- params->die_erase_opcode = SPINOR_OP_CYPRESS_DIE_ERASE;
+ params->opcodes.die_erase = SPINOR_OP_CYPRESS_DIE_ERASE;
return 0;
}
@@ -763,7 +763,7 @@ static int s28hx_t_late_init(struct spi_nor *nor)
cypress_nor_ecc_init(nor);
if (params->n_dice > 1)
- params->die_erase_opcode = SPINOR_OP_CYPRESS_DIE_ERASE;
+ params->opcodes.die_erase = SPINOR_OP_CYPRESS_DIE_ERASE;
return 0;
}
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 03/23] mtd: spi-nor: Refactor Read Status/Write Status support
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
SPI NOR has a lot of history. Additions over additions, the subtleties
of the JESD216 specification, their implementations by the manufacturers
and the hardware mistakes have generated a gigantic maze, let's try to
understand what is really needed.
The specification explains the QE (Quad Enable) bitfield as describing
where the bit to enable the Quad capability is, but also how to set
it. Unfortunately, the specification is not precise about what opcodes
are supported exactly in all the cases. There is an introduction that
basically states:
- Opcode 0x05 reads SR1
- Opcode 0x35 reads SR2
- Opcode 0x01 writes SR1, and then SR2 if another byte is written
Then the bitfield, among indicating the location of the QE bit, may
indicate:
- Reading SR1 and SR2 in one operation is not possible (loops over the
content of SR1)
- Reading SR2 directly is possible
- Only writing SR1 zeroes SR2.
One problem with the current implementation, is that it only focuses on
the QE bit. A quad_enable function was created for each case, even
though in practice, the logic was always the same: read, modify, write,
read back and verify. One problem comes when other features need to play
with the status registers, like software block protection or OTP: you
never know how to properly handle the QE bit, nor where it is, nor how
to read/write the Status registers. This lead to
approximations/guessing (in swp.c, otp.c and obviously in legacy
controller drivers like atmel.c) but also to the implementation of a
gazillon of helpers for reading/writing/checking the status registers.
In addition, I believe some design decisions had a negative impact over
the years.
- All possible situations had to be flagged by the core. This is likely
wrong, because we no longer know why we need specific quirks. It was
ineherent to the state of the SPI NOR core before the great cleanup
that had happened the past few years. I believe this creates confusion
in the core today, and we should push this to vendor fixups
instead. As an example, in 2023 Hsin-Yi was facing an issue because
his chip was setting the wrong QER value, leading to RDCR being
prevented, thus falling into a condition blindly setting a random QE
bit (I strongy believe it is done like that for wrong reasons). His
chip actually had RDCR support! The correct fix should have been to
mark the capability in a device fixup instead of handling this in the
core.
Link: https://lore.kernel.org/lkml/CAJMQK-hR0eaO0b4Vd0U8_KAndLyZapqdHjVLAoe42rWi9rdLkA@mail.gmail.com/
- SFDP parsing is over cautious. I believe
BFPT_DWORD15_QER_SR2_BIT1_NO_RD is abusive (nothing states that RDCR is
not supported), and BFPT_DWORD15_QER_SR2_BIT1 is also out of
specification when forcing 16-bit Status writes.
- SNOR_F_HAS_16BIT_SR is only imposing 16bit Status writes, whereas
reads can still be 8-bit wide.
- The usage of helpers verifying the writes was also spread for IMHO no
really good reason. Why shouldn't we trust spi operations when it
comes to Status Registers? We do not read back our page reads, so why
status registers should be treated with so much care, if it's not
because we are unsure of what is being done? My proposal includes a
check when it comes to the QE bit (done once) but we don't need these
checks otherwise. If the QE bit was written properly, there are high
chances that the other register accesses will just be fine, no?
Asde from my main quest, I also observed no good reason to ask the
read/write status register callers to use nor->bouncebuf while the
low-level helpers could do it themselves (we are talking about one or
two bytes being copied).
So after these observations, my proposal is the following:
- Create private low level helpers that just read or write a status
register. They are flexible, we can give the opcode (which varies
based on the SFDP QER field) and the length (1 or 2).
- Create public generic accessors which will be used to read/write sr1
and/or sr2. This is where all the cleverness shall be. The helpers use
the available opcodes for a given chip in order to fullfill the
request.
- Provide a single generic ->quad_enable() hook which generically does
all the steps mentioned above (read, modify, write, read back and
verify).
- Create a list of opcodes for all 6 possible situations:
{read, write} {sr1, sr2, sr1 and sr2}. These opcodes are
filled/cleared based on the QER field. An opcode set to 0 indicates
the absence of support (there is no 0x00 opcode in SPI NOR).
I tried my best to analyze the current behavior and to mimic it as much
as possible, but this is a risky cleanup. However, if we go for this, it
will be *much* easier in the future to handle all kind of chip
variations. We won't be limited to a couple of flags anymore, but rather
we'll be able to just disable a read or write capability using a single
line.
Known deviations:
- The Atmel manufacturer driver drives non SFDP chips which by default
were receiving the HAS_16B_WR flag, forcing SR2 writes all the times,
but it was deliberately making single bytes writes to SR1 for its
locking operations. The flag is likely wrong for them, so I removed
it.
- I am proposing on purpose a single quad_enable helper. It should match
all the cases, with 1 identified difference which I believe is
harmless: in the SR2_BIT7 case, the helper would make an extra SR1
read/write which was not done before. This entry explicitly supports
reading and writing the two registers. Note: no manufacturer has been
identified to actually use that entry yet.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
This is a really hard to review patch, it is big, full of changes
everywhere, but I cannot really split it further. The commit log is
really important, it tries to explain the steps I went through when
trying to refactor the whole QE/SR handling for which I received
feedback from Michael, Tudor and Sashiko.
Ideally we could expect test coverage of each case:
- BFPT_DWORD15_QER_NONE: Probably not needed
- BFPT_DWORD15_QER_SR2_BIT1_BUGGY: Expected from Hsin-Yi (flag is being
renamed _NO_1B_WR)
- BFPT_DWORD15_QER_SR2_BIT1_NO_RD: Tested with a chip re-enabling RDCR
in a fixup
- BFPT_DWORD15_QER_SR1_BIT6: TBD
- BFPT_DWORD15_QER_SR2_BIT7: TBD
- BFPT_DWORD15_QER_SR2_BIT1: TBD
- BFPT_DWORD15_QER_SR2_BIT1_1B: Done.
There will probably be breakages on older chips. These cannot be
guessed because they are not properly listed in manufacturer
fixups (yet). If we want a cleanup/simplification, we will have to cope
with this risk.
I hope the diff stats will motivate people to have a look and report
their testing.
I will also eagerly monitor Sashiko's output which will probably be
very useful to catch niche weird cases where these changes might break.
---
Documentation/driver-api/mtd/spi-nor.rst | 2 +-
drivers/mtd/spi-nor/atmel.c | 52 +-
drivers/mtd/spi-nor/core.c | 784 +++++++++++--------------------
drivers/mtd/spi-nor/core.h | 57 +--
drivers/mtd/spi-nor/debugfs.c | 2 -
drivers/mtd/spi-nor/gigadevice.c | 6 +-
drivers/mtd/spi-nor/issi.c | 3 +-
drivers/mtd/spi-nor/macronix.c | 12 +-
drivers/mtd/spi-nor/micron-st.c | 4 +-
drivers/mtd/spi-nor/otp.c | 16 +-
drivers/mtd/spi-nor/sfdp.c | 41 +-
drivers/mtd/spi-nor/spansion.c | 16 +-
drivers/mtd/spi-nor/sst.c | 5 +-
drivers/mtd/spi-nor/swp.c | 58 +--
drivers/mtd/spi-nor/winbond.c | 4 +-
include/linux/mtd/spi-nor.h | 4 -
16 files changed, 416 insertions(+), 650 deletions(-)
diff --git a/Documentation/driver-api/mtd/spi-nor.rst b/Documentation/driver-api/mtd/spi-nor.rst
index 747a326fb6c0..5441fa7d4f04 100644
--- a/Documentation/driver-api/mtd/spi-nor.rst
+++ b/Documentation/driver-api/mtd/spi-nor.rst
@@ -118,7 +118,7 @@ section, after the ``---`` marker.
write size 1
page size 256
address nbytes 3
- flags HAS_LOCK | HAS_16BIT_SR | SOFT_RESET | SWP_IS_VOLATILE
+ flags HAS_LOCK | SOFT_RESET | SWP_IS_VOLATILE
opcodes
read 0xeb
diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
index 82c592f0a1e1..8741c0bda497 100644
--- a/drivers/mtd/spi-nor/atmel.c
+++ b/drivers/mtd/spi-nor/atmel.c
@@ -23,18 +23,28 @@ static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len)
static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
{
+ /* Write 0x00 to the status register to disable write protection */
+ u8 sr = 0;
int ret;
/* We only support unlocking the whole flash array */
if (ofs || len != nor->params->size)
return -EINVAL;
- /* Write 0x00 to the status register to disable write protection */
- ret = spi_nor_write_sr_and_check(nor, 0);
+ ret = spi_nor_write_sr1(nor, &sr);
if (ret)
- dev_dbg(nor->dev, "unable to clear BP bits, WP# asserted?\n");
+ return ret;
- return ret;
+ ret = spi_nor_read_sr1(nor, &sr);
+ if (ret)
+ return ret;
+
+ if (sr) {
+ dev_dbg(nor->dev, "unable to clear BP bits, WP# asserted?\n");
+ return -EIO;
+ }
+
+ return 0;
}
static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, u64 len)
@@ -50,6 +60,7 @@ static const struct spi_nor_locking_ops at25fs_nor_locking_ops = {
static int at25fs_nor_late_init(struct spi_nor *nor)
{
+ nor->params->opcodes.write_sr1 = SPINOR_OP_WRSR;
nor->params->locking_ops = &at25fs_nor_locking_ops;
return 0;
@@ -69,6 +80,7 @@ static const struct spi_nor_fixups at25fs_nor_fixups = {
* Return: 0 on success, -error otherwise.
*/
static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
+
u64 len, bool is_protect)
{
int ret;
@@ -78,19 +90,24 @@ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
if (ofs || len != nor->params->size)
return -EINVAL;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1(nor, &sr);
if (ret)
return ret;
- sr = nor->bouncebuf[0];
-
/* SRWD bit needs to be cleared, otherwise the protection doesn't change */
if (sr & SR_SRWD) {
sr &= ~SR_SRWD;
- ret = spi_nor_write_sr_and_check(nor, sr);
- if (ret) {
- dev_dbg(nor->dev, "unable to clear SRWD bit, WP# asserted?\n");
+ ret = spi_nor_write_sr1(nor, &sr);
+ if (ret)
return ret;
+
+ ret = spi_nor_read_sr1(nor, &sr);
+ if (ret)
+ return ret;
+
+ if (sr & SR_SRWD) {
+ dev_dbg(nor->dev, "unable to clear SRWD bit, WP# asserted?\n");
+ return -EIO;
}
}
@@ -108,14 +125,7 @@ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
sr &= ~ATMEL_SR_GLOBAL_PROTECT_MASK;
}
- nor->bouncebuf[0] = sr;
-
- /*
- * We cannot use the spi_nor_write_sr_and_check() because this command
- * isn't really setting any bits, instead it is an pseudo command for
- * "Global Unprotect" or "Global Protect"
- */
- return spi_nor_write_sr(nor, nor->bouncebuf, 1);
+ return spi_nor_write_sr1(nor, &sr);
}
static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs, u64 len)
@@ -131,16 +141,17 @@ static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs, u64 len)
static int atmel_nor_is_global_protected(struct spi_nor *nor, loff_t ofs,
u64 len)
{
+ u8 sr;
int ret;
if (ofs >= nor->params->size || (ofs + len) > nor->params->size)
return -EINVAL;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1(nor, &sr);
if (ret)
return ret;
- return ((nor->bouncebuf[0] & ATMEL_SR_GLOBAL_PROTECT_MASK) == ATMEL_SR_GLOBAL_PROTECT_MASK);
+ return ((sr & ATMEL_SR_GLOBAL_PROTECT_MASK) == ATMEL_SR_GLOBAL_PROTECT_MASK);
}
static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = {
@@ -151,6 +162,7 @@ static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = {
static int atmel_nor_global_protection_late_init(struct spi_nor *nor)
{
+ nor->params->opcodes.write_sr1 = SPINOR_OP_WRSR;
nor->params->locking_ops = &atmel_nor_global_protection_ops;
return 0;
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 29b8fe3d1c65..ac7812562047 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -443,75 +443,6 @@ int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
return ret;
}
-/**
- * spi_nor_read_sr() - Read the Status Register.
- * @nor: pointer to 'struct spi_nor'.
- * @sr: pointer to a DMA-able buffer where the value of the
- * Status Register will be written. Should be at least 2 bytes.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
-{
- int ret;
-
- if (nor->spimem) {
- struct spi_mem_op op = SPI_NOR_RDSR_OP(sr);
-
- if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
- op.addr.nbytes = nor->params->rdsr_addr_nbytes;
- op.dummy.nbytes = nor->params->rdsr_dummy;
- /*
- * We don't want to read only one byte in DTR mode. So,
- * read 2 and then discard the second byte.
- */
- op.data.nbytes = 2;
- }
-
- spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,
- 1);
- }
-
- if (ret)
- dev_dbg(nor->dev, "error %d reading SR\n", ret);
-
- return ret;
-}
-
-/**
- * spi_nor_read_cr() - Read the Configuration Register using the
- * SPINOR_OP_RDCR (35h) command.
- * @nor: pointer to 'struct spi_nor'
- * @cr: pointer to a DMA-able buffer where the value of the
- * Configuration Register will be written.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
-{
- int ret;
-
- if (nor->spimem) {
- struct spi_mem_op op = SPI_NOR_RDCR_OP(cr);
-
- spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr,
- 1);
- }
-
- if (ret)
- dev_dbg(nor->dev, "error %d reading CR\n", ret);
-
- return ret;
-}
-
/**
* spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode
* using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by
@@ -617,12 +548,13 @@ int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable)
int spi_nor_sr_ready(struct spi_nor *nor)
{
int ret;
+ u8 sr;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1(nor, &sr);
if (ret)
return ret;
- return !(nor->bouncebuf[0] & SR_WIP);
+ return !(sr & SR_WIP);
}
/**
@@ -784,345 +716,297 @@ int spi_nor_global_block_unlock(struct spi_nor *nor)
}
/**
- * spi_nor_write_sr() - Write the Status Register.
+ * spi_nor_read_sr_ll() - Low-level Status Registers read.
* @nor: pointer to 'struct spi_nor'.
- * @sr: pointer to DMA-able buffer to write to the Status Register.
- * @len: number of bytes to write to the Status Register.
+ * @opcode: opcode for the status register read operation.
+ * @sr: pointer to buffer for storing the content of the status registers.
+ * @len: number of status registers to read (1 or 2).
*
* Return: 0 on success, -errno otherwise.
*/
-int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
+static int spi_nor_read_sr_ll(struct spi_nor *nor, u8 opcode, u8 *sr,
+ unsigned int len)
{
- int ret;
+ int ret, i;
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
+ if (len > 2)
+ return -EINVAL;
+
+ for (i = 0; i < len; i++)
+ nor->bouncebuf[i] = 0;
if (nor->spimem) {
- struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len);
+ struct spi_mem_op op = SPI_NOR_RDSR_OP(opcode, nor->bouncebuf, len);
+
+ if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
+ op.addr.nbytes = nor->params->rdsr_addr_nbytes;
+ op.dummy.nbytes = nor->params->rdsr_dummy;
+ /*
+ * We don't want to read only one byte in DTR mode. So,
+ * read 2 and then discard the second byte.
+ */
+ op.data.nbytes = 2;
+ }
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr,
- len);
+ ret = spi_nor_controller_ops_read_reg(nor, opcode, nor->bouncebuf, len);
}
- if (ret) {
- dev_dbg(nor->dev, "error %d writing SR\n", ret);
- return ret;
- }
-
- return spi_nor_wait_till_ready(nor);
-}
-
-/**
- * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
- * ensure that the byte written match the received value.
- * @nor: pointer to a 'struct spi_nor'.
- * @sr1: byte value to be written to the Status Register.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
-{
- int ret;
-
- nor->bouncebuf[0] = sr1;
-
- ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
- if (ret)
- return ret;
-
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- if (nor->bouncebuf[0] != sr1) {
- dev_dbg(nor->dev, "SR1: read back test failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-/**
- * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
- * Status Register 2 in one shot. Ensure that the byte written in the Status
- * Register 1 match the received value, and that the 16-bit Write did not
- * affect what was already in the Status Register 2.
- * @nor: pointer to a 'struct spi_nor'.
- * @sr1: byte value to be written to the Status Register 1.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
-{
- int ret;
- u8 *sr_cr = nor->bouncebuf;
- u8 cr_written;
-
- /* Make sure we don't overwrite the contents of Status Register 2. */
- if (!(nor->flags & SNOR_F_NO_READ_CR)) {
- ret = spi_nor_read_cr(nor, &sr_cr[1]);
- if (ret)
- return ret;
- } else if ((spi_nor_get_protocol_width(nor->read_proto) == 4 ||
- spi_nor_get_protocol_width(nor->write_proto) == 4) &&
- nor->params->quad_enable) {
- /*
- * If the Status Register 2 Read command (35h) is not
- * supported, we should at least be sure we don't
- * change the value of the SR2 Quad Enable bit.
- *
- * When the Quad Enable method is set and the buswidth is 4, we
- * can safely assume that the value of the QE bit is one, as a
- * consequence of the nor->params->quad_enable() call.
- *
- * According to the JESD216 revB standard, BFPT DWORDS[15],
- * bits 22:20, the 16-bit Write Status (01h) command is
- * available just for the cases in which the QE bit is
- * described in SR2 at BIT(1).
- */
- sr_cr[1] = SR2_QUAD_EN_BIT1;
- } else {
- sr_cr[1] = 0;
- }
-
- sr_cr[0] = sr1;
-
- ret = spi_nor_write_sr(nor, sr_cr, 2);
- if (ret)
- return ret;
-
- ret = spi_nor_read_sr(nor, sr_cr);
- if (ret)
- return ret;
-
- if (sr1 != sr_cr[0]) {
- dev_dbg(nor->dev, "SR: Read back test failed\n");
- return -EIO;
- }
-
- if (nor->flags & SNOR_F_NO_READ_CR)
- return 0;
-
- cr_written = sr_cr[1];
-
- ret = spi_nor_read_cr(nor, &sr_cr[1]);
- if (ret)
- return ret;
-
- if (cr_written != sr_cr[1]) {
- dev_dbg(nor->dev, "CR: read back test failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-/**
- * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
- * Configuration Register in one shot. Ensure that the byte written in the
- * Configuration Register match the received value, and that the 16-bit Write
- * did not affect what was already in the Status Register 1.
- * @nor: pointer to a 'struct spi_nor'.
- * @cr: byte value to be written to the Configuration Register.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
-{
- int ret;
- u8 *sr_cr = nor->bouncebuf;
- u8 sr_written;
-
- /* Keep the current value of the Status Register 1. */
- ret = spi_nor_read_sr(nor, sr_cr);
- if (ret)
- return ret;
-
- sr_cr[1] = cr;
-
- ret = spi_nor_write_sr(nor, sr_cr, 2);
- if (ret)
- return ret;
-
- sr_written = sr_cr[0];
-
- ret = spi_nor_read_sr(nor, sr_cr);
- if (ret)
- return ret;
-
- if (sr_written != sr_cr[0]) {
- dev_dbg(nor->dev, "SR: Read back test failed\n");
- return -EIO;
- }
-
- if (nor->flags & SNOR_F_NO_READ_CR)
- return 0;
-
- ret = spi_nor_read_cr(nor, &sr_cr[1]);
- if (ret)
- return ret;
-
- if (cr != sr_cr[1]) {
- dev_dbg(nor->dev, "CR: read back test failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-/**
- * spi_nor_write_16bit_sr_cr_and_check() - Write the Status Register 1 and the
- * Configuration Register in one shot. Ensure that the bytes written in both
- * registers match the received value.
- * @nor: pointer to a 'struct spi_nor'.
- * @regs: two-byte array with values to be written to the status and
- * configuration registers.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_write_16bit_sr_cr_and_check(struct spi_nor *nor, const u8 *regs)
-{
- u8 written_regs[2];
- int ret;
-
- written_regs[0] = regs[0];
- written_regs[1] = regs[1];
- nor->bouncebuf[0] = regs[0];
- nor->bouncebuf[1] = regs[1];
-
- ret = spi_nor_write_sr(nor, nor->bouncebuf, 2);
- if (ret)
- return ret;
-
- ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
- if (ret)
- return ret;
-
- if (written_regs[0] != nor->bouncebuf[0]) {
- dev_dbg(nor->dev, "SR: Read back test failed\n");
- return -EIO;
- }
-
- if (nor->flags & SNOR_F_NO_READ_CR)
- return 0;
-
- ret = spi_nor_read_cr(nor, &nor->bouncebuf[1]);
- if (ret)
- return ret;
-
- if (written_regs[1] != nor->bouncebuf[1]) {
- dev_dbg(nor->dev, "CR: read back test failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-/**
- * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
- * the byte written match the received value without affecting other bits in the
- * Status Register 1 and 2.
- * @nor: pointer to a 'struct spi_nor'.
- * @sr1: byte value to be written to the Status Register.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
-{
- if (nor->flags & SNOR_F_HAS_16BIT_SR)
- return spi_nor_write_16bit_sr_and_check(nor, sr1);
-
- return spi_nor_write_sr1_and_check(nor, sr1);
-}
-
-/**
- * spi_nor_write_sr_cr_and_check() - Write the Status Register 1 and ensure that
- * the byte written match the received value. Same for the Control Register if
- * available.
- * @nor: pointer to a 'struct spi_nor'.
- * @regs: byte array to be written to the registers.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs)
-{
- if (nor->flags & SNOR_F_HAS_16BIT_SR)
- return spi_nor_write_16bit_sr_cr_and_check(nor, regs);
-
- return spi_nor_write_sr1_and_check(nor, regs[0]);
-}
-
-/**
- * spi_nor_write_sr2() - Write the Status Register 2 using the
- * SPINOR_OP_WRSR2 (3eh) command.
- * @nor: pointer to 'struct spi_nor'.
- * @sr2: pointer to DMA-able buffer to write to the Status Register 2.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
-{
- int ret;
-
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
-
- if (nor->spimem) {
- struct spi_mem_op op = SPI_NOR_WRSR2_OP(sr2);
-
- spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2,
- sr2, 1);
- }
-
- if (ret) {
- dev_dbg(nor->dev, "error %d writing SR2\n", ret);
- return ret;
- }
-
- return spi_nor_wait_till_ready(nor);
-}
-
-/**
- * spi_nor_read_sr2() - Read the Status Register 2 using the
- * SPINOR_OP_RDSR2 (3fh) command.
- * @nor: pointer to 'struct spi_nor'.
- * @sr2: pointer to DMA-able buffer where the value of the
- * Status Register 2 will be written.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
-{
- int ret;
-
- if (nor->spimem) {
- struct spi_mem_op op = SPI_NOR_RDSR2_OP(sr2);
-
- spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2,
- 1);
- }
+ memcpy(sr, nor->bouncebuf, len);
if (ret)
- dev_dbg(nor->dev, "error %d reading SR2\n", ret);
+ dev_dbg(nor->dev, "Error %d reading Status Registers\n", ret);
return ret;
}
+/**
+ * spi_nor_write_sr_ll() - Low-level Status Registers write.
+ * @nor: pointer to 'struct spi_nor'.
+ * @opcode: opcode for the status register write operation.
+ * @sr: pointer to status registers buffer to write.
+ * @len: number of status registers to write.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_write_sr_ll(struct spi_nor *nor, u8 opcode, const u8 *sr,
+ unsigned int len)
+{
+ int ret, i;
+
+ if (len > 2)
+ return -EINVAL;
+
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < len; i++)
+ nor->bouncebuf[i] = sr[i];
+
+ if (nor->spimem) {
+ struct spi_mem_op op = SPI_NOR_WRSR_OP(opcode,
+ nor->bouncebuf, len);
+
+ spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = spi_nor_controller_ops_write_reg(nor, opcode,
+ nor->bouncebuf, len);
+ }
+
+ if (ret) {
+ dev_dbg(nor->dev, "Error %d writing Status Registers\n", ret);
+ return ret;
+ }
+
+ return spi_nor_wait_till_ready(nor);
+}
+
+/**
+ * spi_nor_read_sr1() - Read SR1 only
+ * Useful for:
+ * - The core to offer a generic "read SR1 and SR2" capability
+ * - Manufacturer drivers (since they know the chip SR layout)
+ * - Polling the BUSY bit in the core
+ *
+ * @nor: the spi_nor structure
+ * @sr1: pointer to a valid SR1 buffer
+ *
+ * Return 0 or errno.
+ */
+int spi_nor_read_sr1(struct spi_nor *nor, u8 *sr1)
+{
+ return spi_nor_read_sr_ll(nor, nor->params->opcodes.read_sr1, sr1, 1);
+}
+
+/**
+ * spi_nor_read_sr2() - Read SR2 only
+ * Useful for:
+ * - The core to offer a generic "read SR1 and SR2" capability
+ * - Manufacturer drivers (since they know the chip SR layout)
+ * - SR2 based OTP configuration
+ *
+ * @nor: the spi_nor structure
+ * @sr2: pointer to a valid SR2 buffer
+ *
+ * Return 0 or errno.
+ */
+int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
+{
+ struct spi_nor_flash_parameter *params = nor->params;
+ int ret;
+
+ if (params->opcodes.read_sr2) {
+ ret = spi_nor_read_sr_ll(nor, params->opcodes.read_sr2, sr2, 1);
+ if (ret)
+ return ret;
+ } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
+ spi_nor_get_protocol_width(nor->write_proto) == 4) {
+ /* Make sure the QE bit is persistently kept */
+ *sr2 = params->qe_mask[1];
+ } else {
+ *sr2 = 0;
+ }
+
+ return 0;
+}
+
+/**
+ * spi_nor_read_sr1_and_sr2() - Read SR1 then SR2
+ * General purpose helper, always safe to call.
+ *
+ * @nor: the spi_nor structure
+ * @sr: pointer to a valid 2-byte array
+ *
+ * Return 0 or errno.
+ */
+int spi_nor_read_sr1_and_sr2(struct spi_nor *nor, u8 *sr)
+{
+ int ret;
+
+ ret = spi_nor_read_sr1(nor, &sr[0]);
+ if (ret)
+ return ret;
+
+ return spi_nor_read_sr2(nor, &sr[1]);
+}
+
+/**
+ * spi_nor_write_sr1() - Write SR1 only
+ * Useful for:
+ * - Manufacturer drivers (since they know the chip SR layout)
+ *
+ * @nor: the spi_nor structure
+ * @sr1: pointer to a valid SR1 buffer
+ *
+ * Return 0 or errno.
+ */
+int spi_nor_write_sr1(struct spi_nor *nor, const u8 *sr1)
+{
+ if (WARN_ONCE(!nor->params->opcodes.write_sr1,
+ "Restricted helper use, write SR1 not supported"))
+ return -EIO;
+
+ return spi_nor_write_sr_ll(nor, nor->params->opcodes.write_sr1, sr1, 1);
+}
+
+/**
+ * spi_nor_write_sr2() - Write SR2 only
+ * Useful for:
+ * - Manufacturer drivers (since they know the chip SR layout)
+ * - SR2 based OTP configuration
+ *
+ * @nor: the spi_nor structure
+ * @sr2: pointer to a valid SR2 buffer
+ *
+ * Return 0 or errno.
+ */
+int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
+{
+ if (WARN_ONCE(!nor->params->opcodes.write_sr2,
+ "Restricted helper use, write SR2 not supported"))
+ return -EIO;
+
+ return spi_nor_write_sr_ll(nor, nor->params->opcodes.write_sr2, sr2, 1);
+}
+
+/**
+ * spi_nor_write_sr1_and_sr2() - Write SR1 then SR2
+ * General purpose helper, always safe to call. Will expectedly ignore
+ * SR2 on certain chips.
+ *
+ * @nor: the spi_nor structure
+ * @sr: pointer to a valid 2-byte array
+ *
+ * Return 0 or errno.
+ */
+static int spi_nor_write_sr1_and_sr2(struct spi_nor *nor, const u8 *sr)
+{
+ struct spi_nor_flash_parameter *params = nor->params;
+ int ret;
+
+ if (params->opcodes.write_sr1_and_sr2)
+ return spi_nor_write_sr_ll(nor,
+ params->opcodes.write_sr1_and_sr2,
+ sr, 2);
+
+ ret = spi_nor_write_sr1(nor, &sr[0]);
+ if (ret)
+ return ret;
+
+ if (params->opcodes.write_sr2)
+ return spi_nor_write_sr2(nor, &sr[1]);
+
+ return 0;
+}
+
+/**
+ * spi_nor_write_sr1_and_sr2_and_check() - Write SR1 then SR2, then read
+ * them back and verifies
+ * General purpose helper, always safe to call. Will expectedly ignore
+ * SR2 on certain chips.
+ *
+ * @nor: the spi_nor structure
+ * @sr: pointer to a valid 2-byte array
+ *
+ * Return 0 or errno.
+ */
+int spi_nor_write_sr1_and_sr2_and_check(struct spi_nor *nor, const u8 *sr)
+{
+ u8 tmp[2];
+ int ret;
+
+ ret = spi_nor_write_sr1_and_sr2(nor, sr);
+ if (ret)
+ return ret;
+
+ ret = spi_nor_read_sr1_and_sr2(nor, tmp);
+ if (ret)
+ return ret;
+
+ if (sr[0] != tmp[0] || sr[1] != tmp[1])
+ return -EIO;
+
+ return 0;
+}
+
+/**
+ * spi_nor_generic_quad_enable() - Read the status registers,
+ * apply the QE bit mask,
+ * write the status registers,
+ * read them back and check the content.
+ *
+ * @nor: pointer to 'struct spi_nor'
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_generic_quad_enable(struct spi_nor *nor)
+{
+ u8 *qe_mask = nor->params->qe_mask;
+ u8 sr[2] = {};
+ int ret;
+
+ if (!qe_mask[0] && !qe_mask[1])
+ return 0;
+
+ ret = spi_nor_read_sr1_and_sr2(nor, sr);
+ if (ret)
+ return ret;
+
+ if (sr[0] & qe_mask[0] || sr[1] & qe_mask[1])
+ return 0;
+
+ sr[0] |= qe_mask[0];
+ sr[1] |= qe_mask[1];
+
+ return spi_nor_write_sr1_and_sr2_and_check(nor, sr);
+}
+
/**
* spi_nor_erase_die() - Erase the entire die.
* @nor: pointer to 'struct spi_nor'.
@@ -1904,106 +1788,6 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
return ret;
}
-/**
- * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
- * Register 1.
- * @nor: pointer to a 'struct spi_nor'
- *
- * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
-{
- int ret;
-
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
- return 0;
-
- nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
-
- return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
-}
-
-/**
- * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
- * Register 2.
- * @nor: pointer to a 'struct spi_nor'.
- *
- * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
-{
- int ret;
-
- if (nor->flags & SNOR_F_NO_READ_CR)
- return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
-
- ret = spi_nor_read_cr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
- return 0;
-
- nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
-
- return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
-}
-
-/**
- * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
- * @nor: pointer to a 'struct spi_nor'
- *
- * Set the Quad Enable (QE) bit in the Status Register 2.
- *
- * This is one of the procedures to set the QE bit described in the SFDP
- * (JESD216 rev B) specification but no manufacturer using this procedure has
- * been identified yet, hence the name of the function.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
-{
- u8 *sr2 = nor->bouncebuf;
- int ret;
- u8 sr2_written;
-
- /* Check current Quad Enable bit value. */
- ret = spi_nor_read_sr2(nor, sr2);
- if (ret)
- return ret;
- if (*sr2 & SR2_QUAD_EN_BIT7)
- return 0;
-
- /* Update the Quad Enable bit. */
- *sr2 |= SR2_QUAD_EN_BIT7;
-
- ret = spi_nor_write_sr2(nor, sr2);
- if (ret)
- return ret;
-
- sr2_written = *sr2;
-
- /* Read back and check it. */
- ret = spi_nor_read_sr2(nor, sr2);
- if (ret)
- return ret;
-
- if (*sr2 != sr2_written) {
- dev_dbg(nor->dev, "SR2: Read back test failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
static const struct spi_nor_manufacturer *manufacturers[] = {
&spi_nor_atmel,
&spi_nor_eon,
@@ -2494,6 +2278,7 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
{
struct spi_nor_flash_parameter *params = nor->params;
unsigned int cap;
+ u8 opcode;
/* X-X-X modes are not supported yet, mask them all. */
*hwcaps &= ~SNOR_HWCAPS_X_X_X;
@@ -2525,14 +2310,14 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
*hwcaps &= ~BIT(cap);
}
- /* Some SPI controllers might not support CR read opcode. */
- if (!(nor->flags & SNOR_F_NO_READ_CR)) {
- struct spi_mem_op op = SPI_NOR_RDCR_OP(nor->bouncebuf);
-
+ /* Some SPI controllers might not support reading SR2 */
+ opcode = nor->params->opcodes.read_sr2;
+ if (opcode) {
+ struct spi_mem_op op = SPI_NOR_RDSR_OP(opcode, nor->bouncebuf, 1);
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
if (!spi_mem_supports_op(nor->spimem, &op))
- nor->flags |= SNOR_F_NO_READ_CR;
+ nor->params->opcodes.read_sr2 = 0;
}
}
@@ -3107,11 +2892,14 @@ static void spi_nor_init_default_params(struct spi_nor *nor)
const struct flash_info *info = nor->info;
struct device_node *np = spi_nor_get_flash_node(nor);
- params->quad_enable = spi_nor_sr2_bit1_quad_enable;
- params->otp.org = info->otp;
+ /* Default to 16-bit Read/Write Status commands */
+ params->opcodes.read_sr1 = SPINOR_OP_RDSR;
+ params->opcodes.read_sr2 = SPINOR_OP_RDCR;
+ params->opcodes.write_sr1_and_sr2 = SPINOR_OP_WRSR;
+ params->quad_enable = spi_nor_generic_quad_enable;
+ params->qe_mask[1] = BIT(1);
- /* Default to 16-bit Write Status (01h) Command */
- nor->flags |= SNOR_F_HAS_16BIT_SR;
+ params->otp.org = info->otp;
/* Set SPI NOR sizes. */
params->writesize = 1;
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 2cc0c80da3fa..7d43d3ba47ee 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -37,36 +37,18 @@
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_NO_DATA)
-#define SPI_NOR_RDSR_OP(buf) \
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), \
+#define SPI_NOR_RDSR_OP(opcode, buf, len) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
SPI_MEM_OP_NO_ADDR, \
SPI_MEM_OP_NO_DUMMY, \
- SPI_MEM_OP_DATA_IN(1, buf, 0))
+ SPI_MEM_OP_DATA_IN(len, buf, 0))
-#define SPI_NOR_WRSR_OP(buf, len) \
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), \
+#define SPI_NOR_WRSR_OP(opcode, buf, len) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
SPI_MEM_OP_NO_ADDR, \
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_DATA_OUT(len, buf, 0))
-#define SPI_NOR_RDSR2_OP(buf) \
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), \
- SPI_MEM_OP_NO_ADDR, \
- SPI_MEM_OP_NO_DUMMY, \
- SPI_MEM_OP_DATA_OUT(1, buf, 0))
-
-#define SPI_NOR_WRSR2_OP(buf) \
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), \
- SPI_MEM_OP_NO_ADDR, \
- SPI_MEM_OP_NO_DUMMY, \
- SPI_MEM_OP_DATA_OUT(1, buf, 0))
-
-#define SPI_NOR_RDCR_OP(buf) \
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), \
- SPI_MEM_OP_NO_ADDR, \
- SPI_MEM_OP_NO_DUMMY, \
- SPI_MEM_OP_DATA_IN(1, buf, 0))
-
#define SPI_NOR_EN4B_EX4B_OP(enable) \
SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B, 0), \
SPI_MEM_OP_NO_ADDR, \
@@ -129,8 +111,6 @@ enum spi_nor_option_flags {
SNOR_F_4B_OPCODES = BIT(3),
SNOR_F_HAS_4BAIT = BIT(4),
SNOR_F_HAS_LOCK = BIT(5),
- SNOR_F_HAS_16BIT_SR = BIT(6),
- SNOR_F_NO_READ_CR = BIT(7),
SNOR_F_HAS_SR_TB_BIT6 = BIT(8),
SNOR_F_HAS_4BIT_BP = BIT(9),
SNOR_F_HAS_SR_BP3_BIT6 = BIT(10),
@@ -345,9 +325,19 @@ struct spi_nor_otp {
* List of variable opcodes used by the chip.
*
* @die_erase: opcode for erasing a die, defaults to SPINOR_OP_CHIP_ERASE
+ * @read_sr1: opcode for reading SR1 alone
+ * @read_sr2: opcode for reading SR2 alone
+ * @write_sr1: opcode for writing SR1 alone
+ * @write_sr2: opcode for writing SR2 alone
+ * @write_sr1_and_sr2: opcode for writing SR1 then SR2 in one operation
*/
struct spi_nor_opcodes {
u8 die_erase;
+ u8 read_sr1;
+ u8 read_sr2;
+ u8 write_sr1;
+ u8 write_sr2;
+ u8 write_sr1_and_sr2;
};
/**
@@ -384,6 +374,7 @@ struct spi_nor_opcodes {
* @otp: SPI NOR OTP info.
* @set_octal_dtr: enables or disables SPI NOR octal DTR mode.
* @quad_enable: enables SPI NOR quad mode.
+ * @qe_mask: two bytes mask used to set/clear the QE bit
* @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
* @ready: (optional) flashes might use a different mechanism
* than reading the status register to indicate they
@@ -413,6 +404,7 @@ struct spi_nor_flash_parameter {
int (*set_octal_dtr)(struct spi_nor *nor, bool enable);
int (*quad_enable)(struct spi_nor *nor);
+ u8 qe_mask[2];
int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
int (*ready)(struct spi_nor *nor);
@@ -641,18 +633,15 @@ int spi_nor_wait_till_ready(struct spi_nor *nor);
int spi_nor_global_block_unlock(struct spi_nor *nor);
int spi_nor_prep_and_lock(struct spi_nor *nor);
void spi_nor_unlock_and_unprep(struct spi_nor *nor);
-int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
-int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
-int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
enum spi_nor_protocol reg_proto);
-int spi_nor_read_sr(struct spi_nor *nor, u8 *sr);
int spi_nor_sr_ready(struct spi_nor *nor);
-int spi_nor_read_cr(struct spi_nor *nor, u8 *cr);
-int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len);
-int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1);
-int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr);
-int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs);
+int spi_nor_read_sr1(struct spi_nor *nor, u8 *sr1);
+int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2);
+int spi_nor_read_sr1_and_sr2(struct spi_nor *nor, u8 *sr);
+int spi_nor_write_sr1(struct spi_nor *nor, const u8 *sr1);
+int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2);
+int spi_nor_write_sr1_and_sr2_and_check(struct spi_nor *nor, const u8 *sr);
ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
u8 *buf);
diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
index ef6f0ffcd6bb..512825c3fc85 100644
--- a/drivers/mtd/spi-nor/debugfs.c
+++ b/drivers/mtd/spi-nor/debugfs.c
@@ -19,8 +19,6 @@ static const char *const snor_f_names[] = {
SNOR_F_NAME(4B_OPCODES),
SNOR_F_NAME(HAS_4BAIT),
SNOR_F_NAME(HAS_LOCK),
- SNOR_F_NAME(HAS_16BIT_SR),
- SNOR_F_NAME(NO_READ_CR),
SNOR_F_NAME(HAS_SR_TB_BIT6),
SNOR_F_NAME(HAS_4BIT_BP),
SNOR_F_NAME(HAS_SR_BP3_BIT6),
diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
index ef1edd0add70..4070a692e968 100644
--- a/drivers/mtd/spi-nor/gigadevice.c
+++ b/drivers/mtd/spi-nor/gigadevice.c
@@ -23,8 +23,10 @@ gd25q256_post_bfpt(struct spi_nor *nor,
* GD25Q256E | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR
*/
if (bfpt_header->major == SFDP_JESD216_MAJOR &&
- bfpt_header->minor == SFDP_JESD216_MINOR)
- nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ bfpt_header->minor == SFDP_JESD216_MINOR) {
+ nor->params->qe_mask[0] = BIT(6);
+ nor->params->qe_mask[1] = 0;
+ }
return 0;
}
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index 18d9a00aa22e..04db42b5141e 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -131,7 +131,8 @@ static const struct flash_info issi_nor_parts[] = {
static void issi_nor_default_init(struct spi_nor *nor)
{
- nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ nor->params->qe_mask[0] = BIT(6);
+ nor->params->qe_mask[1] = 0;
}
static const struct spi_nor_fixups issi_fixups = {
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index e97f5cbd9aad..55612237c1ef 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -65,11 +65,12 @@ mx25l3255e_late_init_fixups(struct spi_nor *nor)
/*
* SFDP of MX25L3255E is JESD216, which does not include the Quad
- * Enable bit Requirement in BFPT. As a result, during BFPT parsing,
- * the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.
- * Therefore, it is necessary to correct this setting by late_init.
+ * Enable bit Requirement in BFPT. As a result, during BFPT parsing
+ * the quad_enable mask is reset. Therefore, it is necessary to
+ * correct this setting by late_init.
*/
- params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ params->qe_mask[0] = BIT(6);
+ params->qe_mask[1] = 0;
/*
* In addition, MX25L3255E also supports 1-4-4 page program in 3-byte
@@ -314,7 +315,8 @@ static int macronix_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
static void macronix_nor_default_init(struct spi_nor *nor)
{
- nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ nor->params->qe_mask[0] = BIT(6);
+ nor->params->qe_mask[1] = 0;
}
static int macronix_nor_late_init(struct spi_nor *nor)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 031cf887318c..344539d2a36a 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -229,7 +229,7 @@ static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt)
{
- nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+ nor->params->opcodes.write_sr1 = 0;
return 0;
}
@@ -633,7 +633,7 @@ static int micron_st_nor_ready(struct spi_nor *nor)
static void micron_st_nor_default_init(struct spi_nor *nor)
{
nor->flags |= SNOR_F_HAS_LOCK;
- nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+ nor->params->opcodes.write_sr1 = 0;
nor->params->quad_enable = NULL;
}
diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
index 7d0b145d78d8..1eeb33a20091 100644
--- a/drivers/mtd/spi-nor/otp.c
+++ b/drivers/mtd/spi-nor/otp.c
@@ -175,24 +175,24 @@ static int spi_nor_otp_lock_bit_cr(unsigned int region)
*/
int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigned int region)
{
- u8 *cr = nor->bouncebuf;
int ret, lock_bit;
+ u8 sr[2];
lock_bit = spi_nor_otp_lock_bit_cr(region);
if (lock_bit < 0)
return lock_bit;
- ret = spi_nor_read_cr(nor, cr);
+ ret = spi_nor_read_sr1_and_sr2(nor, sr);
if (ret)
return ret;
/* no need to write the register if region is already locked */
- if (cr[0] & lock_bit)
+ if (sr[1] & lock_bit)
return 0;
- cr[0] |= lock_bit;
+ sr[1] |= lock_bit;
- return spi_nor_write_16bit_cr_and_check(nor, cr[0]);
+ return spi_nor_write_sr1_and_sr2_and_check(nor, sr);
}
/**
@@ -207,18 +207,18 @@ int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigned int region)
*/
int spi_nor_otp_is_locked_sr2(struct spi_nor *nor, unsigned int region)
{
- u8 *cr = nor->bouncebuf;
int ret, lock_bit;
+ u8 sr2;
lock_bit = spi_nor_otp_lock_bit_cr(region);
if (lock_bit < 0)
return lock_bit;
- ret = spi_nor_read_cr(nor, cr);
+ ret = spi_nor_read_sr2(nor, &sr2);
if (ret)
return ret;
- return cr[0] & lock_bit;
+ return sr2 & lock_bit;
}
static loff_t spi_nor_otp_region_start(const struct spi_nor *nor, unsigned int region)
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index 526763c79f55..1d799f02b8e5 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -561,10 +561,21 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
val >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
params->page_size = 1U << val;
+ /*
+ * The standard declares various read and write status methods, some of
+ * them will be overloaded based on the QER field.
+ */
+ params->opcodes.read_sr1 = SPINOR_OP_RDSR;
+ params->opcodes.read_sr2 = SPINOR_OP_RDCR;
+ params->opcodes.write_sr1 = SPINOR_OP_WRSR;
+ params->opcodes.write_sr1_and_sr2 = SPINOR_OP_WRSR;
+
+ params->qe_mask[0] = 0;
+ params->qe_mask[1] = 0;
+
/* Quad Enable Requirements. */
switch (bfpt.dwords[SFDP_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
case BFPT_DWORD15_QER_NONE:
- params->quad_enable = NULL;
break;
case BFPT_DWORD15_QER_SR2_BIT1_NO_1B_WR:
@@ -572,23 +583,28 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
* Writing only one byte to the Status Register has the
* side-effect of clearing Status Register 2.
*/
+ fallthrough;
case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
/*
* Read Configuration Register (35h) instruction is not
- * supported.
+ * supported. 16-bit writes expected.
*/
- nor->flags |= SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR;
- params->quad_enable = spi_nor_sr2_bit1_quad_enable;
+ params->opcodes.read_sr2 = 0;
+ params->opcodes.write_sr1 = 0;
+ params->qe_mask[1] = BIT(1);
break;
case BFPT_DWORD15_QER_SR1_BIT6:
- nor->flags &= ~SNOR_F_HAS_16BIT_SR;
- params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ params->opcodes.read_sr2 = 0;
+ params->opcodes.write_sr1_and_sr2 = 0;
+ params->qe_mask[0] = BIT(6);
break;
case BFPT_DWORD15_QER_SR2_BIT7:
- nor->flags &= ~SNOR_F_HAS_16BIT_SR;
- params->quad_enable = spi_nor_sr2_bit7_quad_enable;
+ params->opcodes.read_sr2 = SPINOR_OP_RDSR2;
+ params->opcodes.write_sr1_and_sr2 = 0;
+ params->opcodes.write_sr2 = SPINOR_OP_WRSR2;
+ params->qe_mask[1] = BIT(7);
break;
case BFPT_DWORD15_QER_SR2_BIT1:
@@ -598,9 +614,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
* Register 2, so let's be cautious and keep the default
* assumption of a 16-bit Write Status (01h) command.
*/
- nor->flags |= SNOR_F_HAS_16BIT_SR;
-
- params->quad_enable = spi_nor_sr2_bit1_quad_enable;
+ params->opcodes.write_sr1 = 0;
+ params->qe_mask[1] = BIT(1);
break;
default:
@@ -608,6 +623,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
break;
}
+ /* opcodes sanity check */
+ WARN_ON(!params->opcodes.read_sr1 ||
+ (!params->opcodes.write_sr1 && !params->opcodes.write_sr1_and_sr2));
+
dword = bfpt.dwords[SFDP_DWORD(16)] & BFPT_DWORD16_4B_ADDR_MODE_MASK;
if (SFDP_MASK_CHECK(dword, BFPT_DWORD16_4B_ADDR_MODE_BRWR))
params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr;
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 2a8238c707e1..ca2703a5a338 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -399,8 +399,9 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
nor->bouncebuf);
bool is3byte, is4byte;
int ret;
+ u8 sr;
- ret = spi_nor_read_sr(nor, &nor->bouncebuf[1]);
+ ret = spi_nor_read_sr1(nor, &sr);
if (ret)
return ret;
@@ -408,7 +409,7 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
if (ret)
return ret;
- is3byte = (nor->bouncebuf[0] == nor->bouncebuf[1]);
+ is3byte = (nor->bouncebuf[0] == sr);
op = (struct spi_mem_op)
CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0,
@@ -417,7 +418,7 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
if (ret)
return ret;
- is4byte = (nor->bouncebuf[0] == nor->bouncebuf[1]);
+ is4byte = (nor->bouncebuf[0] == sr);
if (is3byte == is4byte)
return -EIO;
@@ -1103,13 +1104,14 @@ static const struct flash_info spansion_nor_parts[] = {
static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
{
int ret;
+ u8 sr;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1(nor, &sr);
if (ret)
return ret;
- if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
- if (nor->bouncebuf[0] & SR_E_ERR)
+ if (sr & (SR_E_ERR | SR_P_ERR)) {
+ if (sr & SR_E_ERR)
dev_err(nor->dev, "Erase Error occurred\n");
else
dev_err(nor->dev, "Programming Error occurred\n");
@@ -1129,7 +1131,7 @@ static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
return -EIO;
}
- return !(nor->bouncebuf[0] & SR_WIP);
+ return !(sr & SR_WIP);
}
static int spansion_nor_late_init(struct spi_nor *nor)
diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
index db02c14ba16f..77a0bc41d4e5 100644
--- a/drivers/mtd/spi-nor/sst.c
+++ b/drivers/mtd/spi-nor/sst.c
@@ -21,16 +21,17 @@ static int sst26vf_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len)
static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
{
int ret;
+ u8 cr;
/* We only support unlocking the entire flash array. */
if (ofs != 0 || len != nor->params->size)
return -EINVAL;
- ret = spi_nor_read_cr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr2(nor, &cr);
if (ret)
return ret;
- if (!(nor->bouncebuf[0] & SST26VF_CR_BPNV)) {
+ if (!(cr & SST26VF_CR_BPNV)) {
dev_dbg(nor->dev, "Any block has been permanently locked\n");
return -EINVAL;
}
diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c
index 235070b215d1..b7b291e15917 100644
--- a/drivers/mtd/spi-nor/swp.c
+++ b/drivers/mtd/spi-nor/swp.c
@@ -36,7 +36,7 @@ static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor)
static u8 spi_nor_get_sr_cmp_mask(struct spi_nor *nor)
{
- if (!(nor->flags & SNOR_F_NO_READ_CR) &&
+ if (nor->params->opcodes.read_sr2 &&
nor->flags & SNOR_F_HAS_SR2_CMP_BIT6)
return SR2_CMP_BIT6;
else
@@ -207,17 +207,9 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u8 *sr)
if (!sr) {
- if (spi_nor_read_sr(nor, nor->bouncebuf))
+ if (spi_nor_read_sr1_and_sr2(nor, sr_cr))
return;
- sr_cr[0] = nor->bouncebuf[0];
-
- if (!(nor->flags & SNOR_F_NO_READ_CR)) {
- if (spi_nor_read_cr(nor, nor->bouncebuf))
- return;
- }
-
- sr_cr[1] = nor->bouncebuf[0];
sr = sr_cr;
}
@@ -273,20 +265,10 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)
int ret;
u8 pow;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1_and_sr2(nor, status_old);
if (ret)
return ret;
- status_old[0] = nor->bouncebuf[0];
-
- if (!(nor->flags & SNOR_F_NO_READ_CR)) {
- ret = spi_nor_read_cr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- status_old[1] = nor->bouncebuf[0];
- }
-
/* If nothing in our range is unlocked, we don't need to do anything */
if (spi_nor_is_locked_sr(nor, ofs, len, status_old))
return 0;
@@ -378,10 +360,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)
(ofs_old < ofs_new || (ofs_new + len_new) < (ofs_old + len_old)))
return -EINVAL;
- if (nor->flags & SNOR_F_NO_READ_CR)
- ret = spi_nor_write_sr_and_check(nor, best_status_new[0]);
- else
- ret = spi_nor_write_sr_cr_and_check(nor, best_status_new);
+ ret = spi_nor_write_sr1_and_sr2_and_check(nor, best_status_new);
if (ret)
return ret;
@@ -409,20 +388,10 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
int ret;
u8 pow;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1_and_sr2(nor, status_old);
if (ret)
return ret;
- status_old[0] = nor->bouncebuf[0];
-
- if (!(nor->flags & SNOR_F_NO_READ_CR)) {
- ret = spi_nor_read_cr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- status_old[1] = nor->bouncebuf[0];
- }
-
/* If nothing in our range is locked, we don't need to do anything */
if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old))
return 0;
@@ -512,10 +481,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
(ofs_new < ofs_old || (ofs_old + len_old) < (ofs_new + len_new)))
return -EINVAL;
- if (nor->flags & SNOR_F_NO_READ_CR)
- ret = spi_nor_write_sr_and_check(nor, best_status_new[0]);
- else
- ret = spi_nor_write_sr_cr_and_check(nor, best_status_new);
+ ret = spi_nor_write_sr1_and_sr2_and_check(nor, best_status_new);
if (ret)
return ret;
@@ -536,20 +502,10 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, u64 len)
u8 sr_cr[2] = {};
int ret;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1_and_sr2(nor, sr_cr);
if (ret)
return ret;
- sr_cr[0] = nor->bouncebuf[0];
-
- if (!(nor->flags & SNOR_F_NO_READ_CR)) {
- ret = spi_nor_read_cr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- sr_cr[1] = nor->bouncebuf[0];
- }
-
return spi_nor_is_locked_sr(nor, ofs, len, sr_cr);
}
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 593429bd6cdf..01a693033448 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -520,12 +520,12 @@ static int winbond_nor_late_init(struct spi_nor *nor)
* been to declare CR reads as unsupported, whereas the Jedec
* specification doesn't clearly state that. In practice, all these
* chips do support reading back the CR, which is needed for SWP support,
- * so make sure that capability remains enabled (needed for SWP).
+ * so make sure that capability remains enabled.
* In practice, only exclude the old W25X family (JEDEC ID: EF 30 xx)
* which actually does not support this feature.
*/
if (nor->id[1] > 0x30)
- nor->flags &= ~SNOR_F_NO_READ_CR;
+ params->opcodes.read_sr2 = SPINOR_OP_RDCR;
/*
* Winbond has reused many IDs, up to four times at this
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 4b92494827b1..f0b5a1989881 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -113,20 +113,16 @@
#define SR_E_ERR BIT(5)
#define SR_P_ERR BIT(6)
-#define SR1_QUAD_EN_BIT6 BIT(6)
-
#define SR_BP_SHIFT 2
/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
/* Status Register 2 bits. */
-#define SR2_QUAD_EN_BIT1 BIT(1)
#define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */
#define SR2_LB2 BIT(4) /* Security Register Lock Bit 2 */
#define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */
#define SR2_CMP_BIT6 BIT(6)
-#define SR2_QUAD_EN_BIT7 BIT(7)
/* Supported SPI protocols */
#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 03/23] mtd: spi-nor: Refactor Read Status/Write Status support
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
SPI NOR has a lot of history. Additions over additions, the subtleties
of the JESD216 specification, their implementations by the manufacturers
and the hardware mistakes have generated a gigantic maze, let's try to
understand what is really needed.
The specification explains the QE (Quad Enable) bitfield as describing
where the bit to enable the Quad capability is, but also how to set
it. Unfortunately, the specification is not precise about what opcodes
are supported exactly in all the cases. There is an introduction that
basically states:
- Opcode 0x05 reads SR1
- Opcode 0x35 reads SR2
- Opcode 0x01 writes SR1, and then SR2 if another byte is written
Then the bitfield, among indicating the location of the QE bit, may
indicate:
- Reading SR1 and SR2 in one operation is not possible (loops over the
content of SR1)
- Reading SR2 directly is possible
- Only writing SR1 zeroes SR2.
One problem with the current implementation, is that it only focuses on
the QE bit. A quad_enable function was created for each case, even
though in practice, the logic was always the same: read, modify, write,
read back and verify. One problem comes when other features need to play
with the status registers, like software block protection or OTP: you
never know how to properly handle the QE bit, nor where it is, nor how
to read/write the Status registers. This lead to
approximations/guessing (in swp.c, otp.c and obviously in legacy
controller drivers like atmel.c) but also to the implementation of a
gazillon of helpers for reading/writing/checking the status registers.
In addition, I believe some design decisions had a negative impact over
the years.
- All possible situations had to be flagged by the core. This is likely
wrong, because we no longer know why we need specific quirks. It was
ineherent to the state of the SPI NOR core before the great cleanup
that had happened the past few years. I believe this creates confusion
in the core today, and we should push this to vendor fixups
instead. As an example, in 2023 Hsin-Yi was facing an issue because
his chip was setting the wrong QER value, leading to RDCR being
prevented, thus falling into a condition blindly setting a random QE
bit (I strongy believe it is done like that for wrong reasons). His
chip actually had RDCR support! The correct fix should have been to
mark the capability in a device fixup instead of handling this in the
core.
Link: https://lore.kernel.org/lkml/CAJMQK-hR0eaO0b4Vd0U8_KAndLyZapqdHjVLAoe42rWi9rdLkA@mail.gmail.com/
- SFDP parsing is over cautious. I believe
BFPT_DWORD15_QER_SR2_BIT1_NO_RD is abusive (nothing states that RDCR is
not supported), and BFPT_DWORD15_QER_SR2_BIT1 is also out of
specification when forcing 16-bit Status writes.
- SNOR_F_HAS_16BIT_SR is only imposing 16bit Status writes, whereas
reads can still be 8-bit wide.
- The usage of helpers verifying the writes was also spread for IMHO no
really good reason. Why shouldn't we trust spi operations when it
comes to Status Registers? We do not read back our page reads, so why
status registers should be treated with so much care, if it's not
because we are unsure of what is being done? My proposal includes a
check when it comes to the QE bit (done once) but we don't need these
checks otherwise. If the QE bit was written properly, there are high
chances that the other register accesses will just be fine, no?
Asde from my main quest, I also observed no good reason to ask the
read/write status register callers to use nor->bouncebuf while the
low-level helpers could do it themselves (we are talking about one or
two bytes being copied).
So after these observations, my proposal is the following:
- Create private low level helpers that just read or write a status
register. They are flexible, we can give the opcode (which varies
based on the SFDP QER field) and the length (1 or 2).
- Create public generic accessors which will be used to read/write sr1
and/or sr2. This is where all the cleverness shall be. The helpers use
the available opcodes for a given chip in order to fullfill the
request.
- Provide a single generic ->quad_enable() hook which generically does
all the steps mentioned above (read, modify, write, read back and
verify).
- Create a list of opcodes for all 6 possible situations:
{read, write} {sr1, sr2, sr1 and sr2}. These opcodes are
filled/cleared based on the QER field. An opcode set to 0 indicates
the absence of support (there is no 0x00 opcode in SPI NOR).
I tried my best to analyze the current behavior and to mimic it as much
as possible, but this is a risky cleanup. However, if we go for this, it
will be *much* easier in the future to handle all kind of chip
variations. We won't be limited to a couple of flags anymore, but rather
we'll be able to just disable a read or write capability using a single
line.
Known deviations:
- The Atmel manufacturer driver drives non SFDP chips which by default
were receiving the HAS_16B_WR flag, forcing SR2 writes all the times,
but it was deliberately making single bytes writes to SR1 for its
locking operations. The flag is likely wrong for them, so I removed
it.
- I am proposing on purpose a single quad_enable helper. It should match
all the cases, with 1 identified difference which I believe is
harmless: in the SR2_BIT7 case, the helper would make an extra SR1
read/write which was not done before. This entry explicitly supports
reading and writing the two registers. Note: no manufacturer has been
identified to actually use that entry yet.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
This is a really hard to review patch, it is big, full of changes
everywhere, but I cannot really split it further. The commit log is
really important, it tries to explain the steps I went through when
trying to refactor the whole QE/SR handling for which I received
feedback from Michael, Tudor and Sashiko.
Ideally we could expect test coverage of each case:
- BFPT_DWORD15_QER_NONE: Probably not needed
- BFPT_DWORD15_QER_SR2_BIT1_BUGGY: Expected from Hsin-Yi (flag is being
renamed _NO_1B_WR)
- BFPT_DWORD15_QER_SR2_BIT1_NO_RD: Tested with a chip re-enabling RDCR
in a fixup
- BFPT_DWORD15_QER_SR1_BIT6: TBD
- BFPT_DWORD15_QER_SR2_BIT7: TBD
- BFPT_DWORD15_QER_SR2_BIT1: TBD
- BFPT_DWORD15_QER_SR2_BIT1_1B: Done.
There will probably be breakages on older chips. These cannot be
guessed because they are not properly listed in manufacturer
fixups (yet). If we want a cleanup/simplification, we will have to cope
with this risk.
I hope the diff stats will motivate people to have a look and report
their testing.
I will also eagerly monitor Sashiko's output which will probably be
very useful to catch niche weird cases where these changes might break.
---
Documentation/driver-api/mtd/spi-nor.rst | 2 +-
drivers/mtd/spi-nor/atmel.c | 52 +-
drivers/mtd/spi-nor/core.c | 784 +++++++++++--------------------
drivers/mtd/spi-nor/core.h | 57 +--
drivers/mtd/spi-nor/debugfs.c | 2 -
drivers/mtd/spi-nor/gigadevice.c | 6 +-
drivers/mtd/spi-nor/issi.c | 3 +-
drivers/mtd/spi-nor/macronix.c | 12 +-
drivers/mtd/spi-nor/micron-st.c | 4 +-
drivers/mtd/spi-nor/otp.c | 16 +-
drivers/mtd/spi-nor/sfdp.c | 41 +-
drivers/mtd/spi-nor/spansion.c | 16 +-
drivers/mtd/spi-nor/sst.c | 5 +-
drivers/mtd/spi-nor/swp.c | 58 +--
drivers/mtd/spi-nor/winbond.c | 4 +-
include/linux/mtd/spi-nor.h | 4 -
16 files changed, 416 insertions(+), 650 deletions(-)
diff --git a/Documentation/driver-api/mtd/spi-nor.rst b/Documentation/driver-api/mtd/spi-nor.rst
index 747a326fb6c0..5441fa7d4f04 100644
--- a/Documentation/driver-api/mtd/spi-nor.rst
+++ b/Documentation/driver-api/mtd/spi-nor.rst
@@ -118,7 +118,7 @@ section, after the ``---`` marker.
write size 1
page size 256
address nbytes 3
- flags HAS_LOCK | HAS_16BIT_SR | SOFT_RESET | SWP_IS_VOLATILE
+ flags HAS_LOCK | SOFT_RESET | SWP_IS_VOLATILE
opcodes
read 0xeb
diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
index 82c592f0a1e1..8741c0bda497 100644
--- a/drivers/mtd/spi-nor/atmel.c
+++ b/drivers/mtd/spi-nor/atmel.c
@@ -23,18 +23,28 @@ static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len)
static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
{
+ /* Write 0x00 to the status register to disable write protection */
+ u8 sr = 0;
int ret;
/* We only support unlocking the whole flash array */
if (ofs || len != nor->params->size)
return -EINVAL;
- /* Write 0x00 to the status register to disable write protection */
- ret = spi_nor_write_sr_and_check(nor, 0);
+ ret = spi_nor_write_sr1(nor, &sr);
if (ret)
- dev_dbg(nor->dev, "unable to clear BP bits, WP# asserted?\n");
+ return ret;
- return ret;
+ ret = spi_nor_read_sr1(nor, &sr);
+ if (ret)
+ return ret;
+
+ if (sr) {
+ dev_dbg(nor->dev, "unable to clear BP bits, WP# asserted?\n");
+ return -EIO;
+ }
+
+ return 0;
}
static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, u64 len)
@@ -50,6 +60,7 @@ static const struct spi_nor_locking_ops at25fs_nor_locking_ops = {
static int at25fs_nor_late_init(struct spi_nor *nor)
{
+ nor->params->opcodes.write_sr1 = SPINOR_OP_WRSR;
nor->params->locking_ops = &at25fs_nor_locking_ops;
return 0;
@@ -69,6 +80,7 @@ static const struct spi_nor_fixups at25fs_nor_fixups = {
* Return: 0 on success, -error otherwise.
*/
static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
+
u64 len, bool is_protect)
{
int ret;
@@ -78,19 +90,24 @@ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
if (ofs || len != nor->params->size)
return -EINVAL;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1(nor, &sr);
if (ret)
return ret;
- sr = nor->bouncebuf[0];
-
/* SRWD bit needs to be cleared, otherwise the protection doesn't change */
if (sr & SR_SRWD) {
sr &= ~SR_SRWD;
- ret = spi_nor_write_sr_and_check(nor, sr);
- if (ret) {
- dev_dbg(nor->dev, "unable to clear SRWD bit, WP# asserted?\n");
+ ret = spi_nor_write_sr1(nor, &sr);
+ if (ret)
return ret;
+
+ ret = spi_nor_read_sr1(nor, &sr);
+ if (ret)
+ return ret;
+
+ if (sr & SR_SRWD) {
+ dev_dbg(nor->dev, "unable to clear SRWD bit, WP# asserted?\n");
+ return -EIO;
}
}
@@ -108,14 +125,7 @@ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
sr &= ~ATMEL_SR_GLOBAL_PROTECT_MASK;
}
- nor->bouncebuf[0] = sr;
-
- /*
- * We cannot use the spi_nor_write_sr_and_check() because this command
- * isn't really setting any bits, instead it is an pseudo command for
- * "Global Unprotect" or "Global Protect"
- */
- return spi_nor_write_sr(nor, nor->bouncebuf, 1);
+ return spi_nor_write_sr1(nor, &sr);
}
static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs, u64 len)
@@ -131,16 +141,17 @@ static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs, u64 len)
static int atmel_nor_is_global_protected(struct spi_nor *nor, loff_t ofs,
u64 len)
{
+ u8 sr;
int ret;
if (ofs >= nor->params->size || (ofs + len) > nor->params->size)
return -EINVAL;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1(nor, &sr);
if (ret)
return ret;
- return ((nor->bouncebuf[0] & ATMEL_SR_GLOBAL_PROTECT_MASK) == ATMEL_SR_GLOBAL_PROTECT_MASK);
+ return ((sr & ATMEL_SR_GLOBAL_PROTECT_MASK) == ATMEL_SR_GLOBAL_PROTECT_MASK);
}
static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = {
@@ -151,6 +162,7 @@ static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = {
static int atmel_nor_global_protection_late_init(struct spi_nor *nor)
{
+ nor->params->opcodes.write_sr1 = SPINOR_OP_WRSR;
nor->params->locking_ops = &atmel_nor_global_protection_ops;
return 0;
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 29b8fe3d1c65..ac7812562047 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -443,75 +443,6 @@ int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
return ret;
}
-/**
- * spi_nor_read_sr() - Read the Status Register.
- * @nor: pointer to 'struct spi_nor'.
- * @sr: pointer to a DMA-able buffer where the value of the
- * Status Register will be written. Should be at least 2 bytes.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
-{
- int ret;
-
- if (nor->spimem) {
- struct spi_mem_op op = SPI_NOR_RDSR_OP(sr);
-
- if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
- op.addr.nbytes = nor->params->rdsr_addr_nbytes;
- op.dummy.nbytes = nor->params->rdsr_dummy;
- /*
- * We don't want to read only one byte in DTR mode. So,
- * read 2 and then discard the second byte.
- */
- op.data.nbytes = 2;
- }
-
- spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,
- 1);
- }
-
- if (ret)
- dev_dbg(nor->dev, "error %d reading SR\n", ret);
-
- return ret;
-}
-
-/**
- * spi_nor_read_cr() - Read the Configuration Register using the
- * SPINOR_OP_RDCR (35h) command.
- * @nor: pointer to 'struct spi_nor'
- * @cr: pointer to a DMA-able buffer where the value of the
- * Configuration Register will be written.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
-{
- int ret;
-
- if (nor->spimem) {
- struct spi_mem_op op = SPI_NOR_RDCR_OP(cr);
-
- spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr,
- 1);
- }
-
- if (ret)
- dev_dbg(nor->dev, "error %d reading CR\n", ret);
-
- return ret;
-}
-
/**
* spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode
* using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by
@@ -617,12 +548,13 @@ int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable)
int spi_nor_sr_ready(struct spi_nor *nor)
{
int ret;
+ u8 sr;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1(nor, &sr);
if (ret)
return ret;
- return !(nor->bouncebuf[0] & SR_WIP);
+ return !(sr & SR_WIP);
}
/**
@@ -784,345 +716,297 @@ int spi_nor_global_block_unlock(struct spi_nor *nor)
}
/**
- * spi_nor_write_sr() - Write the Status Register.
+ * spi_nor_read_sr_ll() - Low-level Status Registers read.
* @nor: pointer to 'struct spi_nor'.
- * @sr: pointer to DMA-able buffer to write to the Status Register.
- * @len: number of bytes to write to the Status Register.
+ * @opcode: opcode for the status register read operation.
+ * @sr: pointer to buffer for storing the content of the status registers.
+ * @len: number of status registers to read (1 or 2).
*
* Return: 0 on success, -errno otherwise.
*/
-int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
+static int spi_nor_read_sr_ll(struct spi_nor *nor, u8 opcode, u8 *sr,
+ unsigned int len)
{
- int ret;
+ int ret, i;
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
+ if (len > 2)
+ return -EINVAL;
+
+ for (i = 0; i < len; i++)
+ nor->bouncebuf[i] = 0;
if (nor->spimem) {
- struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len);
+ struct spi_mem_op op = SPI_NOR_RDSR_OP(opcode, nor->bouncebuf, len);
+
+ if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
+ op.addr.nbytes = nor->params->rdsr_addr_nbytes;
+ op.dummy.nbytes = nor->params->rdsr_dummy;
+ /*
+ * We don't want to read only one byte in DTR mode. So,
+ * read 2 and then discard the second byte.
+ */
+ op.data.nbytes = 2;
+ }
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr,
- len);
+ ret = spi_nor_controller_ops_read_reg(nor, opcode, nor->bouncebuf, len);
}
- if (ret) {
- dev_dbg(nor->dev, "error %d writing SR\n", ret);
- return ret;
- }
-
- return spi_nor_wait_till_ready(nor);
-}
-
-/**
- * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
- * ensure that the byte written match the received value.
- * @nor: pointer to a 'struct spi_nor'.
- * @sr1: byte value to be written to the Status Register.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
-{
- int ret;
-
- nor->bouncebuf[0] = sr1;
-
- ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
- if (ret)
- return ret;
-
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- if (nor->bouncebuf[0] != sr1) {
- dev_dbg(nor->dev, "SR1: read back test failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-/**
- * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
- * Status Register 2 in one shot. Ensure that the byte written in the Status
- * Register 1 match the received value, and that the 16-bit Write did not
- * affect what was already in the Status Register 2.
- * @nor: pointer to a 'struct spi_nor'.
- * @sr1: byte value to be written to the Status Register 1.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
-{
- int ret;
- u8 *sr_cr = nor->bouncebuf;
- u8 cr_written;
-
- /* Make sure we don't overwrite the contents of Status Register 2. */
- if (!(nor->flags & SNOR_F_NO_READ_CR)) {
- ret = spi_nor_read_cr(nor, &sr_cr[1]);
- if (ret)
- return ret;
- } else if ((spi_nor_get_protocol_width(nor->read_proto) == 4 ||
- spi_nor_get_protocol_width(nor->write_proto) == 4) &&
- nor->params->quad_enable) {
- /*
- * If the Status Register 2 Read command (35h) is not
- * supported, we should at least be sure we don't
- * change the value of the SR2 Quad Enable bit.
- *
- * When the Quad Enable method is set and the buswidth is 4, we
- * can safely assume that the value of the QE bit is one, as a
- * consequence of the nor->params->quad_enable() call.
- *
- * According to the JESD216 revB standard, BFPT DWORDS[15],
- * bits 22:20, the 16-bit Write Status (01h) command is
- * available just for the cases in which the QE bit is
- * described in SR2 at BIT(1).
- */
- sr_cr[1] = SR2_QUAD_EN_BIT1;
- } else {
- sr_cr[1] = 0;
- }
-
- sr_cr[0] = sr1;
-
- ret = spi_nor_write_sr(nor, sr_cr, 2);
- if (ret)
- return ret;
-
- ret = spi_nor_read_sr(nor, sr_cr);
- if (ret)
- return ret;
-
- if (sr1 != sr_cr[0]) {
- dev_dbg(nor->dev, "SR: Read back test failed\n");
- return -EIO;
- }
-
- if (nor->flags & SNOR_F_NO_READ_CR)
- return 0;
-
- cr_written = sr_cr[1];
-
- ret = spi_nor_read_cr(nor, &sr_cr[1]);
- if (ret)
- return ret;
-
- if (cr_written != sr_cr[1]) {
- dev_dbg(nor->dev, "CR: read back test failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-/**
- * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
- * Configuration Register in one shot. Ensure that the byte written in the
- * Configuration Register match the received value, and that the 16-bit Write
- * did not affect what was already in the Status Register 1.
- * @nor: pointer to a 'struct spi_nor'.
- * @cr: byte value to be written to the Configuration Register.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
-{
- int ret;
- u8 *sr_cr = nor->bouncebuf;
- u8 sr_written;
-
- /* Keep the current value of the Status Register 1. */
- ret = spi_nor_read_sr(nor, sr_cr);
- if (ret)
- return ret;
-
- sr_cr[1] = cr;
-
- ret = spi_nor_write_sr(nor, sr_cr, 2);
- if (ret)
- return ret;
-
- sr_written = sr_cr[0];
-
- ret = spi_nor_read_sr(nor, sr_cr);
- if (ret)
- return ret;
-
- if (sr_written != sr_cr[0]) {
- dev_dbg(nor->dev, "SR: Read back test failed\n");
- return -EIO;
- }
-
- if (nor->flags & SNOR_F_NO_READ_CR)
- return 0;
-
- ret = spi_nor_read_cr(nor, &sr_cr[1]);
- if (ret)
- return ret;
-
- if (cr != sr_cr[1]) {
- dev_dbg(nor->dev, "CR: read back test failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-/**
- * spi_nor_write_16bit_sr_cr_and_check() - Write the Status Register 1 and the
- * Configuration Register in one shot. Ensure that the bytes written in both
- * registers match the received value.
- * @nor: pointer to a 'struct spi_nor'.
- * @regs: two-byte array with values to be written to the status and
- * configuration registers.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_write_16bit_sr_cr_and_check(struct spi_nor *nor, const u8 *regs)
-{
- u8 written_regs[2];
- int ret;
-
- written_regs[0] = regs[0];
- written_regs[1] = regs[1];
- nor->bouncebuf[0] = regs[0];
- nor->bouncebuf[1] = regs[1];
-
- ret = spi_nor_write_sr(nor, nor->bouncebuf, 2);
- if (ret)
- return ret;
-
- ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
- if (ret)
- return ret;
-
- if (written_regs[0] != nor->bouncebuf[0]) {
- dev_dbg(nor->dev, "SR: Read back test failed\n");
- return -EIO;
- }
-
- if (nor->flags & SNOR_F_NO_READ_CR)
- return 0;
-
- ret = spi_nor_read_cr(nor, &nor->bouncebuf[1]);
- if (ret)
- return ret;
-
- if (written_regs[1] != nor->bouncebuf[1]) {
- dev_dbg(nor->dev, "CR: read back test failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
-/**
- * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
- * the byte written match the received value without affecting other bits in the
- * Status Register 1 and 2.
- * @nor: pointer to a 'struct spi_nor'.
- * @sr1: byte value to be written to the Status Register.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
-{
- if (nor->flags & SNOR_F_HAS_16BIT_SR)
- return spi_nor_write_16bit_sr_and_check(nor, sr1);
-
- return spi_nor_write_sr1_and_check(nor, sr1);
-}
-
-/**
- * spi_nor_write_sr_cr_and_check() - Write the Status Register 1 and ensure that
- * the byte written match the received value. Same for the Control Register if
- * available.
- * @nor: pointer to a 'struct spi_nor'.
- * @regs: byte array to be written to the registers.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs)
-{
- if (nor->flags & SNOR_F_HAS_16BIT_SR)
- return spi_nor_write_16bit_sr_cr_and_check(nor, regs);
-
- return spi_nor_write_sr1_and_check(nor, regs[0]);
-}
-
-/**
- * spi_nor_write_sr2() - Write the Status Register 2 using the
- * SPINOR_OP_WRSR2 (3eh) command.
- * @nor: pointer to 'struct spi_nor'.
- * @sr2: pointer to DMA-able buffer to write to the Status Register 2.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
-{
- int ret;
-
- ret = spi_nor_write_enable(nor);
- if (ret)
- return ret;
-
- if (nor->spimem) {
- struct spi_mem_op op = SPI_NOR_WRSR2_OP(sr2);
-
- spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2,
- sr2, 1);
- }
-
- if (ret) {
- dev_dbg(nor->dev, "error %d writing SR2\n", ret);
- return ret;
- }
-
- return spi_nor_wait_till_ready(nor);
-}
-
-/**
- * spi_nor_read_sr2() - Read the Status Register 2 using the
- * SPINOR_OP_RDSR2 (3fh) command.
- * @nor: pointer to 'struct spi_nor'.
- * @sr2: pointer to DMA-able buffer where the value of the
- * Status Register 2 will be written.
- *
- * Return: 0 on success, -errno otherwise.
- */
-static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
-{
- int ret;
-
- if (nor->spimem) {
- struct spi_mem_op op = SPI_NOR_RDSR2_OP(sr2);
-
- spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
- ret = spi_mem_exec_op(nor->spimem, &op);
- } else {
- ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2,
- 1);
- }
+ memcpy(sr, nor->bouncebuf, len);
if (ret)
- dev_dbg(nor->dev, "error %d reading SR2\n", ret);
+ dev_dbg(nor->dev, "Error %d reading Status Registers\n", ret);
return ret;
}
+/**
+ * spi_nor_write_sr_ll() - Low-level Status Registers write.
+ * @nor: pointer to 'struct spi_nor'.
+ * @opcode: opcode for the status register write operation.
+ * @sr: pointer to status registers buffer to write.
+ * @len: number of status registers to write.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_write_sr_ll(struct spi_nor *nor, u8 opcode, const u8 *sr,
+ unsigned int len)
+{
+ int ret, i;
+
+ if (len > 2)
+ return -EINVAL;
+
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < len; i++)
+ nor->bouncebuf[i] = sr[i];
+
+ if (nor->spimem) {
+ struct spi_mem_op op = SPI_NOR_WRSR_OP(opcode,
+ nor->bouncebuf, len);
+
+ spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ } else {
+ ret = spi_nor_controller_ops_write_reg(nor, opcode,
+ nor->bouncebuf, len);
+ }
+
+ if (ret) {
+ dev_dbg(nor->dev, "Error %d writing Status Registers\n", ret);
+ return ret;
+ }
+
+ return spi_nor_wait_till_ready(nor);
+}
+
+/**
+ * spi_nor_read_sr1() - Read SR1 only
+ * Useful for:
+ * - The core to offer a generic "read SR1 and SR2" capability
+ * - Manufacturer drivers (since they know the chip SR layout)
+ * - Polling the BUSY bit in the core
+ *
+ * @nor: the spi_nor structure
+ * @sr1: pointer to a valid SR1 buffer
+ *
+ * Return 0 or errno.
+ */
+int spi_nor_read_sr1(struct spi_nor *nor, u8 *sr1)
+{
+ return spi_nor_read_sr_ll(nor, nor->params->opcodes.read_sr1, sr1, 1);
+}
+
+/**
+ * spi_nor_read_sr2() - Read SR2 only
+ * Useful for:
+ * - The core to offer a generic "read SR1 and SR2" capability
+ * - Manufacturer drivers (since they know the chip SR layout)
+ * - SR2 based OTP configuration
+ *
+ * @nor: the spi_nor structure
+ * @sr2: pointer to a valid SR2 buffer
+ *
+ * Return 0 or errno.
+ */
+int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
+{
+ struct spi_nor_flash_parameter *params = nor->params;
+ int ret;
+
+ if (params->opcodes.read_sr2) {
+ ret = spi_nor_read_sr_ll(nor, params->opcodes.read_sr2, sr2, 1);
+ if (ret)
+ return ret;
+ } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
+ spi_nor_get_protocol_width(nor->write_proto) == 4) {
+ /* Make sure the QE bit is persistently kept */
+ *sr2 = params->qe_mask[1];
+ } else {
+ *sr2 = 0;
+ }
+
+ return 0;
+}
+
+/**
+ * spi_nor_read_sr1_and_sr2() - Read SR1 then SR2
+ * General purpose helper, always safe to call.
+ *
+ * @nor: the spi_nor structure
+ * @sr: pointer to a valid 2-byte array
+ *
+ * Return 0 or errno.
+ */
+int spi_nor_read_sr1_and_sr2(struct spi_nor *nor, u8 *sr)
+{
+ int ret;
+
+ ret = spi_nor_read_sr1(nor, &sr[0]);
+ if (ret)
+ return ret;
+
+ return spi_nor_read_sr2(nor, &sr[1]);
+}
+
+/**
+ * spi_nor_write_sr1() - Write SR1 only
+ * Useful for:
+ * - Manufacturer drivers (since they know the chip SR layout)
+ *
+ * @nor: the spi_nor structure
+ * @sr1: pointer to a valid SR1 buffer
+ *
+ * Return 0 or errno.
+ */
+int spi_nor_write_sr1(struct spi_nor *nor, const u8 *sr1)
+{
+ if (WARN_ONCE(!nor->params->opcodes.write_sr1,
+ "Restricted helper use, write SR1 not supported"))
+ return -EIO;
+
+ return spi_nor_write_sr_ll(nor, nor->params->opcodes.write_sr1, sr1, 1);
+}
+
+/**
+ * spi_nor_write_sr2() - Write SR2 only
+ * Useful for:
+ * - Manufacturer drivers (since they know the chip SR layout)
+ * - SR2 based OTP configuration
+ *
+ * @nor: the spi_nor structure
+ * @sr2: pointer to a valid SR2 buffer
+ *
+ * Return 0 or errno.
+ */
+int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
+{
+ if (WARN_ONCE(!nor->params->opcodes.write_sr2,
+ "Restricted helper use, write SR2 not supported"))
+ return -EIO;
+
+ return spi_nor_write_sr_ll(nor, nor->params->opcodes.write_sr2, sr2, 1);
+}
+
+/**
+ * spi_nor_write_sr1_and_sr2() - Write SR1 then SR2
+ * General purpose helper, always safe to call. Will expectedly ignore
+ * SR2 on certain chips.
+ *
+ * @nor: the spi_nor structure
+ * @sr: pointer to a valid 2-byte array
+ *
+ * Return 0 or errno.
+ */
+static int spi_nor_write_sr1_and_sr2(struct spi_nor *nor, const u8 *sr)
+{
+ struct spi_nor_flash_parameter *params = nor->params;
+ int ret;
+
+ if (params->opcodes.write_sr1_and_sr2)
+ return spi_nor_write_sr_ll(nor,
+ params->opcodes.write_sr1_and_sr2,
+ sr, 2);
+
+ ret = spi_nor_write_sr1(nor, &sr[0]);
+ if (ret)
+ return ret;
+
+ if (params->opcodes.write_sr2)
+ return spi_nor_write_sr2(nor, &sr[1]);
+
+ return 0;
+}
+
+/**
+ * spi_nor_write_sr1_and_sr2_and_check() - Write SR1 then SR2, then read
+ * them back and verifies
+ * General purpose helper, always safe to call. Will expectedly ignore
+ * SR2 on certain chips.
+ *
+ * @nor: the spi_nor structure
+ * @sr: pointer to a valid 2-byte array
+ *
+ * Return 0 or errno.
+ */
+int spi_nor_write_sr1_and_sr2_and_check(struct spi_nor *nor, const u8 *sr)
+{
+ u8 tmp[2];
+ int ret;
+
+ ret = spi_nor_write_sr1_and_sr2(nor, sr);
+ if (ret)
+ return ret;
+
+ ret = spi_nor_read_sr1_and_sr2(nor, tmp);
+ if (ret)
+ return ret;
+
+ if (sr[0] != tmp[0] || sr[1] != tmp[1])
+ return -EIO;
+
+ return 0;
+}
+
+/**
+ * spi_nor_generic_quad_enable() - Read the status registers,
+ * apply the QE bit mask,
+ * write the status registers,
+ * read them back and check the content.
+ *
+ * @nor: pointer to 'struct spi_nor'
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_generic_quad_enable(struct spi_nor *nor)
+{
+ u8 *qe_mask = nor->params->qe_mask;
+ u8 sr[2] = {};
+ int ret;
+
+ if (!qe_mask[0] && !qe_mask[1])
+ return 0;
+
+ ret = spi_nor_read_sr1_and_sr2(nor, sr);
+ if (ret)
+ return ret;
+
+ if (sr[0] & qe_mask[0] || sr[1] & qe_mask[1])
+ return 0;
+
+ sr[0] |= qe_mask[0];
+ sr[1] |= qe_mask[1];
+
+ return spi_nor_write_sr1_and_sr2_and_check(nor, sr);
+}
+
/**
* spi_nor_erase_die() - Erase the entire die.
* @nor: pointer to 'struct spi_nor'.
@@ -1904,106 +1788,6 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
return ret;
}
-/**
- * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
- * Register 1.
- * @nor: pointer to a 'struct spi_nor'
- *
- * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
-{
- int ret;
-
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
- return 0;
-
- nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
-
- return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
-}
-
-/**
- * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
- * Register 2.
- * @nor: pointer to a 'struct spi_nor'.
- *
- * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
-{
- int ret;
-
- if (nor->flags & SNOR_F_NO_READ_CR)
- return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
-
- ret = spi_nor_read_cr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
- return 0;
-
- nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
-
- return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
-}
-
-/**
- * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
- * @nor: pointer to a 'struct spi_nor'
- *
- * Set the Quad Enable (QE) bit in the Status Register 2.
- *
- * This is one of the procedures to set the QE bit described in the SFDP
- * (JESD216 rev B) specification but no manufacturer using this procedure has
- * been identified yet, hence the name of the function.
- *
- * Return: 0 on success, -errno otherwise.
- */
-int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
-{
- u8 *sr2 = nor->bouncebuf;
- int ret;
- u8 sr2_written;
-
- /* Check current Quad Enable bit value. */
- ret = spi_nor_read_sr2(nor, sr2);
- if (ret)
- return ret;
- if (*sr2 & SR2_QUAD_EN_BIT7)
- return 0;
-
- /* Update the Quad Enable bit. */
- *sr2 |= SR2_QUAD_EN_BIT7;
-
- ret = spi_nor_write_sr2(nor, sr2);
- if (ret)
- return ret;
-
- sr2_written = *sr2;
-
- /* Read back and check it. */
- ret = spi_nor_read_sr2(nor, sr2);
- if (ret)
- return ret;
-
- if (*sr2 != sr2_written) {
- dev_dbg(nor->dev, "SR2: Read back test failed\n");
- return -EIO;
- }
-
- return 0;
-}
-
static const struct spi_nor_manufacturer *manufacturers[] = {
&spi_nor_atmel,
&spi_nor_eon,
@@ -2494,6 +2278,7 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
{
struct spi_nor_flash_parameter *params = nor->params;
unsigned int cap;
+ u8 opcode;
/* X-X-X modes are not supported yet, mask them all. */
*hwcaps &= ~SNOR_HWCAPS_X_X_X;
@@ -2525,14 +2310,14 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
*hwcaps &= ~BIT(cap);
}
- /* Some SPI controllers might not support CR read opcode. */
- if (!(nor->flags & SNOR_F_NO_READ_CR)) {
- struct spi_mem_op op = SPI_NOR_RDCR_OP(nor->bouncebuf);
-
+ /* Some SPI controllers might not support reading SR2 */
+ opcode = nor->params->opcodes.read_sr2;
+ if (opcode) {
+ struct spi_mem_op op = SPI_NOR_RDSR_OP(opcode, nor->bouncebuf, 1);
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
if (!spi_mem_supports_op(nor->spimem, &op))
- nor->flags |= SNOR_F_NO_READ_CR;
+ nor->params->opcodes.read_sr2 = 0;
}
}
@@ -3107,11 +2892,14 @@ static void spi_nor_init_default_params(struct spi_nor *nor)
const struct flash_info *info = nor->info;
struct device_node *np = spi_nor_get_flash_node(nor);
- params->quad_enable = spi_nor_sr2_bit1_quad_enable;
- params->otp.org = info->otp;
+ /* Default to 16-bit Read/Write Status commands */
+ params->opcodes.read_sr1 = SPINOR_OP_RDSR;
+ params->opcodes.read_sr2 = SPINOR_OP_RDCR;
+ params->opcodes.write_sr1_and_sr2 = SPINOR_OP_WRSR;
+ params->quad_enable = spi_nor_generic_quad_enable;
+ params->qe_mask[1] = BIT(1);
- /* Default to 16-bit Write Status (01h) Command */
- nor->flags |= SNOR_F_HAS_16BIT_SR;
+ params->otp.org = info->otp;
/* Set SPI NOR sizes. */
params->writesize = 1;
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 2cc0c80da3fa..7d43d3ba47ee 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -37,36 +37,18 @@
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_NO_DATA)
-#define SPI_NOR_RDSR_OP(buf) \
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), \
+#define SPI_NOR_RDSR_OP(opcode, buf, len) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
SPI_MEM_OP_NO_ADDR, \
SPI_MEM_OP_NO_DUMMY, \
- SPI_MEM_OP_DATA_IN(1, buf, 0))
+ SPI_MEM_OP_DATA_IN(len, buf, 0))
-#define SPI_NOR_WRSR_OP(buf, len) \
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), \
+#define SPI_NOR_WRSR_OP(opcode, buf, len) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
SPI_MEM_OP_NO_ADDR, \
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_DATA_OUT(len, buf, 0))
-#define SPI_NOR_RDSR2_OP(buf) \
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), \
- SPI_MEM_OP_NO_ADDR, \
- SPI_MEM_OP_NO_DUMMY, \
- SPI_MEM_OP_DATA_OUT(1, buf, 0))
-
-#define SPI_NOR_WRSR2_OP(buf) \
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), \
- SPI_MEM_OP_NO_ADDR, \
- SPI_MEM_OP_NO_DUMMY, \
- SPI_MEM_OP_DATA_OUT(1, buf, 0))
-
-#define SPI_NOR_RDCR_OP(buf) \
- SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), \
- SPI_MEM_OP_NO_ADDR, \
- SPI_MEM_OP_NO_DUMMY, \
- SPI_MEM_OP_DATA_IN(1, buf, 0))
-
#define SPI_NOR_EN4B_EX4B_OP(enable) \
SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B, 0), \
SPI_MEM_OP_NO_ADDR, \
@@ -129,8 +111,6 @@ enum spi_nor_option_flags {
SNOR_F_4B_OPCODES = BIT(3),
SNOR_F_HAS_4BAIT = BIT(4),
SNOR_F_HAS_LOCK = BIT(5),
- SNOR_F_HAS_16BIT_SR = BIT(6),
- SNOR_F_NO_READ_CR = BIT(7),
SNOR_F_HAS_SR_TB_BIT6 = BIT(8),
SNOR_F_HAS_4BIT_BP = BIT(9),
SNOR_F_HAS_SR_BP3_BIT6 = BIT(10),
@@ -345,9 +325,19 @@ struct spi_nor_otp {
* List of variable opcodes used by the chip.
*
* @die_erase: opcode for erasing a die, defaults to SPINOR_OP_CHIP_ERASE
+ * @read_sr1: opcode for reading SR1 alone
+ * @read_sr2: opcode for reading SR2 alone
+ * @write_sr1: opcode for writing SR1 alone
+ * @write_sr2: opcode for writing SR2 alone
+ * @write_sr1_and_sr2: opcode for writing SR1 then SR2 in one operation
*/
struct spi_nor_opcodes {
u8 die_erase;
+ u8 read_sr1;
+ u8 read_sr2;
+ u8 write_sr1;
+ u8 write_sr2;
+ u8 write_sr1_and_sr2;
};
/**
@@ -384,6 +374,7 @@ struct spi_nor_opcodes {
* @otp: SPI NOR OTP info.
* @set_octal_dtr: enables or disables SPI NOR octal DTR mode.
* @quad_enable: enables SPI NOR quad mode.
+ * @qe_mask: two bytes mask used to set/clear the QE bit
* @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
* @ready: (optional) flashes might use a different mechanism
* than reading the status register to indicate they
@@ -413,6 +404,7 @@ struct spi_nor_flash_parameter {
int (*set_octal_dtr)(struct spi_nor *nor, bool enable);
int (*quad_enable)(struct spi_nor *nor);
+ u8 qe_mask[2];
int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
int (*ready)(struct spi_nor *nor);
@@ -641,18 +633,15 @@ int spi_nor_wait_till_ready(struct spi_nor *nor);
int spi_nor_global_block_unlock(struct spi_nor *nor);
int spi_nor_prep_and_lock(struct spi_nor *nor);
void spi_nor_unlock_and_unprep(struct spi_nor *nor);
-int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
-int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
-int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
enum spi_nor_protocol reg_proto);
-int spi_nor_read_sr(struct spi_nor *nor, u8 *sr);
int spi_nor_sr_ready(struct spi_nor *nor);
-int spi_nor_read_cr(struct spi_nor *nor, u8 *cr);
-int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len);
-int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1);
-int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr);
-int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs);
+int spi_nor_read_sr1(struct spi_nor *nor, u8 *sr1);
+int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2);
+int spi_nor_read_sr1_and_sr2(struct spi_nor *nor, u8 *sr);
+int spi_nor_write_sr1(struct spi_nor *nor, const u8 *sr1);
+int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2);
+int spi_nor_write_sr1_and_sr2_and_check(struct spi_nor *nor, const u8 *sr);
ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
u8 *buf);
diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
index ef6f0ffcd6bb..512825c3fc85 100644
--- a/drivers/mtd/spi-nor/debugfs.c
+++ b/drivers/mtd/spi-nor/debugfs.c
@@ -19,8 +19,6 @@ static const char *const snor_f_names[] = {
SNOR_F_NAME(4B_OPCODES),
SNOR_F_NAME(HAS_4BAIT),
SNOR_F_NAME(HAS_LOCK),
- SNOR_F_NAME(HAS_16BIT_SR),
- SNOR_F_NAME(NO_READ_CR),
SNOR_F_NAME(HAS_SR_TB_BIT6),
SNOR_F_NAME(HAS_4BIT_BP),
SNOR_F_NAME(HAS_SR_BP3_BIT6),
diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
index ef1edd0add70..4070a692e968 100644
--- a/drivers/mtd/spi-nor/gigadevice.c
+++ b/drivers/mtd/spi-nor/gigadevice.c
@@ -23,8 +23,10 @@ gd25q256_post_bfpt(struct spi_nor *nor,
* GD25Q256E | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR
*/
if (bfpt_header->major == SFDP_JESD216_MAJOR &&
- bfpt_header->minor == SFDP_JESD216_MINOR)
- nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ bfpt_header->minor == SFDP_JESD216_MINOR) {
+ nor->params->qe_mask[0] = BIT(6);
+ nor->params->qe_mask[1] = 0;
+ }
return 0;
}
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index 18d9a00aa22e..04db42b5141e 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -131,7 +131,8 @@ static const struct flash_info issi_nor_parts[] = {
static void issi_nor_default_init(struct spi_nor *nor)
{
- nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ nor->params->qe_mask[0] = BIT(6);
+ nor->params->qe_mask[1] = 0;
}
static const struct spi_nor_fixups issi_fixups = {
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index e97f5cbd9aad..55612237c1ef 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -65,11 +65,12 @@ mx25l3255e_late_init_fixups(struct spi_nor *nor)
/*
* SFDP of MX25L3255E is JESD216, which does not include the Quad
- * Enable bit Requirement in BFPT. As a result, during BFPT parsing,
- * the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.
- * Therefore, it is necessary to correct this setting by late_init.
+ * Enable bit Requirement in BFPT. As a result, during BFPT parsing
+ * the quad_enable mask is reset. Therefore, it is necessary to
+ * correct this setting by late_init.
*/
- params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ params->qe_mask[0] = BIT(6);
+ params->qe_mask[1] = 0;
/*
* In addition, MX25L3255E also supports 1-4-4 page program in 3-byte
@@ -314,7 +315,8 @@ static int macronix_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
static void macronix_nor_default_init(struct spi_nor *nor)
{
- nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ nor->params->qe_mask[0] = BIT(6);
+ nor->params->qe_mask[1] = 0;
}
static int macronix_nor_late_init(struct spi_nor *nor)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 031cf887318c..344539d2a36a 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -229,7 +229,7 @@ static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt)
{
- nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+ nor->params->opcodes.write_sr1 = 0;
return 0;
}
@@ -633,7 +633,7 @@ static int micron_st_nor_ready(struct spi_nor *nor)
static void micron_st_nor_default_init(struct spi_nor *nor)
{
nor->flags |= SNOR_F_HAS_LOCK;
- nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+ nor->params->opcodes.write_sr1 = 0;
nor->params->quad_enable = NULL;
}
diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
index 7d0b145d78d8..1eeb33a20091 100644
--- a/drivers/mtd/spi-nor/otp.c
+++ b/drivers/mtd/spi-nor/otp.c
@@ -175,24 +175,24 @@ static int spi_nor_otp_lock_bit_cr(unsigned int region)
*/
int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigned int region)
{
- u8 *cr = nor->bouncebuf;
int ret, lock_bit;
+ u8 sr[2];
lock_bit = spi_nor_otp_lock_bit_cr(region);
if (lock_bit < 0)
return lock_bit;
- ret = spi_nor_read_cr(nor, cr);
+ ret = spi_nor_read_sr1_and_sr2(nor, sr);
if (ret)
return ret;
/* no need to write the register if region is already locked */
- if (cr[0] & lock_bit)
+ if (sr[1] & lock_bit)
return 0;
- cr[0] |= lock_bit;
+ sr[1] |= lock_bit;
- return spi_nor_write_16bit_cr_and_check(nor, cr[0]);
+ return spi_nor_write_sr1_and_sr2_and_check(nor, sr);
}
/**
@@ -207,18 +207,18 @@ int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigned int region)
*/
int spi_nor_otp_is_locked_sr2(struct spi_nor *nor, unsigned int region)
{
- u8 *cr = nor->bouncebuf;
int ret, lock_bit;
+ u8 sr2;
lock_bit = spi_nor_otp_lock_bit_cr(region);
if (lock_bit < 0)
return lock_bit;
- ret = spi_nor_read_cr(nor, cr);
+ ret = spi_nor_read_sr2(nor, &sr2);
if (ret)
return ret;
- return cr[0] & lock_bit;
+ return sr2 & lock_bit;
}
static loff_t spi_nor_otp_region_start(const struct spi_nor *nor, unsigned int region)
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index 526763c79f55..1d799f02b8e5 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -561,10 +561,21 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
val >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
params->page_size = 1U << val;
+ /*
+ * The standard declares various read and write status methods, some of
+ * them will be overloaded based on the QER field.
+ */
+ params->opcodes.read_sr1 = SPINOR_OP_RDSR;
+ params->opcodes.read_sr2 = SPINOR_OP_RDCR;
+ params->opcodes.write_sr1 = SPINOR_OP_WRSR;
+ params->opcodes.write_sr1_and_sr2 = SPINOR_OP_WRSR;
+
+ params->qe_mask[0] = 0;
+ params->qe_mask[1] = 0;
+
/* Quad Enable Requirements. */
switch (bfpt.dwords[SFDP_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
case BFPT_DWORD15_QER_NONE:
- params->quad_enable = NULL;
break;
case BFPT_DWORD15_QER_SR2_BIT1_NO_1B_WR:
@@ -572,23 +583,28 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
* Writing only one byte to the Status Register has the
* side-effect of clearing Status Register 2.
*/
+ fallthrough;
case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
/*
* Read Configuration Register (35h) instruction is not
- * supported.
+ * supported. 16-bit writes expected.
*/
- nor->flags |= SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR;
- params->quad_enable = spi_nor_sr2_bit1_quad_enable;
+ params->opcodes.read_sr2 = 0;
+ params->opcodes.write_sr1 = 0;
+ params->qe_mask[1] = BIT(1);
break;
case BFPT_DWORD15_QER_SR1_BIT6:
- nor->flags &= ~SNOR_F_HAS_16BIT_SR;
- params->quad_enable = spi_nor_sr1_bit6_quad_enable;
+ params->opcodes.read_sr2 = 0;
+ params->opcodes.write_sr1_and_sr2 = 0;
+ params->qe_mask[0] = BIT(6);
break;
case BFPT_DWORD15_QER_SR2_BIT7:
- nor->flags &= ~SNOR_F_HAS_16BIT_SR;
- params->quad_enable = spi_nor_sr2_bit7_quad_enable;
+ params->opcodes.read_sr2 = SPINOR_OP_RDSR2;
+ params->opcodes.write_sr1_and_sr2 = 0;
+ params->opcodes.write_sr2 = SPINOR_OP_WRSR2;
+ params->qe_mask[1] = BIT(7);
break;
case BFPT_DWORD15_QER_SR2_BIT1:
@@ -598,9 +614,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
* Register 2, so let's be cautious and keep the default
* assumption of a 16-bit Write Status (01h) command.
*/
- nor->flags |= SNOR_F_HAS_16BIT_SR;
-
- params->quad_enable = spi_nor_sr2_bit1_quad_enable;
+ params->opcodes.write_sr1 = 0;
+ params->qe_mask[1] = BIT(1);
break;
default:
@@ -608,6 +623,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
break;
}
+ /* opcodes sanity check */
+ WARN_ON(!params->opcodes.read_sr1 ||
+ (!params->opcodes.write_sr1 && !params->opcodes.write_sr1_and_sr2));
+
dword = bfpt.dwords[SFDP_DWORD(16)] & BFPT_DWORD16_4B_ADDR_MODE_MASK;
if (SFDP_MASK_CHECK(dword, BFPT_DWORD16_4B_ADDR_MODE_BRWR))
params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr;
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 2a8238c707e1..ca2703a5a338 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -399,8 +399,9 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
nor->bouncebuf);
bool is3byte, is4byte;
int ret;
+ u8 sr;
- ret = spi_nor_read_sr(nor, &nor->bouncebuf[1]);
+ ret = spi_nor_read_sr1(nor, &sr);
if (ret)
return ret;
@@ -408,7 +409,7 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
if (ret)
return ret;
- is3byte = (nor->bouncebuf[0] == nor->bouncebuf[1]);
+ is3byte = (nor->bouncebuf[0] == sr);
op = (struct spi_mem_op)
CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0,
@@ -417,7 +418,7 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
if (ret)
return ret;
- is4byte = (nor->bouncebuf[0] == nor->bouncebuf[1]);
+ is4byte = (nor->bouncebuf[0] == sr);
if (is3byte == is4byte)
return -EIO;
@@ -1103,13 +1104,14 @@ static const struct flash_info spansion_nor_parts[] = {
static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
{
int ret;
+ u8 sr;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1(nor, &sr);
if (ret)
return ret;
- if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
- if (nor->bouncebuf[0] & SR_E_ERR)
+ if (sr & (SR_E_ERR | SR_P_ERR)) {
+ if (sr & SR_E_ERR)
dev_err(nor->dev, "Erase Error occurred\n");
else
dev_err(nor->dev, "Programming Error occurred\n");
@@ -1129,7 +1131,7 @@ static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
return -EIO;
}
- return !(nor->bouncebuf[0] & SR_WIP);
+ return !(sr & SR_WIP);
}
static int spansion_nor_late_init(struct spi_nor *nor)
diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
index db02c14ba16f..77a0bc41d4e5 100644
--- a/drivers/mtd/spi-nor/sst.c
+++ b/drivers/mtd/spi-nor/sst.c
@@ -21,16 +21,17 @@ static int sst26vf_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len)
static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
{
int ret;
+ u8 cr;
/* We only support unlocking the entire flash array. */
if (ofs != 0 || len != nor->params->size)
return -EINVAL;
- ret = spi_nor_read_cr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr2(nor, &cr);
if (ret)
return ret;
- if (!(nor->bouncebuf[0] & SST26VF_CR_BPNV)) {
+ if (!(cr & SST26VF_CR_BPNV)) {
dev_dbg(nor->dev, "Any block has been permanently locked\n");
return -EINVAL;
}
diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c
index 235070b215d1..b7b291e15917 100644
--- a/drivers/mtd/spi-nor/swp.c
+++ b/drivers/mtd/spi-nor/swp.c
@@ -36,7 +36,7 @@ static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor)
static u8 spi_nor_get_sr_cmp_mask(struct spi_nor *nor)
{
- if (!(nor->flags & SNOR_F_NO_READ_CR) &&
+ if (nor->params->opcodes.read_sr2 &&
nor->flags & SNOR_F_HAS_SR2_CMP_BIT6)
return SR2_CMP_BIT6;
else
@@ -207,17 +207,9 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u8 *sr)
if (!sr) {
- if (spi_nor_read_sr(nor, nor->bouncebuf))
+ if (spi_nor_read_sr1_and_sr2(nor, sr_cr))
return;
- sr_cr[0] = nor->bouncebuf[0];
-
- if (!(nor->flags & SNOR_F_NO_READ_CR)) {
- if (spi_nor_read_cr(nor, nor->bouncebuf))
- return;
- }
-
- sr_cr[1] = nor->bouncebuf[0];
sr = sr_cr;
}
@@ -273,20 +265,10 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)
int ret;
u8 pow;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1_and_sr2(nor, status_old);
if (ret)
return ret;
- status_old[0] = nor->bouncebuf[0];
-
- if (!(nor->flags & SNOR_F_NO_READ_CR)) {
- ret = spi_nor_read_cr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- status_old[1] = nor->bouncebuf[0];
- }
-
/* If nothing in our range is unlocked, we don't need to do anything */
if (spi_nor_is_locked_sr(nor, ofs, len, status_old))
return 0;
@@ -378,10 +360,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)
(ofs_old < ofs_new || (ofs_new + len_new) < (ofs_old + len_old)))
return -EINVAL;
- if (nor->flags & SNOR_F_NO_READ_CR)
- ret = spi_nor_write_sr_and_check(nor, best_status_new[0]);
- else
- ret = spi_nor_write_sr_cr_and_check(nor, best_status_new);
+ ret = spi_nor_write_sr1_and_sr2_and_check(nor, best_status_new);
if (ret)
return ret;
@@ -409,20 +388,10 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
int ret;
u8 pow;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1_and_sr2(nor, status_old);
if (ret)
return ret;
- status_old[0] = nor->bouncebuf[0];
-
- if (!(nor->flags & SNOR_F_NO_READ_CR)) {
- ret = spi_nor_read_cr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- status_old[1] = nor->bouncebuf[0];
- }
-
/* If nothing in our range is locked, we don't need to do anything */
if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old))
return 0;
@@ -512,10 +481,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
(ofs_new < ofs_old || (ofs_old + len_old) < (ofs_new + len_new)))
return -EINVAL;
- if (nor->flags & SNOR_F_NO_READ_CR)
- ret = spi_nor_write_sr_and_check(nor, best_status_new[0]);
- else
- ret = spi_nor_write_sr_cr_and_check(nor, best_status_new);
+ ret = spi_nor_write_sr1_and_sr2_and_check(nor, best_status_new);
if (ret)
return ret;
@@ -536,20 +502,10 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, u64 len)
u8 sr_cr[2] = {};
int ret;
- ret = spi_nor_read_sr(nor, nor->bouncebuf);
+ ret = spi_nor_read_sr1_and_sr2(nor, sr_cr);
if (ret)
return ret;
- sr_cr[0] = nor->bouncebuf[0];
-
- if (!(nor->flags & SNOR_F_NO_READ_CR)) {
- ret = spi_nor_read_cr(nor, nor->bouncebuf);
- if (ret)
- return ret;
-
- sr_cr[1] = nor->bouncebuf[0];
- }
-
return spi_nor_is_locked_sr(nor, ofs, len, sr_cr);
}
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 593429bd6cdf..01a693033448 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -520,12 +520,12 @@ static int winbond_nor_late_init(struct spi_nor *nor)
* been to declare CR reads as unsupported, whereas the Jedec
* specification doesn't clearly state that. In practice, all these
* chips do support reading back the CR, which is needed for SWP support,
- * so make sure that capability remains enabled (needed for SWP).
+ * so make sure that capability remains enabled.
* In practice, only exclude the old W25X family (JEDEC ID: EF 30 xx)
* which actually does not support this feature.
*/
if (nor->id[1] > 0x30)
- nor->flags &= ~SNOR_F_NO_READ_CR;
+ params->opcodes.read_sr2 = SPINOR_OP_RDCR;
/*
* Winbond has reused many IDs, up to four times at this
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 4b92494827b1..f0b5a1989881 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -113,20 +113,16 @@
#define SR_E_ERR BIT(5)
#define SR_P_ERR BIT(6)
-#define SR1_QUAD_EN_BIT6 BIT(6)
-
#define SR_BP_SHIFT 2
/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
/* Status Register 2 bits. */
-#define SR2_QUAD_EN_BIT1 BIT(1)
#define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */
#define SR2_LB2 BIT(4) /* Security Register Lock Bit 2 */
#define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */
#define SR2_CMP_BIT6 BIT(6)
-#define SR2_QUAD_EN_BIT7 BIT(7)
/* Supported SPI protocols */
#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 04/23] mtd: spi-nor: Add support for the new JESD216 rev F QER field
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
Revision F of the JEDEC JESD216 standard includes yet another
supported setting in the QER 3-bit bitfield: 110b.
This setting implies that the QE bit is bit 1 of SR2 (which is an
already supported case) but this time it makes it very clear that both
reading and writing to SR2 is supported, but not with the usual
opcodes. The write operation uses an alternate WRSR2 opcode:
0x31 (instead of 0x3E) and both the reads and writes manipulate a single
register at a time.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/sfdp.c | 6 ++++++
drivers/mtd/spi-nor/sfdp.h | 8 ++++++++
include/linux/mtd/spi-nor.h | 1 +
3 files changed, 15 insertions(+)
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index 1d799f02b8e5..285ac781fba8 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -618,6 +618,12 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
params->qe_mask[1] = BIT(1);
break;
+ case BFPT_DWORD15_QER_SR2_BIT1_1B:
+ params->qe_mask[1] = BIT(1);
+ params->opcodes.write_sr1_and_sr2 = 0;
+ params->opcodes.write_sr2 = SPINOR_OP_WRSR2_ALT;
+ break;
+
default:
dev_dbg(nor->dev, "BFPT QER reserved value used\n");
break;
diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h
index d976c6c9a4ad..e8ed814c6530 100644
--- a/drivers/mtd/spi-nor/sfdp.h
+++ b/drivers/mtd/spi-nor/sfdp.h
@@ -12,6 +12,7 @@
#define SFDP_JESD216_MINOR 0
#define SFDP_JESD216A_MINOR 5
#define SFDP_JESD216B_MINOR 6
+#define SFDP_JESD216F_MINOR 10
/* SFDP DWORDS are indexed from 1 but C arrays are indexed from 0. */
#define SFDP_DWORD(i) ((i) - 1)
@@ -81,6 +82,12 @@ struct sfdp_bfpt {
* instruction 35h. QE is set via Write Status instruction 01h with
* two data bytes where bit 1 of the second byte is one.
* [...]
+ * (from JESD216 rev F)
+ * - 110b: QE is bit 1 of status register 2. Status register 1 is read using
+ * Read Status instruction 05h. Status register2 is read using
+ * instruction 35h, and status register 3 is read using instruction 15h.
+ * QE is set via Write Status Register instruction 31h with one data
+ * byte.
*/
#define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
@@ -89,6 +96,7 @@ struct sfdp_bfpt {
#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
+#define BFPT_DWORD15_QER_SR2_BIT1_1B (0x6UL << 20) /* Winbond */
#define BFPT_DWORD16_EN4B_MASK GENMASK(31, 24)
#define BFPT_DWORD16_EN4B_ALWAYS_4B BIT(30)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index f0b5a1989881..3a55d76ea77d 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -25,6 +25,7 @@
#define SPINOR_OP_WRSR 0x01 /* Write status register 1 */
#define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
#define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
+#define SPINOR_OP_WRSR2_ALT 0x31 /* Write status register 2 (alternative) */
#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 04/23] mtd: spi-nor: Add support for the new JESD216 rev F QER field
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
Revision F of the JEDEC JESD216 standard includes yet another
supported setting in the QER 3-bit bitfield: 110b.
This setting implies that the QE bit is bit 1 of SR2 (which is an
already supported case) but this time it makes it very clear that both
reading and writing to SR2 is supported, but not with the usual
opcodes. The write operation uses an alternate WRSR2 opcode:
0x31 (instead of 0x3E) and both the reads and writes manipulate a single
register at a time.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/sfdp.c | 6 ++++++
drivers/mtd/spi-nor/sfdp.h | 8 ++++++++
include/linux/mtd/spi-nor.h | 1 +
3 files changed, 15 insertions(+)
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index 1d799f02b8e5..285ac781fba8 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -618,6 +618,12 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
params->qe_mask[1] = BIT(1);
break;
+ case BFPT_DWORD15_QER_SR2_BIT1_1B:
+ params->qe_mask[1] = BIT(1);
+ params->opcodes.write_sr1_and_sr2 = 0;
+ params->opcodes.write_sr2 = SPINOR_OP_WRSR2_ALT;
+ break;
+
default:
dev_dbg(nor->dev, "BFPT QER reserved value used\n");
break;
diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h
index d976c6c9a4ad..e8ed814c6530 100644
--- a/drivers/mtd/spi-nor/sfdp.h
+++ b/drivers/mtd/spi-nor/sfdp.h
@@ -12,6 +12,7 @@
#define SFDP_JESD216_MINOR 0
#define SFDP_JESD216A_MINOR 5
#define SFDP_JESD216B_MINOR 6
+#define SFDP_JESD216F_MINOR 10
/* SFDP DWORDS are indexed from 1 but C arrays are indexed from 0. */
#define SFDP_DWORD(i) ((i) - 1)
@@ -81,6 +82,12 @@ struct sfdp_bfpt {
* instruction 35h. QE is set via Write Status instruction 01h with
* two data bytes where bit 1 of the second byte is one.
* [...]
+ * (from JESD216 rev F)
+ * - 110b: QE is bit 1 of status register 2. Status register 1 is read using
+ * Read Status instruction 05h. Status register2 is read using
+ * instruction 35h, and status register 3 is read using instruction 15h.
+ * QE is set via Write Status Register instruction 31h with one data
+ * byte.
*/
#define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
@@ -89,6 +96,7 @@ struct sfdp_bfpt {
#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
+#define BFPT_DWORD15_QER_SR2_BIT1_1B (0x6UL << 20) /* Winbond */
#define BFPT_DWORD16_EN4B_MASK GENMASK(31, 24)
#define BFPT_DWORD16_EN4B_ALWAYS_4B BIT(30)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index f0b5a1989881..3a55d76ea77d 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -25,6 +25,7 @@
#define SPINOR_OP_WRSR 0x01 /* Write status register 1 */
#define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
#define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
+#define SPINOR_OP_WRSR2_ALT 0x31 /* Write status register 2 (alternative) */
#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 05/23] mtd: spi-nor: Create the concept of fixup table with match function
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
Manufacturer ID tables increase and fixup() hooks proliferate. Having
one possible structure per chip was fine until the fixups started being
more and more common and needed, to some extend due to ID reuses. Mixing
fixups and chips becomes hard and requires extra helpers to sort which
ones are needed for a given chip, which every time this happens requires
a lot of rework.
Replace the two-level fixup association (a manufacturer wide hook and a
per flash_info hook) with a per-manufacturer list of fixups that can be
looked up by flash ID and/or match function.
The match logic works as follows:
- If there is an ID, it must match
- If there is a match function, it must match (cumulative)
- If there is no identifier (no ID nor any match function), it's a
catch-all entry typically used for flagging manufacturer fixups.
Suggested-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/atmel.c | 23 ++++++-----
drivers/mtd/spi-nor/core.c | 82 ++++++++++++++++++++++++++++------------
drivers/mtd/spi-nor/core.h | 23 +++++++++--
drivers/mtd/spi-nor/everspin.c | 7 +++-
drivers/mtd/spi-nor/gigadevice.c | 7 +++-
drivers/mtd/spi-nor/issi.c | 22 ++++++++---
drivers/mtd/spi-nor/macronix.c | 23 ++++++-----
drivers/mtd/spi-nor/micron-st.c | 43 +++++++++++++++------
drivers/mtd/spi-nor/sfdp.c | 56 ++++++++++++++++++---------
drivers/mtd/spi-nor/spansion.c | 41 +++++++++++---------
drivers/mtd/spi-nor/sst.c | 11 ++++--
drivers/mtd/spi-nor/winbond.c | 17 ++++++---
12 files changed, 247 insertions(+), 108 deletions(-)
diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
index 8741c0bda497..bccc702a2c4a 100644
--- a/drivers/mtd/spi-nor/atmel.c
+++ b/drivers/mtd/spi-nor/atmel.c
@@ -194,47 +194,40 @@ static const struct flash_info atmel_nor_parts[] = {
.size = SZ_512K,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
- .fixups = &atmel_nor_global_protection_fixups,
}, {
.id = SNOR_ID(0x1f, 0x45, 0x01),
.name = "at26df081a",
.size = SZ_1M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
- .fixups = &atmel_nor_global_protection_fixups
}, {
.id = SNOR_ID(0x1f, 0x46, 0x01),
.name = "at26df161a",
.size = SZ_2M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
- .fixups = &atmel_nor_global_protection_fixups
}, {
.id = SNOR_ID(0x1f, 0x47, 0x00),
.name = "at25df321",
.size = SZ_4M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
- .fixups = &atmel_nor_global_protection_fixups
}, {
.id = SNOR_ID(0x1f, 0x47, 0x01),
.name = "at25df321a",
.size = SZ_4M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
- .fixups = &atmel_nor_global_protection_fixups
}, {
.id = SNOR_ID(0x1f, 0x47, 0x08),
.name = "at25ff321a",
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
- .fixups = &atmel_nor_global_protection_fixups
}, {
.id = SNOR_ID(0x1f, 0x48, 0x00),
.name = "at25df641",
.size = SZ_8M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
- .fixups = &atmel_nor_global_protection_fixups
}, {
.id = SNOR_ID(0x1f, 0x66, 0x01),
.name = "at25fs010",
@@ -242,14 +235,12 @@ static const struct flash_info atmel_nor_parts[] = {
.size = SZ_128K,
.flags = SPI_NOR_HAS_LOCK,
.no_sfdp_flags = SECT_4K,
- .fixups = &at25fs_nor_fixups
}, {
.id = SNOR_ID(0x1f, 0x66, 0x04),
.name = "at25fs040",
.size = SZ_512K,
.flags = SPI_NOR_HAS_LOCK,
.no_sfdp_flags = SECT_4K,
- .fixups = &at25fs_nor_fixups
}, {
.id = SNOR_ID(0x1f, 0x87, 0x01),
.size = SZ_4M,
@@ -257,8 +248,22 @@ static const struct flash_info atmel_nor_parts[] = {
},
};
+static const struct spi_nor_fixup atmel_fixups[] = {
+ { .id = SNOR_ID(0x1f, 0x44, 0x01), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x45, 0x01), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x46, 0x01), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x47, 0x00), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x47, 0x01), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x47, 0x08), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x48, 0x00), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x66, 0x01), .fixups = &at25fs_nor_fixups },
+ { .id = SNOR_ID(0x1f, 0x66, 0x04), .fixups = &at25fs_nor_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_atmel = {
.name = "atmel",
.parts = atmel_nor_parts,
.nparts = ARRAY_SIZE(atmel_nor_parts),
+ .fixups = atmel_fixups,
+ .nfixups = ARRAY_SIZE(atmel_fixups),
};
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index ac7812562047..3a611283a9e6 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2367,19 +2367,24 @@ int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt)
{
+ const struct spi_nor_fixup *fixups;
int ret;
+ unsigned int i;
- if (nor->manufacturer && nor->manufacturer->fixups &&
- nor->manufacturer->fixups->post_bfpt) {
- ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,
- bfpt);
- if (ret)
- return ret;
+ if (!nor->manufacturer || !nor->manufacturer->fixups)
+ return 0;
+
+ fixups = nor->manufacturer->fixups;
+
+ for (i = 0; i < nor->manufacturer->nfixups; i++) {
+ if (fixups[i].fixups->post_bfpt &&
+ spi_nor_fixup_match(nor, &fixups[i])) {
+ ret = fixups[i].fixups->post_bfpt(nor, bfpt_header, bfpt);
+ if (ret)
+ return ret;
+ }
}
- if (nor->info->fixups && nor->info->fixups->post_bfpt)
- return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt);
-
return 0;
}
@@ -2636,6 +2641,26 @@ static int spi_nor_setup(struct spi_nor *nor,
return spi_nor_set_addr_nbytes(nor);
}
+bool spi_nor_fixup_match(const struct spi_nor *nor,
+ const struct spi_nor_fixup *fixup)
+{
+ const struct spi_nor_id *id = nor->info ? nor->info->id : NULL;
+
+ /* Filter by ID first, if available */
+ if (fixup->id) {
+ if (!id || fixup->id->len > id->len ||
+ memcmp(id->bytes, fixup->id->bytes, fixup->id->len))
+ return false;
+ }
+
+ /* Further filter with the match callback, if provided */
+ if (fixup->match)
+ return fixup->match(nor);
+
+ /* Either there was an ID and it matched, or it is a catch-all entry */
+ return true;
+}
+
/**
* spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
* settings based on MFR register and ->default_init() hook.
@@ -2643,12 +2668,19 @@ static int spi_nor_setup(struct spi_nor *nor,
*/
static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
{
- if (nor->manufacturer && nor->manufacturer->fixups &&
- nor->manufacturer->fixups->default_init)
- nor->manufacturer->fixups->default_init(nor);
+ const struct spi_nor_fixup *fixups;
+ unsigned int i;
- if (nor->info->fixups && nor->info->fixups->default_init)
- nor->info->fixups->default_init(nor);
+ if (!nor->manufacturer || !nor->manufacturer->fixups)
+ return;
+
+ fixups = nor->manufacturer->fixups;
+
+ for (i = 0; i < nor->manufacturer->nfixups; i++) {
+ if (fixups[i].fixups->default_init &&
+ spi_nor_fixup_match(nor, &fixups[i]))
+ fixups[i].fixups->default_init(nor);
+ }
}
/**
@@ -2797,22 +2829,24 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor)
static int spi_nor_late_init_params(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = nor->params;
+ const struct spi_nor_fixup *fixups;
+ unsigned int i;
int ret;
/* Needed by some late_init hooks */
spi_nor_init_flags(nor);
- if (nor->manufacturer && nor->manufacturer->fixups &&
- nor->manufacturer->fixups->late_init) {
- ret = nor->manufacturer->fixups->late_init(nor);
- if (ret)
- return ret;
- }
+ if (nor->manufacturer && nor->manufacturer->fixups) {
+ fixups = nor->manufacturer->fixups;
- if (nor->info->fixups && nor->info->fixups->late_init) {
- ret = nor->info->fixups->late_init(nor);
- if (ret)
- return ret;
+ for (i = 0; i < nor->manufacturer->nfixups; i++) {
+ if (fixups[i].fixups->late_init &&
+ spi_nor_fixup_match(nor, &fixups[i])) {
+ ret = fixups[i].fixups->late_init(nor);
+ if (ret)
+ return ret;
+ }
+ }
}
if (!nor->params->opcodes.die_erase)
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 7d43d3ba47ee..b650778a10de 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -445,6 +445,19 @@ struct spi_nor_fixups {
int (*late_init)(struct spi_nor *nor);
};
+/**
+ * struct spi_nor_fixup - SPI NOR fixup registration.
+ * @id: (optional) flash ID this fixup applies to, may only match the
+ * ID prefix, eg. just the first few bytes to match a whole family
+ * @match: (optional) custom match function (can be used together with @id)
+ * @fixups: the fixup hooks to apply when this entry matches
+ */
+struct spi_nor_fixup {
+ const struct spi_nor_id *id;
+ bool (*match)(const struct spi_nor *nor);
+ const struct spi_nor_fixups *fixups;
+};
+
/**
* struct spi_nor_id - SPI NOR flash ID.
*
@@ -560,7 +573,6 @@ struct flash_info {
u8 mfr_flags;
const struct spi_nor_otp_organization *otp;
- const struct spi_nor_fixups *fixups;
};
#define SNOR_ID(...) \
@@ -582,13 +594,16 @@ struct flash_info {
* @name: manufacturer name
* @parts: array of parts supported by this manufacturer
* @nparts: number of entries in the parts array
- * @fixups: hooks called at various points in time during spi_nor_scan()
+ * @fixups: list of fixups, each matched by ID (or a custom match function),
+ * applied to any part of this manufacturer.
+ * @nfixups: number of entries in the fixups array
*/
struct spi_nor_manufacturer {
const char *name;
const struct flash_info *parts;
unsigned int nparts;
- const struct spi_nor_fixups *fixups;
+ const struct spi_nor_fixup *fixups;
+ unsigned int nfixups;
};
/**
@@ -619,6 +634,8 @@ extern const struct spi_nor_manufacturer spi_nor_xmc;
extern const struct attribute_group *spi_nor_sysfs_groups[];
+bool spi_nor_fixup_match(const struct spi_nor *nor,
+ const struct spi_nor_fixup *fixup);
void spi_nor_spimem_setup_op(const struct spi_nor *nor,
struct spi_mem_op *op,
const enum spi_nor_protocol proto);
diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c
index add37104d673..864dffba0e9c 100644
--- a/drivers/mtd/spi-nor/everspin.c
+++ b/drivers/mtd/spi-nor/everspin.c
@@ -44,9 +44,14 @@ static const struct spi_nor_fixups everspin_nor_fixups = {
.default_init = everspin_nor_default_init,
};
+static const struct spi_nor_fixup everspin_fixups[] = {
+ { .fixups = &everspin_nor_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_everspin = {
.name = "everspin",
.parts = everspin_nor_parts,
.nparts = ARRAY_SIZE(everspin_nor_parts),
- .fixups = &everspin_nor_fixups,
+ .fixups = everspin_fixups,
+ .nfixups = ARRAY_SIZE(everspin_fixups),
};
diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
index 4070a692e968..f76fd0dedd0a 100644
--- a/drivers/mtd/spi-nor/gigadevice.c
+++ b/drivers/mtd/spi-nor/gigadevice.c
@@ -64,7 +64,6 @@ static const struct flash_info gigadevice_nor_parts[] = {
.id = SNOR_ID(0xc8, 0x40, 0x19),
.name = "gd25q256",
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6,
- .fixups = &gd25q256_fixups,
.fixup_flags = SPI_NOR_4B_OPCODES,
}, {
.id = SNOR_ID(0xc8, 0x60, 0x16),
@@ -87,8 +86,14 @@ static const struct flash_info gigadevice_nor_parts[] = {
},
};
+static const struct spi_nor_fixup gigadevice_fixups[] = {
+ { .id = SNOR_ID(0xc8, 0x40, 0x19), .fixups = &gd25q256_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_gigadevice = {
.name = "gigadevice",
.parts = gigadevice_nor_parts,
.nparts = ARRAY_SIZE(gigadevice_nor_parts),
+ .fixups = gigadevice_fixups,
+ .nfixups = ARRAY_SIZE(gigadevice_fixups),
};
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index 04db42b5141e..4842f8acd074 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -52,13 +52,11 @@ static const struct flash_info issi_nor_parts[] = {
.sector_size = SZ_32K,
.size = SZ_64K,
.no_sfdp_flags = SECT_4K,
- .fixups = &pm25lv_nor_fixups
}, {
.name = "pm25lv010",
.sector_size = SZ_32K,
.size = SZ_128K,
.no_sfdp_flags = SECT_4K,
- .fixups = &pm25lv_nor_fixups
}, {
.id = SNOR_ID(0x7f, 0x9d, 0x20),
.name = "is25cd512",
@@ -103,7 +101,6 @@ static const struct flash_info issi_nor_parts[] = {
}, {
.id = SNOR_ID(0x9d, 0x60, 0x19),
.name = "is25lp256",
- .fixups = &is25lp256_fixups,
.fixup_flags = SPI_NOR_4B_OPCODES,
}, {
.id = SNOR_ID(0x9d, 0x70, 0x16),
@@ -124,7 +121,6 @@ static const struct flash_info issi_nor_parts[] = {
.id = SNOR_ID(0x9d, 0x70, 0x19),
.name = "is25wp256",
.flags = SPI_NOR_QUAD_PP,
- .fixups = &is25lp256_fixups,
.fixup_flags = SPI_NOR_4B_OPCODES,
}
};
@@ -139,9 +135,25 @@ static const struct spi_nor_fixups issi_fixups = {
.default_init = issi_nor_default_init,
};
+/* PM25LV parts have no JEDEC ID and are likely matched by name */
+static bool issi_pm25lv_match(const struct spi_nor *nor)
+{
+ const char *name = nor->info ? nor->info->name : NULL;
+
+ return name && !strncmp(name, "pm25lv", 6);
+}
+
+static const struct spi_nor_fixup issi_fixup_list[] = {
+ { .fixups = &issi_fixups },
+ { .match = issi_pm25lv_match, .fixups = &pm25lv_nor_fixups },
+ { .id = SNOR_ID(0x9d, 0x60, 0x19), .fixups = &is25lp256_fixups },
+ { .id = SNOR_ID(0x9d, 0x70, 0x19), .fixups = &is25lp256_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_issi = {
.name = "issi",
.parts = issi_nor_parts,
.nparts = ARRAY_SIZE(issi_nor_parts),
- .fixups = &issi_fixups,
+ .fixups = issi_fixup_list,
+ .nfixups = ARRAY_SIZE(issi_fixup_list),
};
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index 55612237c1ef..04b431bf5f13 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -137,20 +137,16 @@ static const struct flash_info macronix_nor_parts[] = {
}, {
/* MX25L25635E, MX25L25645G */
.id = SNOR_ID(0xc2, 0x20, 0x19),
- .fixups = &mx25l25635_fixups
}, {
/* MX66L51235F */
.id = SNOR_ID(0xc2, 0x20, 0x1a),
.fixup_flags = SPI_NOR_4B_OPCODES,
- .fixups = ¯onix_qpp4b_fixups,
}, {
/* MX66L1G45G */
.id = SNOR_ID(0xc2, 0x20, 0x1b),
- .fixups = ¯onix_qpp4b_fixups,
}, {
/* MX66L2G45G */
.id = SNOR_ID(0xc2, 0x20, 0x1c),
- .fixups = ¯onix_qpp4b_fixups,
}, {
.id = SNOR_ID(0xc2, 0x23, 0x14),
.name = "mx25v8035f",
@@ -189,15 +185,12 @@ static const struct flash_info macronix_nor_parts[] = {
}, {
/* MX25U51245G */
.id = SNOR_ID(0xc2, 0x25, 0x3a),
- .fixups = ¯onix_qpp4b_fixups,
}, {
/* MX66U1G45G */
.id = SNOR_ID(0xc2, 0x25, 0x3b),
- .fixups = ¯onix_qpp4b_fixups,
}, {
/* MX66U2G45G */
.id = SNOR_ID(0xc2, 0x25, 0x3c),
- .fixups = ¯onix_qpp4b_fixups,
}, {
.id = SNOR_ID(0xc2, 0x26, 0x18),
.name = "mx25l12855e",
@@ -229,7 +222,6 @@ static const struct flash_info macronix_nor_parts[] = {
}, {
/* MX25L3255E */
.id = SNOR_ID(0xc2, 0x9e, 0x16),
- .fixups = &mx25l3255e_fixups,
},
/*
* This spares us of adding new flash entries for flashes that can be
@@ -333,9 +325,22 @@ static const struct spi_nor_fixups macronix_nor_fixups = {
.late_init = macronix_nor_late_init,
};
+static const struct spi_nor_fixup macronix_fixups[] = {
+ { .fixups = ¯onix_nor_fixups },
+ { .id = SNOR_ID(0xc2, 0x20, 0x19), .fixups = &mx25l25635_fixups },
+ { .id = SNOR_ID(0xc2, 0x20, 0x1a), .fixups = ¯onix_qpp4b_fixups },
+ { .id = SNOR_ID(0xc2, 0x20, 0x1b), .fixups = ¯onix_qpp4b_fixups },
+ { .id = SNOR_ID(0xc2, 0x20, 0x1c), .fixups = ¯onix_qpp4b_fixups },
+ { .id = SNOR_ID(0xc2, 0x25, 0x3a), .fixups = ¯onix_qpp4b_fixups },
+ { .id = SNOR_ID(0xc2, 0x25, 0x3b), .fixups = ¯onix_qpp4b_fixups },
+ { .id = SNOR_ID(0xc2, 0x25, 0x3c), .fixups = ¯onix_qpp4b_fixups },
+ { .id = SNOR_ID(0xc2, 0x9e, 0x16), .fixups = &mx25l3255e_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_macronix = {
.name = "macronix",
.parts = macronix_nor_parts,
.nparts = ARRAY_SIZE(macronix_nor_parts),
- .fixups = ¯onix_nor_fixups,
+ .fixups = macronix_fixups,
+ .nfixups = ARRAY_SIZE(macronix_fixups),
};
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 344539d2a36a..2aabd6d487ba 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -206,13 +206,11 @@ static const struct flash_info micron_nor_parts[] = {
.id = SNOR_ID(0x2c, 0x5b, 0x1a),
.mfr_flags = USE_FSR,
.fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE,
- .fixups = &mt35xu512aba_fixups,
}, {
/* MT35XU01GBBA */
.id = SNOR_ID(0x2c, 0x5b, 0x1b),
.mfr_flags = USE_FSR,
.fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE,
- .fixups = &mt35_two_die_fixups,
}, {
.id = SNOR_ID(0x2c, 0x5b, 0x1c),
.name = "mt35xu02g",
@@ -221,7 +219,6 @@ static const struct flash_info micron_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ,
.mfr_flags = USE_FSR,
.fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,
- .fixups = &mt35_two_die_fixups,
},
};
@@ -233,6 +230,17 @@ static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor,
return 0;
}
+/*
+ * n25q00a parts share the first same 3 ID bytes with mt25qu01g.
+ * In order to not mix the fixups, further filter out using the part name.
+ */
+static bool n25q00a_match(const struct spi_nor *nor)
+{
+ const char *name = nor->info ? nor->info->name : NULL;
+
+ return name && !strncmp(name, "n25q00a", 7);
+}
+
static const struct spi_nor_fixups mt25qu512a_fixups = {
.post_bfpt = mt25qu512a_post_bfpt_fixup,
};
@@ -426,14 +434,12 @@ static const struct flash_info st_nor_parts[] = {
SPI_NOR_BP3_SR_BIT6,
.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
.mfr_flags = USE_FSR,
- .fixups = &n25q00_fixups,
}, {
.id = SNOR_ID(0x20, 0xba, 0x22),
.name = "mt25ql02g",
.size = SZ_256M,
.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
.mfr_flags = USE_FSR,
- .fixups = &mt25q02_fixups,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x15),
.name = "n25q016a",
@@ -480,7 +486,6 @@ static const struct flash_info st_nor_parts[] = {
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
SPI_NOR_BP3_SR_BIT6,
.mfr_flags = USE_FSR,
- .fixups = &mt25qu512a_fixups,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x20),
.name = "n25q512a",
@@ -493,21 +498,18 @@ static const struct flash_info st_nor_parts[] = {
.id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00),
.name = "mt25qu01g",
.mfr_flags = USE_FSR,
- .fixups = &mt25q01_fixups,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x21),
.name = "n25q00a",
.size = SZ_128M,
.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
.mfr_flags = USE_FSR,
- .fixups = &n25q00_fixups,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x22),
.name = "mt25qu02g",
.size = SZ_256M,
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.mfr_flags = USE_FSR,
- .fixups = &mt25q02_fixups,
}
};
@@ -657,16 +659,35 @@ static const struct spi_nor_fixups micron_st_nor_fixups = {
.late_init = micron_st_nor_late_init,
};
+static const struct spi_nor_fixup micron_fixups[] = {
+ { .fixups = µn_st_nor_fixups },
+ { .id = SNOR_ID(0x2c, 0x5b, 0x1a), .fixups = &mt35xu512aba_fixups },
+ { .id = SNOR_ID(0x2c, 0x5b, 0x1b), .fixups = &mt35_two_die_fixups },
+ { .id = SNOR_ID(0x2c, 0x5b, 0x1c), .fixups = &mt35_two_die_fixups },
+};
+
+static const struct spi_nor_fixup st_fixups[] = {
+ { .fixups = µn_st_nor_fixups },
+ { .id = SNOR_ID(0x20, 0xba, 0x21), .fixups = &n25q00_fixups },
+ { .id = SNOR_ID(0x20, 0xba, 0x22), .fixups = &mt25q02_fixups },
+ { .id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00), .fixups = &mt25qu512a_fixups },
+ { .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00), .fixups = &mt25q01_fixups },
+ { .id = SNOR_ID(0x20, 0xbb, 0x21), .match = n25q00a_match, .fixups = &n25q00_fixups },
+ { .id = SNOR_ID(0x20, 0xbb, 0x22), .fixups = &mt25q02_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_micron = {
.name = "micron",
.parts = micron_nor_parts,
.nparts = ARRAY_SIZE(micron_nor_parts),
- .fixups = µn_st_nor_fixups,
+ .fixups = micron_fixups,
+ .nfixups = ARRAY_SIZE(micron_fixups),
};
const struct spi_nor_manufacturer spi_nor_st = {
.name = "st",
.parts = st_nor_parts,
.nparts = ARRAY_SIZE(st_nor_parts),
- .fixups = µn_st_nor_fixups,
+ .fixups = st_fixups,
+ .nfixups = ARRAY_SIZE(st_fixups),
};
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index 285ac781fba8..39cb8ac3a037 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -727,12 +727,19 @@ static u8 spi_nor_smpt_addr_nbytes(const struct spi_nor *nor, const u32 settings
static void spi_nor_smpt_read_dummy_fixups(const struct spi_nor *nor,
u8 *read_dummy)
{
- if (nor->manufacturer && nor->manufacturer->fixups &&
- nor->manufacturer->fixups->smpt_read_dummy)
- nor->manufacturer->fixups->smpt_read_dummy(nor, read_dummy);
+ const struct spi_nor_fixup *fixups;
+ unsigned int i;
- if (nor->info->fixups && nor->info->fixups->smpt_read_dummy)
- nor->info->fixups->smpt_read_dummy(nor, read_dummy);
+ if (!nor->manufacturer || !nor->manufacturer->fixups)
+ return;
+
+ fixups = nor->manufacturer->fixups;
+
+ for (i = 0; i < nor->manufacturer->nfixups; i++) {
+ if (fixups[i].fixups->smpt_read_dummy &&
+ spi_nor_fixup_match(nor, &fixups[i]))
+ fixups[i].fixups->smpt_read_dummy(nor, read_dummy);
+ }
}
/**
@@ -757,12 +764,19 @@ static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings)
static void spi_nor_smpt_map_id_fixups(const struct spi_nor *nor, u8 *map_id)
{
- if (nor->manufacturer && nor->manufacturer->fixups &&
- nor->manufacturer->fixups->smpt_map_id)
- nor->manufacturer->fixups->smpt_map_id(nor, map_id);
+ const struct spi_nor_fixup *fixups;
+ unsigned int i;
- if (nor->info->fixups && nor->info->fixups->smpt_map_id)
- nor->info->fixups->smpt_map_id(nor, map_id);
+ if (!nor->manufacturer || !nor->manufacturer->fixups)
+ return;
+
+ fixups = nor->manufacturer->fixups;
+
+ for (i = 0; i < nor->manufacturer->nfixups; i++) {
+ if (fixups[i].fixups->smpt_map_id &&
+ spi_nor_fixup_match(nor, &fixups[i]))
+ fixups[i].fixups->smpt_map_id(nor, map_id);
+ }
}
/**
@@ -1406,17 +1420,23 @@ static int spi_nor_parse_sccr_mc(struct spi_nor *nor,
*/
static int spi_nor_post_sfdp_fixups(struct spi_nor *nor)
{
+ const struct spi_nor_fixup *fixups;
+ unsigned int i;
int ret;
- if (nor->manufacturer && nor->manufacturer->fixups &&
- nor->manufacturer->fixups->post_sfdp) {
- ret = nor->manufacturer->fixups->post_sfdp(nor);
- if (ret)
- return ret;
- }
+ if (!nor->manufacturer || !nor->manufacturer->fixups)
+ return 0;
- if (nor->info->fixups && nor->info->fixups->post_sfdp)
- return nor->info->fixups->post_sfdp(nor);
+ fixups = nor->manufacturer->fixups;
+
+ for (i = 0; i < nor->manufacturer->nfixups; i++) {
+ if (fixups[i].fixups->post_sfdp &&
+ spi_nor_fixup_match(nor, &fixups[i])) {
+ ret = fixups[i].fixups->post_sfdp(nor);
+ if (ret)
+ return ret;
+ }
+ }
return 0;
}
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index ca2703a5a338..f3862eb1a23a 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -905,7 +905,6 @@ static const struct flash_info spansion_nor_parts[] = {
.sector_size = SZ_256K,
.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.mfr_flags = USE_CLSR,
- .fixups = &s25fs_s_nor_fixups,
}, {
.id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x00),
.name = "s25sl12800",
@@ -941,7 +940,6 @@ static const struct flash_info spansion_nor_parts[] = {
.size = SZ_16M,
.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.mfr_flags = USE_CLSR,
- .fixups = &s25fs_s_nor_fixups,
}, {
.id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01),
.name = "s25fl129p1",
@@ -1001,76 +999,61 @@ static const struct flash_info spansion_nor_parts[] = {
.id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90),
.name = "s25hl512t",
.mfr_flags = USE_CLPEF,
- .fixups = &s25hx_t_fixups
}, {
.id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90),
.name = "s25hl01gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s25hx_t_fixups
}, {
.id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90),
.name = "s25hl02gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s25hx_t_fixups
}, {
.id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90),
.name = "s25fs256t",
.mfr_flags = USE_CLPEF,
- .fixups = &s25fs256t_fixups
}, {
.id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90),
.name = "s25hs512t",
.mfr_flags = USE_CLPEF,
- .fixups = &s25hx_t_fixups
}, {
.id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90),
.name = "s25hs01gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s25hx_t_fixups
}, {
.id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90),
.name = "s25hs02gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s25hx_t_fixups
}, {
/* S28HL256T */
.id = SNOR_ID(0x34, 0x5a, 0x19),
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0x34, 0x5a, 0x1a),
.name = "s28hl512t",
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0x34, 0x5a, 0x1b),
.name = "s28hl01gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
/* S28HL02GT */
.id = SNOR_ID(0x34, 0x5a, 0x1c),
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0x34, 0x5b, 0x19),
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0x34, 0x5b, 0x1a),
.name = "s28hs512t",
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0x34, 0x5b, 0x1b),
.name = "s28hs01gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0x34, 0x5b, 0x1c),
.name = "s28hs02gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0xef, 0x40, 0x13),
.name = "s25fl004k",
@@ -1170,9 +1153,31 @@ static const struct spi_nor_fixups spansion_nor_fixups = {
.late_init = spansion_nor_late_init,
};
+static const struct spi_nor_fixup spansion_fixups[] = {
+ { .fixups = &spansion_nor_fixups },
+ { .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x81), .fixups = &s25fs_s_nor_fixups },
+ { .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x81), .fixups = &s25fs_s_nor_fixups },
+ { .id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90), .fixups = &s25hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90), .fixups = &s25fs256t_fixups },
+ { .id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90), .fixups = &s25hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5a, 0x19), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5a, 0x1a), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5a, 0x1b), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5a, 0x1c), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5b, 0x19), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5b, 0x1a), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5b, 0x1b), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5b, 0x1c), .fixups = &s28hx_t_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_spansion = {
.name = "spansion",
.parts = spansion_nor_parts,
.nparts = ARRAY_SIZE(spansion_nor_parts),
- .fixups = &spansion_nor_fixups,
+ .fixups = spansion_fixups,
+ .nfixups = ARRAY_SIZE(spansion_fixups),
};
diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
index 77a0bc41d4e5..c460803b278b 100644
--- a/drivers/mtd/spi-nor/sst.c
+++ b/drivers/mtd/spi-nor/sst.c
@@ -152,14 +152,12 @@ static const struct flash_info sst_nor_parts[] = {
.id = SNOR_ID(0xbf, 0x26, 0x42),
.name = "sst26vf032b",
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
- .fixups = &sst26vf_nor_fixups,
}, {
.id = SNOR_ID(0xbf, 0x26, 0x43),
.name = "sst26vf064b",
.size = SZ_8M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- .fixups = &sst26vf_nor_fixups,
}, {
.id = SNOR_ID(0xbf, 0x26, 0x51),
.name = "sst26wf016b",
@@ -278,9 +276,16 @@ static const struct spi_nor_fixups sst_nor_fixups = {
.late_init = sst_nor_late_init,
};
+static const struct spi_nor_fixup sst_fixups[] = {
+ { .fixups = &sst_nor_fixups },
+ { .id = SNOR_ID(0xbf, 0x26, 0x42), .fixups = &sst26vf_nor_fixups },
+ { .id = SNOR_ID(0xbf, 0x26, 0x43), .fixups = &sst26vf_nor_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_sst = {
.name = "sst",
.parts = sst_nor_parts,
.nparts = ARRAY_SIZE(sst_nor_parts),
- .fixups = &sst_nor_fixups,
+ .fixups = sst_fixups,
+ .nfixups = ARRAY_SIZE(sst_fixups),
};
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 01a693033448..583b1669270f 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -219,7 +219,6 @@ static const struct flash_info winbond_nor_parts[] = {
.size = SZ_16M,
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
- .fixups = &w25q128_fixups,
}, {
/* W25Q256JV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x19),
@@ -228,7 +227,6 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
- .fixups = &w25q256_fixups,
}, {
/* W25Q512JV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x20),
@@ -242,7 +240,6 @@ static const struct flash_info winbond_nor_parts[] = {
.id = SNOR_ID(0xef, 0x40, 0x21),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
- .fixups = &winbond_nor_multi_die_fixups,
}, {
.id = SNOR_ID(0xef, 0x50, 0x12),
.name = "w25q20bw",
@@ -345,13 +342,11 @@ static const struct flash_info winbond_nor_parts[] = {
.id = SNOR_ID(0xef, 0x70, 0x21),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
- .fixups = &winbond_nor_multi_die_fixups,
}, {
/* W25Q02JV-M */
.id = SNOR_ID(0xef, 0x70, 0x22),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
- .fixups = &winbond_nor_multi_die_fixups,
}, {
.id = SNOR_ID(0xef, 0x71, 0x19),
.name = "w25m512jv",
@@ -553,9 +548,19 @@ static const struct spi_nor_fixups winbond_nor_fixups = {
.late_init = winbond_nor_late_init,
};
+static const struct spi_nor_fixup winbond_fixups[] = {
+ { .fixups = &winbond_nor_fixups },
+ { .id = SNOR_ID(0xef, 0x40, 0x18), .fixups = &w25q128_fixups },
+ { .id = SNOR_ID(0xef, 0x40, 0x19), .fixups = &w25q256_fixups },
+ { .id = SNOR_ID(0xef, 0x40, 0x21), .fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x70, 0x21), .fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x70, 0x22), .fixups = &winbond_nor_multi_die_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_winbond = {
.name = "winbond",
.parts = winbond_nor_parts,
.nparts = ARRAY_SIZE(winbond_nor_parts),
- .fixups = &winbond_nor_fixups,
+ .fixups = winbond_fixups,
+ .nfixups = ARRAY_SIZE(winbond_fixups),
};
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 05/23] mtd: spi-nor: Create the concept of fixup table with match function
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
Manufacturer ID tables increase and fixup() hooks proliferate. Having
one possible structure per chip was fine until the fixups started being
more and more common and needed, to some extend due to ID reuses. Mixing
fixups and chips becomes hard and requires extra helpers to sort which
ones are needed for a given chip, which every time this happens requires
a lot of rework.
Replace the two-level fixup association (a manufacturer wide hook and a
per flash_info hook) with a per-manufacturer list of fixups that can be
looked up by flash ID and/or match function.
The match logic works as follows:
- If there is an ID, it must match
- If there is a match function, it must match (cumulative)
- If there is no identifier (no ID nor any match function), it's a
catch-all entry typically used for flagging manufacturer fixups.
Suggested-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/atmel.c | 23 ++++++-----
drivers/mtd/spi-nor/core.c | 82 ++++++++++++++++++++++++++++------------
drivers/mtd/spi-nor/core.h | 23 +++++++++--
drivers/mtd/spi-nor/everspin.c | 7 +++-
drivers/mtd/spi-nor/gigadevice.c | 7 +++-
drivers/mtd/spi-nor/issi.c | 22 ++++++++---
drivers/mtd/spi-nor/macronix.c | 23 ++++++-----
drivers/mtd/spi-nor/micron-st.c | 43 +++++++++++++++------
drivers/mtd/spi-nor/sfdp.c | 56 ++++++++++++++++++---------
drivers/mtd/spi-nor/spansion.c | 41 +++++++++++---------
drivers/mtd/spi-nor/sst.c | 11 ++++--
drivers/mtd/spi-nor/winbond.c | 17 ++++++---
12 files changed, 247 insertions(+), 108 deletions(-)
diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
index 8741c0bda497..bccc702a2c4a 100644
--- a/drivers/mtd/spi-nor/atmel.c
+++ b/drivers/mtd/spi-nor/atmel.c
@@ -194,47 +194,40 @@ static const struct flash_info atmel_nor_parts[] = {
.size = SZ_512K,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
- .fixups = &atmel_nor_global_protection_fixups,
}, {
.id = SNOR_ID(0x1f, 0x45, 0x01),
.name = "at26df081a",
.size = SZ_1M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
- .fixups = &atmel_nor_global_protection_fixups
}, {
.id = SNOR_ID(0x1f, 0x46, 0x01),
.name = "at26df161a",
.size = SZ_2M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
- .fixups = &atmel_nor_global_protection_fixups
}, {
.id = SNOR_ID(0x1f, 0x47, 0x00),
.name = "at25df321",
.size = SZ_4M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
- .fixups = &atmel_nor_global_protection_fixups
}, {
.id = SNOR_ID(0x1f, 0x47, 0x01),
.name = "at25df321a",
.size = SZ_4M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
- .fixups = &atmel_nor_global_protection_fixups
}, {
.id = SNOR_ID(0x1f, 0x47, 0x08),
.name = "at25ff321a",
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
- .fixups = &atmel_nor_global_protection_fixups
}, {
.id = SNOR_ID(0x1f, 0x48, 0x00),
.name = "at25df641",
.size = SZ_8M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K,
- .fixups = &atmel_nor_global_protection_fixups
}, {
.id = SNOR_ID(0x1f, 0x66, 0x01),
.name = "at25fs010",
@@ -242,14 +235,12 @@ static const struct flash_info atmel_nor_parts[] = {
.size = SZ_128K,
.flags = SPI_NOR_HAS_LOCK,
.no_sfdp_flags = SECT_4K,
- .fixups = &at25fs_nor_fixups
}, {
.id = SNOR_ID(0x1f, 0x66, 0x04),
.name = "at25fs040",
.size = SZ_512K,
.flags = SPI_NOR_HAS_LOCK,
.no_sfdp_flags = SECT_4K,
- .fixups = &at25fs_nor_fixups
}, {
.id = SNOR_ID(0x1f, 0x87, 0x01),
.size = SZ_4M,
@@ -257,8 +248,22 @@ static const struct flash_info atmel_nor_parts[] = {
},
};
+static const struct spi_nor_fixup atmel_fixups[] = {
+ { .id = SNOR_ID(0x1f, 0x44, 0x01), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x45, 0x01), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x46, 0x01), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x47, 0x00), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x47, 0x01), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x47, 0x08), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x48, 0x00), .fixups = &atmel_nor_global_protection_fixups },
+ { .id = SNOR_ID(0x1f, 0x66, 0x01), .fixups = &at25fs_nor_fixups },
+ { .id = SNOR_ID(0x1f, 0x66, 0x04), .fixups = &at25fs_nor_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_atmel = {
.name = "atmel",
.parts = atmel_nor_parts,
.nparts = ARRAY_SIZE(atmel_nor_parts),
+ .fixups = atmel_fixups,
+ .nfixups = ARRAY_SIZE(atmel_fixups),
};
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index ac7812562047..3a611283a9e6 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2367,19 +2367,24 @@ int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
const struct sfdp_bfpt *bfpt)
{
+ const struct spi_nor_fixup *fixups;
int ret;
+ unsigned int i;
- if (nor->manufacturer && nor->manufacturer->fixups &&
- nor->manufacturer->fixups->post_bfpt) {
- ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,
- bfpt);
- if (ret)
- return ret;
+ if (!nor->manufacturer || !nor->manufacturer->fixups)
+ return 0;
+
+ fixups = nor->manufacturer->fixups;
+
+ for (i = 0; i < nor->manufacturer->nfixups; i++) {
+ if (fixups[i].fixups->post_bfpt &&
+ spi_nor_fixup_match(nor, &fixups[i])) {
+ ret = fixups[i].fixups->post_bfpt(nor, bfpt_header, bfpt);
+ if (ret)
+ return ret;
+ }
}
- if (nor->info->fixups && nor->info->fixups->post_bfpt)
- return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt);
-
return 0;
}
@@ -2636,6 +2641,26 @@ static int spi_nor_setup(struct spi_nor *nor,
return spi_nor_set_addr_nbytes(nor);
}
+bool spi_nor_fixup_match(const struct spi_nor *nor,
+ const struct spi_nor_fixup *fixup)
+{
+ const struct spi_nor_id *id = nor->info ? nor->info->id : NULL;
+
+ /* Filter by ID first, if available */
+ if (fixup->id) {
+ if (!id || fixup->id->len > id->len ||
+ memcmp(id->bytes, fixup->id->bytes, fixup->id->len))
+ return false;
+ }
+
+ /* Further filter with the match callback, if provided */
+ if (fixup->match)
+ return fixup->match(nor);
+
+ /* Either there was an ID and it matched, or it is a catch-all entry */
+ return true;
+}
+
/**
* spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
* settings based on MFR register and ->default_init() hook.
@@ -2643,12 +2668,19 @@ static int spi_nor_setup(struct spi_nor *nor,
*/
static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
{
- if (nor->manufacturer && nor->manufacturer->fixups &&
- nor->manufacturer->fixups->default_init)
- nor->manufacturer->fixups->default_init(nor);
+ const struct spi_nor_fixup *fixups;
+ unsigned int i;
- if (nor->info->fixups && nor->info->fixups->default_init)
- nor->info->fixups->default_init(nor);
+ if (!nor->manufacturer || !nor->manufacturer->fixups)
+ return;
+
+ fixups = nor->manufacturer->fixups;
+
+ for (i = 0; i < nor->manufacturer->nfixups; i++) {
+ if (fixups[i].fixups->default_init &&
+ spi_nor_fixup_match(nor, &fixups[i]))
+ fixups[i].fixups->default_init(nor);
+ }
}
/**
@@ -2797,22 +2829,24 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor)
static int spi_nor_late_init_params(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = nor->params;
+ const struct spi_nor_fixup *fixups;
+ unsigned int i;
int ret;
/* Needed by some late_init hooks */
spi_nor_init_flags(nor);
- if (nor->manufacturer && nor->manufacturer->fixups &&
- nor->manufacturer->fixups->late_init) {
- ret = nor->manufacturer->fixups->late_init(nor);
- if (ret)
- return ret;
- }
+ if (nor->manufacturer && nor->manufacturer->fixups) {
+ fixups = nor->manufacturer->fixups;
- if (nor->info->fixups && nor->info->fixups->late_init) {
- ret = nor->info->fixups->late_init(nor);
- if (ret)
- return ret;
+ for (i = 0; i < nor->manufacturer->nfixups; i++) {
+ if (fixups[i].fixups->late_init &&
+ spi_nor_fixup_match(nor, &fixups[i])) {
+ ret = fixups[i].fixups->late_init(nor);
+ if (ret)
+ return ret;
+ }
+ }
}
if (!nor->params->opcodes.die_erase)
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 7d43d3ba47ee..b650778a10de 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -445,6 +445,19 @@ struct spi_nor_fixups {
int (*late_init)(struct spi_nor *nor);
};
+/**
+ * struct spi_nor_fixup - SPI NOR fixup registration.
+ * @id: (optional) flash ID this fixup applies to, may only match the
+ * ID prefix, eg. just the first few bytes to match a whole family
+ * @match: (optional) custom match function (can be used together with @id)
+ * @fixups: the fixup hooks to apply when this entry matches
+ */
+struct spi_nor_fixup {
+ const struct spi_nor_id *id;
+ bool (*match)(const struct spi_nor *nor);
+ const struct spi_nor_fixups *fixups;
+};
+
/**
* struct spi_nor_id - SPI NOR flash ID.
*
@@ -560,7 +573,6 @@ struct flash_info {
u8 mfr_flags;
const struct spi_nor_otp_organization *otp;
- const struct spi_nor_fixups *fixups;
};
#define SNOR_ID(...) \
@@ -582,13 +594,16 @@ struct flash_info {
* @name: manufacturer name
* @parts: array of parts supported by this manufacturer
* @nparts: number of entries in the parts array
- * @fixups: hooks called at various points in time during spi_nor_scan()
+ * @fixups: list of fixups, each matched by ID (or a custom match function),
+ * applied to any part of this manufacturer.
+ * @nfixups: number of entries in the fixups array
*/
struct spi_nor_manufacturer {
const char *name;
const struct flash_info *parts;
unsigned int nparts;
- const struct spi_nor_fixups *fixups;
+ const struct spi_nor_fixup *fixups;
+ unsigned int nfixups;
};
/**
@@ -619,6 +634,8 @@ extern const struct spi_nor_manufacturer spi_nor_xmc;
extern const struct attribute_group *spi_nor_sysfs_groups[];
+bool spi_nor_fixup_match(const struct spi_nor *nor,
+ const struct spi_nor_fixup *fixup);
void spi_nor_spimem_setup_op(const struct spi_nor *nor,
struct spi_mem_op *op,
const enum spi_nor_protocol proto);
diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c
index add37104d673..864dffba0e9c 100644
--- a/drivers/mtd/spi-nor/everspin.c
+++ b/drivers/mtd/spi-nor/everspin.c
@@ -44,9 +44,14 @@ static const struct spi_nor_fixups everspin_nor_fixups = {
.default_init = everspin_nor_default_init,
};
+static const struct spi_nor_fixup everspin_fixups[] = {
+ { .fixups = &everspin_nor_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_everspin = {
.name = "everspin",
.parts = everspin_nor_parts,
.nparts = ARRAY_SIZE(everspin_nor_parts),
- .fixups = &everspin_nor_fixups,
+ .fixups = everspin_fixups,
+ .nfixups = ARRAY_SIZE(everspin_fixups),
};
diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
index 4070a692e968..f76fd0dedd0a 100644
--- a/drivers/mtd/spi-nor/gigadevice.c
+++ b/drivers/mtd/spi-nor/gigadevice.c
@@ -64,7 +64,6 @@ static const struct flash_info gigadevice_nor_parts[] = {
.id = SNOR_ID(0xc8, 0x40, 0x19),
.name = "gd25q256",
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6,
- .fixups = &gd25q256_fixups,
.fixup_flags = SPI_NOR_4B_OPCODES,
}, {
.id = SNOR_ID(0xc8, 0x60, 0x16),
@@ -87,8 +86,14 @@ static const struct flash_info gigadevice_nor_parts[] = {
},
};
+static const struct spi_nor_fixup gigadevice_fixups[] = {
+ { .id = SNOR_ID(0xc8, 0x40, 0x19), .fixups = &gd25q256_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_gigadevice = {
.name = "gigadevice",
.parts = gigadevice_nor_parts,
.nparts = ARRAY_SIZE(gigadevice_nor_parts),
+ .fixups = gigadevice_fixups,
+ .nfixups = ARRAY_SIZE(gigadevice_fixups),
};
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index 04db42b5141e..4842f8acd074 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -52,13 +52,11 @@ static const struct flash_info issi_nor_parts[] = {
.sector_size = SZ_32K,
.size = SZ_64K,
.no_sfdp_flags = SECT_4K,
- .fixups = &pm25lv_nor_fixups
}, {
.name = "pm25lv010",
.sector_size = SZ_32K,
.size = SZ_128K,
.no_sfdp_flags = SECT_4K,
- .fixups = &pm25lv_nor_fixups
}, {
.id = SNOR_ID(0x7f, 0x9d, 0x20),
.name = "is25cd512",
@@ -103,7 +101,6 @@ static const struct flash_info issi_nor_parts[] = {
}, {
.id = SNOR_ID(0x9d, 0x60, 0x19),
.name = "is25lp256",
- .fixups = &is25lp256_fixups,
.fixup_flags = SPI_NOR_4B_OPCODES,
}, {
.id = SNOR_ID(0x9d, 0x70, 0x16),
@@ -124,7 +121,6 @@ static const struct flash_info issi_nor_parts[] = {
.id = SNOR_ID(0x9d, 0x70, 0x19),
.name = "is25wp256",
.flags = SPI_NOR_QUAD_PP,
- .fixups = &is25lp256_fixups,
.fixup_flags = SPI_NOR_4B_OPCODES,
}
};
@@ -139,9 +135,25 @@ static const struct spi_nor_fixups issi_fixups = {
.default_init = issi_nor_default_init,
};
+/* PM25LV parts have no JEDEC ID and are likely matched by name */
+static bool issi_pm25lv_match(const struct spi_nor *nor)
+{
+ const char *name = nor->info ? nor->info->name : NULL;
+
+ return name && !strncmp(name, "pm25lv", 6);
+}
+
+static const struct spi_nor_fixup issi_fixup_list[] = {
+ { .fixups = &issi_fixups },
+ { .match = issi_pm25lv_match, .fixups = &pm25lv_nor_fixups },
+ { .id = SNOR_ID(0x9d, 0x60, 0x19), .fixups = &is25lp256_fixups },
+ { .id = SNOR_ID(0x9d, 0x70, 0x19), .fixups = &is25lp256_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_issi = {
.name = "issi",
.parts = issi_nor_parts,
.nparts = ARRAY_SIZE(issi_nor_parts),
- .fixups = &issi_fixups,
+ .fixups = issi_fixup_list,
+ .nfixups = ARRAY_SIZE(issi_fixup_list),
};
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index 55612237c1ef..04b431bf5f13 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -137,20 +137,16 @@ static const struct flash_info macronix_nor_parts[] = {
}, {
/* MX25L25635E, MX25L25645G */
.id = SNOR_ID(0xc2, 0x20, 0x19),
- .fixups = &mx25l25635_fixups
}, {
/* MX66L51235F */
.id = SNOR_ID(0xc2, 0x20, 0x1a),
.fixup_flags = SPI_NOR_4B_OPCODES,
- .fixups = ¯onix_qpp4b_fixups,
}, {
/* MX66L1G45G */
.id = SNOR_ID(0xc2, 0x20, 0x1b),
- .fixups = ¯onix_qpp4b_fixups,
}, {
/* MX66L2G45G */
.id = SNOR_ID(0xc2, 0x20, 0x1c),
- .fixups = ¯onix_qpp4b_fixups,
}, {
.id = SNOR_ID(0xc2, 0x23, 0x14),
.name = "mx25v8035f",
@@ -189,15 +185,12 @@ static const struct flash_info macronix_nor_parts[] = {
}, {
/* MX25U51245G */
.id = SNOR_ID(0xc2, 0x25, 0x3a),
- .fixups = ¯onix_qpp4b_fixups,
}, {
/* MX66U1G45G */
.id = SNOR_ID(0xc2, 0x25, 0x3b),
- .fixups = ¯onix_qpp4b_fixups,
}, {
/* MX66U2G45G */
.id = SNOR_ID(0xc2, 0x25, 0x3c),
- .fixups = ¯onix_qpp4b_fixups,
}, {
.id = SNOR_ID(0xc2, 0x26, 0x18),
.name = "mx25l12855e",
@@ -229,7 +222,6 @@ static const struct flash_info macronix_nor_parts[] = {
}, {
/* MX25L3255E */
.id = SNOR_ID(0xc2, 0x9e, 0x16),
- .fixups = &mx25l3255e_fixups,
},
/*
* This spares us of adding new flash entries for flashes that can be
@@ -333,9 +325,22 @@ static const struct spi_nor_fixups macronix_nor_fixups = {
.late_init = macronix_nor_late_init,
};
+static const struct spi_nor_fixup macronix_fixups[] = {
+ { .fixups = ¯onix_nor_fixups },
+ { .id = SNOR_ID(0xc2, 0x20, 0x19), .fixups = &mx25l25635_fixups },
+ { .id = SNOR_ID(0xc2, 0x20, 0x1a), .fixups = ¯onix_qpp4b_fixups },
+ { .id = SNOR_ID(0xc2, 0x20, 0x1b), .fixups = ¯onix_qpp4b_fixups },
+ { .id = SNOR_ID(0xc2, 0x20, 0x1c), .fixups = ¯onix_qpp4b_fixups },
+ { .id = SNOR_ID(0xc2, 0x25, 0x3a), .fixups = ¯onix_qpp4b_fixups },
+ { .id = SNOR_ID(0xc2, 0x25, 0x3b), .fixups = ¯onix_qpp4b_fixups },
+ { .id = SNOR_ID(0xc2, 0x25, 0x3c), .fixups = ¯onix_qpp4b_fixups },
+ { .id = SNOR_ID(0xc2, 0x9e, 0x16), .fixups = &mx25l3255e_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_macronix = {
.name = "macronix",
.parts = macronix_nor_parts,
.nparts = ARRAY_SIZE(macronix_nor_parts),
- .fixups = ¯onix_nor_fixups,
+ .fixups = macronix_fixups,
+ .nfixups = ARRAY_SIZE(macronix_fixups),
};
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 344539d2a36a..2aabd6d487ba 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -206,13 +206,11 @@ static const struct flash_info micron_nor_parts[] = {
.id = SNOR_ID(0x2c, 0x5b, 0x1a),
.mfr_flags = USE_FSR,
.fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE,
- .fixups = &mt35xu512aba_fixups,
}, {
/* MT35XU01GBBA */
.id = SNOR_ID(0x2c, 0x5b, 0x1b),
.mfr_flags = USE_FSR,
.fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE,
- .fixups = &mt35_two_die_fixups,
}, {
.id = SNOR_ID(0x2c, 0x5b, 0x1c),
.name = "mt35xu02g",
@@ -221,7 +219,6 @@ static const struct flash_info micron_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ,
.mfr_flags = USE_FSR,
.fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,
- .fixups = &mt35_two_die_fixups,
},
};
@@ -233,6 +230,17 @@ static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor,
return 0;
}
+/*
+ * n25q00a parts share the first same 3 ID bytes with mt25qu01g.
+ * In order to not mix the fixups, further filter out using the part name.
+ */
+static bool n25q00a_match(const struct spi_nor *nor)
+{
+ const char *name = nor->info ? nor->info->name : NULL;
+
+ return name && !strncmp(name, "n25q00a", 7);
+}
+
static const struct spi_nor_fixups mt25qu512a_fixups = {
.post_bfpt = mt25qu512a_post_bfpt_fixup,
};
@@ -426,14 +434,12 @@ static const struct flash_info st_nor_parts[] = {
SPI_NOR_BP3_SR_BIT6,
.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
.mfr_flags = USE_FSR,
- .fixups = &n25q00_fixups,
}, {
.id = SNOR_ID(0x20, 0xba, 0x22),
.name = "mt25ql02g",
.size = SZ_256M,
.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
.mfr_flags = USE_FSR,
- .fixups = &mt25q02_fixups,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x15),
.name = "n25q016a",
@@ -480,7 +486,6 @@ static const struct flash_info st_nor_parts[] = {
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
SPI_NOR_BP3_SR_BIT6,
.mfr_flags = USE_FSR,
- .fixups = &mt25qu512a_fixups,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x20),
.name = "n25q512a",
@@ -493,21 +498,18 @@ static const struct flash_info st_nor_parts[] = {
.id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00),
.name = "mt25qu01g",
.mfr_flags = USE_FSR,
- .fixups = &mt25q01_fixups,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x21),
.name = "n25q00a",
.size = SZ_128M,
.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
.mfr_flags = USE_FSR,
- .fixups = &n25q00_fixups,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x22),
.name = "mt25qu02g",
.size = SZ_256M,
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.mfr_flags = USE_FSR,
- .fixups = &mt25q02_fixups,
}
};
@@ -657,16 +659,35 @@ static const struct spi_nor_fixups micron_st_nor_fixups = {
.late_init = micron_st_nor_late_init,
};
+static const struct spi_nor_fixup micron_fixups[] = {
+ { .fixups = µn_st_nor_fixups },
+ { .id = SNOR_ID(0x2c, 0x5b, 0x1a), .fixups = &mt35xu512aba_fixups },
+ { .id = SNOR_ID(0x2c, 0x5b, 0x1b), .fixups = &mt35_two_die_fixups },
+ { .id = SNOR_ID(0x2c, 0x5b, 0x1c), .fixups = &mt35_two_die_fixups },
+};
+
+static const struct spi_nor_fixup st_fixups[] = {
+ { .fixups = µn_st_nor_fixups },
+ { .id = SNOR_ID(0x20, 0xba, 0x21), .fixups = &n25q00_fixups },
+ { .id = SNOR_ID(0x20, 0xba, 0x22), .fixups = &mt25q02_fixups },
+ { .id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00), .fixups = &mt25qu512a_fixups },
+ { .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00), .fixups = &mt25q01_fixups },
+ { .id = SNOR_ID(0x20, 0xbb, 0x21), .match = n25q00a_match, .fixups = &n25q00_fixups },
+ { .id = SNOR_ID(0x20, 0xbb, 0x22), .fixups = &mt25q02_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_micron = {
.name = "micron",
.parts = micron_nor_parts,
.nparts = ARRAY_SIZE(micron_nor_parts),
- .fixups = µn_st_nor_fixups,
+ .fixups = micron_fixups,
+ .nfixups = ARRAY_SIZE(micron_fixups),
};
const struct spi_nor_manufacturer spi_nor_st = {
.name = "st",
.parts = st_nor_parts,
.nparts = ARRAY_SIZE(st_nor_parts),
- .fixups = µn_st_nor_fixups,
+ .fixups = st_fixups,
+ .nfixups = ARRAY_SIZE(st_fixups),
};
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index 285ac781fba8..39cb8ac3a037 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -727,12 +727,19 @@ static u8 spi_nor_smpt_addr_nbytes(const struct spi_nor *nor, const u32 settings
static void spi_nor_smpt_read_dummy_fixups(const struct spi_nor *nor,
u8 *read_dummy)
{
- if (nor->manufacturer && nor->manufacturer->fixups &&
- nor->manufacturer->fixups->smpt_read_dummy)
- nor->manufacturer->fixups->smpt_read_dummy(nor, read_dummy);
+ const struct spi_nor_fixup *fixups;
+ unsigned int i;
- if (nor->info->fixups && nor->info->fixups->smpt_read_dummy)
- nor->info->fixups->smpt_read_dummy(nor, read_dummy);
+ if (!nor->manufacturer || !nor->manufacturer->fixups)
+ return;
+
+ fixups = nor->manufacturer->fixups;
+
+ for (i = 0; i < nor->manufacturer->nfixups; i++) {
+ if (fixups[i].fixups->smpt_read_dummy &&
+ spi_nor_fixup_match(nor, &fixups[i]))
+ fixups[i].fixups->smpt_read_dummy(nor, read_dummy);
+ }
}
/**
@@ -757,12 +764,19 @@ static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings)
static void spi_nor_smpt_map_id_fixups(const struct spi_nor *nor, u8 *map_id)
{
- if (nor->manufacturer && nor->manufacturer->fixups &&
- nor->manufacturer->fixups->smpt_map_id)
- nor->manufacturer->fixups->smpt_map_id(nor, map_id);
+ const struct spi_nor_fixup *fixups;
+ unsigned int i;
- if (nor->info->fixups && nor->info->fixups->smpt_map_id)
- nor->info->fixups->smpt_map_id(nor, map_id);
+ if (!nor->manufacturer || !nor->manufacturer->fixups)
+ return;
+
+ fixups = nor->manufacturer->fixups;
+
+ for (i = 0; i < nor->manufacturer->nfixups; i++) {
+ if (fixups[i].fixups->smpt_map_id &&
+ spi_nor_fixup_match(nor, &fixups[i]))
+ fixups[i].fixups->smpt_map_id(nor, map_id);
+ }
}
/**
@@ -1406,17 +1420,23 @@ static int spi_nor_parse_sccr_mc(struct spi_nor *nor,
*/
static int spi_nor_post_sfdp_fixups(struct spi_nor *nor)
{
+ const struct spi_nor_fixup *fixups;
+ unsigned int i;
int ret;
- if (nor->manufacturer && nor->manufacturer->fixups &&
- nor->manufacturer->fixups->post_sfdp) {
- ret = nor->manufacturer->fixups->post_sfdp(nor);
- if (ret)
- return ret;
- }
+ if (!nor->manufacturer || !nor->manufacturer->fixups)
+ return 0;
- if (nor->info->fixups && nor->info->fixups->post_sfdp)
- return nor->info->fixups->post_sfdp(nor);
+ fixups = nor->manufacturer->fixups;
+
+ for (i = 0; i < nor->manufacturer->nfixups; i++) {
+ if (fixups[i].fixups->post_sfdp &&
+ spi_nor_fixup_match(nor, &fixups[i])) {
+ ret = fixups[i].fixups->post_sfdp(nor);
+ if (ret)
+ return ret;
+ }
+ }
return 0;
}
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index ca2703a5a338..f3862eb1a23a 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -905,7 +905,6 @@ static const struct flash_info spansion_nor_parts[] = {
.sector_size = SZ_256K,
.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.mfr_flags = USE_CLSR,
- .fixups = &s25fs_s_nor_fixups,
}, {
.id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x00),
.name = "s25sl12800",
@@ -941,7 +940,6 @@ static const struct flash_info spansion_nor_parts[] = {
.size = SZ_16M,
.no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.mfr_flags = USE_CLSR,
- .fixups = &s25fs_s_nor_fixups,
}, {
.id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01),
.name = "s25fl129p1",
@@ -1001,76 +999,61 @@ static const struct flash_info spansion_nor_parts[] = {
.id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90),
.name = "s25hl512t",
.mfr_flags = USE_CLPEF,
- .fixups = &s25hx_t_fixups
}, {
.id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90),
.name = "s25hl01gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s25hx_t_fixups
}, {
.id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90),
.name = "s25hl02gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s25hx_t_fixups
}, {
.id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90),
.name = "s25fs256t",
.mfr_flags = USE_CLPEF,
- .fixups = &s25fs256t_fixups
}, {
.id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90),
.name = "s25hs512t",
.mfr_flags = USE_CLPEF,
- .fixups = &s25hx_t_fixups
}, {
.id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90),
.name = "s25hs01gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s25hx_t_fixups
}, {
.id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90),
.name = "s25hs02gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s25hx_t_fixups
}, {
/* S28HL256T */
.id = SNOR_ID(0x34, 0x5a, 0x19),
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0x34, 0x5a, 0x1a),
.name = "s28hl512t",
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0x34, 0x5a, 0x1b),
.name = "s28hl01gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
/* S28HL02GT */
.id = SNOR_ID(0x34, 0x5a, 0x1c),
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0x34, 0x5b, 0x19),
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0x34, 0x5b, 0x1a),
.name = "s28hs512t",
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0x34, 0x5b, 0x1b),
.name = "s28hs01gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0x34, 0x5b, 0x1c),
.name = "s28hs02gt",
.mfr_flags = USE_CLPEF,
- .fixups = &s28hx_t_fixups,
}, {
.id = SNOR_ID(0xef, 0x40, 0x13),
.name = "s25fl004k",
@@ -1170,9 +1153,31 @@ static const struct spi_nor_fixups spansion_nor_fixups = {
.late_init = spansion_nor_late_init,
};
+static const struct spi_nor_fixup spansion_fixups[] = {
+ { .fixups = &spansion_nor_fixups },
+ { .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x81), .fixups = &s25fs_s_nor_fixups },
+ { .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x81), .fixups = &s25fs_s_nor_fixups },
+ { .id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90), .fixups = &s25hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90), .fixups = &s25fs256t_fixups },
+ { .id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90), .fixups = &s25hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5a, 0x19), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5a, 0x1a), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5a, 0x1b), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5a, 0x1c), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5b, 0x19), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5b, 0x1a), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5b, 0x1b), .fixups = &s28hx_t_fixups },
+ { .id = SNOR_ID(0x34, 0x5b, 0x1c), .fixups = &s28hx_t_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_spansion = {
.name = "spansion",
.parts = spansion_nor_parts,
.nparts = ARRAY_SIZE(spansion_nor_parts),
- .fixups = &spansion_nor_fixups,
+ .fixups = spansion_fixups,
+ .nfixups = ARRAY_SIZE(spansion_fixups),
};
diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
index 77a0bc41d4e5..c460803b278b 100644
--- a/drivers/mtd/spi-nor/sst.c
+++ b/drivers/mtd/spi-nor/sst.c
@@ -152,14 +152,12 @@ static const struct flash_info sst_nor_parts[] = {
.id = SNOR_ID(0xbf, 0x26, 0x42),
.name = "sst26vf032b",
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
- .fixups = &sst26vf_nor_fixups,
}, {
.id = SNOR_ID(0xbf, 0x26, 0x43),
.name = "sst26vf064b",
.size = SZ_8M,
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
- .fixups = &sst26vf_nor_fixups,
}, {
.id = SNOR_ID(0xbf, 0x26, 0x51),
.name = "sst26wf016b",
@@ -278,9 +276,16 @@ static const struct spi_nor_fixups sst_nor_fixups = {
.late_init = sst_nor_late_init,
};
+static const struct spi_nor_fixup sst_fixups[] = {
+ { .fixups = &sst_nor_fixups },
+ { .id = SNOR_ID(0xbf, 0x26, 0x42), .fixups = &sst26vf_nor_fixups },
+ { .id = SNOR_ID(0xbf, 0x26, 0x43), .fixups = &sst26vf_nor_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_sst = {
.name = "sst",
.parts = sst_nor_parts,
.nparts = ARRAY_SIZE(sst_nor_parts),
- .fixups = &sst_nor_fixups,
+ .fixups = sst_fixups,
+ .nfixups = ARRAY_SIZE(sst_fixups),
};
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 01a693033448..583b1669270f 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -219,7 +219,6 @@ static const struct flash_info winbond_nor_parts[] = {
.size = SZ_16M,
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
- .fixups = &w25q128_fixups,
}, {
/* W25Q256JV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x19),
@@ -228,7 +227,6 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
- .fixups = &w25q256_fixups,
}, {
/* W25Q512JV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x20),
@@ -242,7 +240,6 @@ static const struct flash_info winbond_nor_parts[] = {
.id = SNOR_ID(0xef, 0x40, 0x21),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
- .fixups = &winbond_nor_multi_die_fixups,
}, {
.id = SNOR_ID(0xef, 0x50, 0x12),
.name = "w25q20bw",
@@ -345,13 +342,11 @@ static const struct flash_info winbond_nor_parts[] = {
.id = SNOR_ID(0xef, 0x70, 0x21),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
- .fixups = &winbond_nor_multi_die_fixups,
}, {
/* W25Q02JV-M */
.id = SNOR_ID(0xef, 0x70, 0x22),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
- .fixups = &winbond_nor_multi_die_fixups,
}, {
.id = SNOR_ID(0xef, 0x71, 0x19),
.name = "w25m512jv",
@@ -553,9 +548,19 @@ static const struct spi_nor_fixups winbond_nor_fixups = {
.late_init = winbond_nor_late_init,
};
+static const struct spi_nor_fixup winbond_fixups[] = {
+ { .fixups = &winbond_nor_fixups },
+ { .id = SNOR_ID(0xef, 0x40, 0x18), .fixups = &w25q128_fixups },
+ { .id = SNOR_ID(0xef, 0x40, 0x19), .fixups = &w25q256_fixups },
+ { .id = SNOR_ID(0xef, 0x40, 0x21), .fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x70, 0x21), .fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x70, 0x22), .fixups = &winbond_nor_multi_die_fixups },
+};
+
const struct spi_nor_manufacturer spi_nor_winbond = {
.name = "winbond",
.parts = winbond_nor_parts,
.nparts = ARRAY_SIZE(winbond_nor_parts),
- .fixups = &winbond_nor_fixups,
+ .fixups = winbond_fixups,
+ .nfixups = ARRAY_SIZE(winbond_fixups),
};
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 06/23] mtd: spi-nor: Create an indirection on the part name
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
We currently print through sysfs and debugfs the name of the part if the
.name field, which is legacy, has been filled in the ID table (otherwise
"(null)" is printed). These IDs had an interest until manufacturers
started re-using more and more extensively the so called unique JEDEC
IDs. At this stage, a name that was tailored for a chip sold in 2016 may
no longer be relevant for a chip sold in 2026. Still showing this name
through the various filesystems may confuse people, removing these names
cannot be done since they are now part of the user ABI (because of
sysfs).
In order to allow overwriting the .name field (which is part of a
read-only structure), let's create a spi-nor pointer which will by
default point to that .name, but which can be cleared in fixup hooks to
make sure the name is hidden on newer parts.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/core.c | 1 +
drivers/mtd/spi-nor/debugfs.c | 3 +--
drivers/mtd/spi-nor/sysfs.c | 4 ++--
include/linux/mtd/spi-nor.h | 1 +
4 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 3a611283a9e6..cf6eccb4c423 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -3492,6 +3492,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
return PTR_ERR(info);
nor->info = info;
+ nor->partname = info->name;
mutex_init(&nor->lock);
diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
index 512825c3fc85..275671222588 100644
--- a/drivers/mtd/spi-nor/debugfs.c
+++ b/drivers/mtd/spi-nor/debugfs.c
@@ -82,13 +82,12 @@ static int spi_nor_params_show(struct seq_file *s, void *data)
struct spi_nor_flash_parameter *params = nor->params;
struct spi_nor_erase_map *erase_map = ¶ms->erase_map;
struct spi_nor_erase_region *region = erase_map->regions;
- const struct flash_info *info = nor->info;
char buf[16], *str;
loff_t lock_start;
u64 lock_length;
unsigned int i;
- seq_printf(s, "name\t\t%s\n", info->name);
+ seq_printf(s, "name\t\t%s\n", nor->partname);
seq_printf(s, "id\t\t%*ph\n", SPI_NOR_MAX_ID_LEN, nor->id);
string_get_size(params->size, 1, STRING_UNITS_2, buf, sizeof(buf));
seq_printf(s, "size\t\t%s\n", buf);
diff --git a/drivers/mtd/spi-nor/sysfs.c b/drivers/mtd/spi-nor/sysfs.c
index 643513ee891b..a2dabe4c6422 100644
--- a/drivers/mtd/spi-nor/sysfs.c
+++ b/drivers/mtd/spi-nor/sysfs.c
@@ -25,7 +25,7 @@ static ssize_t partname_show(struct device *dev,
struct spi_mem *spimem = spi_get_drvdata(spi);
struct spi_nor *nor = spi_mem_get_drvdata(spimem);
- return sysfs_emit(buf, "%s\n", nor->info->name);
+ return sysfs_emit(buf, "%s\n", nor->partname);
}
static DEVICE_ATTR_RO(partname);
@@ -78,7 +78,7 @@ static umode_t spi_nor_sysfs_is_visible(struct kobject *kobj,
if (attr == &dev_attr_manufacturer.attr && !nor->manufacturer)
return 0;
- if (attr == &dev_attr_partname.attr && !nor->info->name)
+ if (attr == &dev_attr_partname.attr && !nor->partname)
return 0;
if (attr == &dev_attr_jedec_id.attr && !nor->info->id && !nor->id)
return 0;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 3a55d76ea77d..b1e573367604 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -395,6 +395,7 @@ struct spi_nor {
u8 *id;
const struct flash_info *info;
const struct spi_nor_manufacturer *manufacturer;
+ const char *partname;
u8 addr_nbytes;
u8 erase_opcode;
u8 read_opcode;
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 06/23] mtd: spi-nor: Create an indirection on the part name
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
We currently print through sysfs and debugfs the name of the part if the
.name field, which is legacy, has been filled in the ID table (otherwise
"(null)" is printed). These IDs had an interest until manufacturers
started re-using more and more extensively the so called unique JEDEC
IDs. At this stage, a name that was tailored for a chip sold in 2016 may
no longer be relevant for a chip sold in 2026. Still showing this name
through the various filesystems may confuse people, removing these names
cannot be done since they are now part of the user ABI (because of
sysfs).
In order to allow overwriting the .name field (which is part of a
read-only structure), let's create a spi-nor pointer which will by
default point to that .name, but which can be cleared in fixup hooks to
make sure the name is hidden on newer parts.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/core.c | 1 +
drivers/mtd/spi-nor/debugfs.c | 3 +--
drivers/mtd/spi-nor/sysfs.c | 4 ++--
include/linux/mtd/spi-nor.h | 1 +
4 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 3a611283a9e6..cf6eccb4c423 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -3492,6 +3492,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
return PTR_ERR(info);
nor->info = info;
+ nor->partname = info->name;
mutex_init(&nor->lock);
diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
index 512825c3fc85..275671222588 100644
--- a/drivers/mtd/spi-nor/debugfs.c
+++ b/drivers/mtd/spi-nor/debugfs.c
@@ -82,13 +82,12 @@ static int spi_nor_params_show(struct seq_file *s, void *data)
struct spi_nor_flash_parameter *params = nor->params;
struct spi_nor_erase_map *erase_map = ¶ms->erase_map;
struct spi_nor_erase_region *region = erase_map->regions;
- const struct flash_info *info = nor->info;
char buf[16], *str;
loff_t lock_start;
u64 lock_length;
unsigned int i;
- seq_printf(s, "name\t\t%s\n", info->name);
+ seq_printf(s, "name\t\t%s\n", nor->partname);
seq_printf(s, "id\t\t%*ph\n", SPI_NOR_MAX_ID_LEN, nor->id);
string_get_size(params->size, 1, STRING_UNITS_2, buf, sizeof(buf));
seq_printf(s, "size\t\t%s\n", buf);
diff --git a/drivers/mtd/spi-nor/sysfs.c b/drivers/mtd/spi-nor/sysfs.c
index 643513ee891b..a2dabe4c6422 100644
--- a/drivers/mtd/spi-nor/sysfs.c
+++ b/drivers/mtd/spi-nor/sysfs.c
@@ -25,7 +25,7 @@ static ssize_t partname_show(struct device *dev,
struct spi_mem *spimem = spi_get_drvdata(spi);
struct spi_nor *nor = spi_mem_get_drvdata(spimem);
- return sysfs_emit(buf, "%s\n", nor->info->name);
+ return sysfs_emit(buf, "%s\n", nor->partname);
}
static DEVICE_ATTR_RO(partname);
@@ -78,7 +78,7 @@ static umode_t spi_nor_sysfs_is_visible(struct kobject *kobj,
if (attr == &dev_attr_manufacturer.attr && !nor->manufacturer)
return 0;
- if (attr == &dev_attr_partname.attr && !nor->info->name)
+ if (attr == &dev_attr_partname.attr && !nor->partname)
return 0;
if (attr == &dev_attr_jedec_id.attr && !nor->info->id && !nor->id)
return 0;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 3a55d76ea77d..b1e573367604 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -395,6 +395,7 @@ struct spi_nor {
u8 *id;
const struct flash_info *info;
const struct spi_nor_manufacturer *manufacturer;
+ const char *partname;
u8 addr_nbytes;
u8 erase_opcode;
u8 read_opcode;
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 07/23] mtd: spi-nor: Move the SFDP header structure to a C header
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
The sfdp_header structure is currently defined in sfdp.c, whereas the
sfdp_parameter_header structure is defined in sfdp.h. In order to ease
the reuse of this structure outside of the sfdp.c file, move this
structure to the sfdp C header (.h).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/sfdp.c | 11 -----------
drivers/mtd/spi-nor/sfdp.h | 11 +++++++++++
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index 39cb8ac3a037..8e39bacddf16 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -34,17 +34,6 @@
#define SFDP_SIGNATURE 0x50444653U
-struct sfdp_header {
- u32 signature; /* Ox50444653U <=> "SFDP" */
- u8 minor;
- u8 major;
- u8 nph; /* 0-base number of parameter headers */
- u8 unused;
-
- /* Basic Flash Parameter Table. */
- struct sfdp_parameter_header bfpt_header;
-};
-
/* Fast Read settings. */
struct sfdp_bfpt_read {
/* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h
index e8ed814c6530..2cbe22246c5e 100644
--- a/drivers/mtd/spi-nor/sfdp.h
+++ b/drivers/mtd/spi-nor/sfdp.h
@@ -149,4 +149,15 @@ struct sfdp_parameter_header {
u8 id_msb;
};
+struct sfdp_header {
+ u32 signature; /* Ox50444653U <=> "SFDP" */
+ u8 minor;
+ u8 major;
+ u8 nph; /* 0-base number of parameter headers */
+ u8 unused;
+
+ /* Basic Flash Parameter Table. */
+ struct sfdp_parameter_header bfpt_header;
+};
+
#endif /* __LINUX_MTD_SFDP_H */
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 07/23] mtd: spi-nor: Move the SFDP header structure to a C header
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
The sfdp_header structure is currently defined in sfdp.c, whereas the
sfdp_parameter_header structure is defined in sfdp.h. In order to ease
the reuse of this structure outside of the sfdp.c file, move this
structure to the sfdp C header (.h).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/sfdp.c | 11 -----------
drivers/mtd/spi-nor/sfdp.h | 11 +++++++++++
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index 39cb8ac3a037..8e39bacddf16 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -34,17 +34,6 @@
#define SFDP_SIGNATURE 0x50444653U
-struct sfdp_header {
- u32 signature; /* Ox50444653U <=> "SFDP" */
- u8 minor;
- u8 major;
- u8 nph; /* 0-base number of parameter headers */
- u8 unused;
-
- /* Basic Flash Parameter Table. */
- struct sfdp_parameter_header bfpt_header;
-};
-
/* Fast Read settings. */
struct sfdp_bfpt_read {
/* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h
index e8ed814c6530..2cbe22246c5e 100644
--- a/drivers/mtd/spi-nor/sfdp.h
+++ b/drivers/mtd/spi-nor/sfdp.h
@@ -149,4 +149,15 @@ struct sfdp_parameter_header {
u8 id_msb;
};
+struct sfdp_header {
+ u32 signature; /* Ox50444653U <=> "SFDP" */
+ u8 minor;
+ u8 major;
+ u8 nph; /* 0-base number of parameter headers */
+ u8 unused;
+
+ /* Basic Flash Parameter Table. */
+ struct sfdp_parameter_header bfpt_header;
+};
+
#endif /* __LINUX_MTD_SFDP_H */
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 08/23] mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-Q/N parts
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision between the JV and RV families. Both chips are
very similar in practice, it is mostly a matter of electrical
differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2 opcode
(0x31). They also do not require the multi-die fixups which must remain
assigned to the JV chips.
Finally, since they share the IDs but not the names, we must hide the
names using a fixup.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/winbond.c | 56 ++++++++++++++++++++++++++++++++++++++++---
1 file changed, 53 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 583b1669270f..8c1cad9e21b4 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -146,6 +146,51 @@ static const struct spi_nor_fixups winbond_nor_multi_die_fixups = {
.post_sfdp = winbond_nor_multi_die_post_sfdp_fixups,
};
+static int winbond_nor_partname_post_sfdp_fixups(struct spi_nor *nor)
+{
+ /*
+ * W25QxxRV parts re-use the JEDEC IDs of the JV family. Their name
+ * being a legacy field, it is kept for the already established JV parts
+ * but must not be exposed by the newer RV ones.
+ */
+ nor->partname = NULL;
+
+ return 0;
+}
+
+static const struct spi_nor_fixups winbond_nor_partname_fixups = {
+ .post_sfdp = winbond_nor_partname_post_sfdp_fixups,
+};
+
+static bool is_w25qxxrv(const struct spi_nor *nor)
+{
+ struct sfdp_header *sfdp_h = (struct sfdp_header *)nor->sfdp->dwords;
+
+ /*
+ * W25QxxRV chips re-use the same ID as the W25QxxJV family.
+ *
+ * Chips are very similar, W25QxxRV brings mostly performance and power
+ * consumption improvements. The RV family does not require the multi
+ * die fixup.
+ *
+ * They can be distinguished based on their SFDP minor revision:
+ * W25QxxJV: JESD216A, minor revision == 05h
+ * W25Q512/01/02JV: JESD216B, minor revision == 06h
+ * W25QxxRV: JESD216F, minor revision >= 0Ah
+ */
+ return sfdp_h->minor >= SFDP_JESD216F_MINOR;
+}
+
+static bool winbond_jv_match(const struct spi_nor *nor)
+{
+ return !nor->sfdp || !is_w25qxxrv(nor);
+}
+
+static bool winbond_rv_match(const struct spi_nor *nor)
+{
+ return nor->sfdp && is_w25qxxrv(nor);
+}
+
static const struct flash_info winbond_nor_parts[] = {
{
.id = SNOR_ID(0xef, 0x30, 0x10),
@@ -552,9 +597,14 @@ static const struct spi_nor_fixup winbond_fixups[] = {
{ .fixups = &winbond_nor_fixups },
{ .id = SNOR_ID(0xef, 0x40, 0x18), .fixups = &w25q128_fixups },
{ .id = SNOR_ID(0xef, 0x40, 0x19), .fixups = &w25q256_fixups },
- { .id = SNOR_ID(0xef, 0x40, 0x21), .fixups = &winbond_nor_multi_die_fixups },
- { .id = SNOR_ID(0xef, 0x70, 0x21), .fixups = &winbond_nor_multi_die_fixups },
- { .id = SNOR_ID(0xef, 0x70, 0x22), .fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x40), .match = winbond_rv_match,
+ .fixups = &winbond_nor_partname_fixups },
+ { .id = SNOR_ID(0xef, 0x40, 0x21), .match = winbond_jv_match,
+ .fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x70, 0x21), .match = winbond_jv_match,
+ .fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x70, 0x22), .match = winbond_jv_match,
+ .fixups = &winbond_nor_multi_die_fixups },
};
const struct spi_nor_manufacturer spi_nor_winbond = {
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 08/23] mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-Q/N parts
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision between the JV and RV families. Both chips are
very similar in practice, it is mostly a matter of electrical
differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2 opcode
(0x31). They also do not require the multi-die fixups which must remain
assigned to the JV chips.
Finally, since they share the IDs but not the names, we must hide the
names using a fixup.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/winbond.c | 56 ++++++++++++++++++++++++++++++++++++++++---
1 file changed, 53 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 583b1669270f..8c1cad9e21b4 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -146,6 +146,51 @@ static const struct spi_nor_fixups winbond_nor_multi_die_fixups = {
.post_sfdp = winbond_nor_multi_die_post_sfdp_fixups,
};
+static int winbond_nor_partname_post_sfdp_fixups(struct spi_nor *nor)
+{
+ /*
+ * W25QxxRV parts re-use the JEDEC IDs of the JV family. Their name
+ * being a legacy field, it is kept for the already established JV parts
+ * but must not be exposed by the newer RV ones.
+ */
+ nor->partname = NULL;
+
+ return 0;
+}
+
+static const struct spi_nor_fixups winbond_nor_partname_fixups = {
+ .post_sfdp = winbond_nor_partname_post_sfdp_fixups,
+};
+
+static bool is_w25qxxrv(const struct spi_nor *nor)
+{
+ struct sfdp_header *sfdp_h = (struct sfdp_header *)nor->sfdp->dwords;
+
+ /*
+ * W25QxxRV chips re-use the same ID as the W25QxxJV family.
+ *
+ * Chips are very similar, W25QxxRV brings mostly performance and power
+ * consumption improvements. The RV family does not require the multi
+ * die fixup.
+ *
+ * They can be distinguished based on their SFDP minor revision:
+ * W25QxxJV: JESD216A, minor revision == 05h
+ * W25Q512/01/02JV: JESD216B, minor revision == 06h
+ * W25QxxRV: JESD216F, minor revision >= 0Ah
+ */
+ return sfdp_h->minor >= SFDP_JESD216F_MINOR;
+}
+
+static bool winbond_jv_match(const struct spi_nor *nor)
+{
+ return !nor->sfdp || !is_w25qxxrv(nor);
+}
+
+static bool winbond_rv_match(const struct spi_nor *nor)
+{
+ return nor->sfdp && is_w25qxxrv(nor);
+}
+
static const struct flash_info winbond_nor_parts[] = {
{
.id = SNOR_ID(0xef, 0x30, 0x10),
@@ -552,9 +597,14 @@ static const struct spi_nor_fixup winbond_fixups[] = {
{ .fixups = &winbond_nor_fixups },
{ .id = SNOR_ID(0xef, 0x40, 0x18), .fixups = &w25q128_fixups },
{ .id = SNOR_ID(0xef, 0x40, 0x19), .fixups = &w25q256_fixups },
- { .id = SNOR_ID(0xef, 0x40, 0x21), .fixups = &winbond_nor_multi_die_fixups },
- { .id = SNOR_ID(0xef, 0x70, 0x21), .fixups = &winbond_nor_multi_die_fixups },
- { .id = SNOR_ID(0xef, 0x70, 0x22), .fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x40), .match = winbond_rv_match,
+ .fixups = &winbond_nor_partname_fixups },
+ { .id = SNOR_ID(0xef, 0x40, 0x21), .match = winbond_jv_match,
+ .fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x70, 0x21), .match = winbond_jv_match,
+ .fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x70, 0x22), .match = winbond_jv_match,
+ .fixups = &winbond_nor_multi_die_fixups },
};
const struct spi_nor_manufacturer spi_nor_winbond = {
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 09/23] mtd: spi-nor: winbond: Add support for W25Q32RV-Q/N
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef4016
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0100ff00080117800000ffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f9ffffffff0144eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001432010183e314c2e96376337a757a75
f7a2d55c39f66dffe930f8800000000000002c0000000000f6f4ffff0f00
0000060d44bd27ed080d
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
2c0c54d6e360dae30b72615eac5f0faff59463aeb2237d46d08d6cfd77d6c9f6 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x03
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3b
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbb
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6b
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x02
1S-1S-4S
opcode 0x32
+ cat /sys/kernel/debug/spi-nor/spi0.0/p[ 84.112272] random: crng init done
arams
name (null)
id ef 40 16 00 00 00
size 4.00 MiB
write size 1
page size 256
address nbytes 3
flags HAS_SR_TB | HAS_LOCK | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xeb
dummy cycles 6
erase 0xd8
program 0x32
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
20 (4.00 KiB) [1]
52 (32.0 KiB) [2]
d8 (64.0 KiB) [3]
c7 (4.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-003fffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003fffff | unlocked | 64
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_read
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 4194304 (4M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x400000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_read
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003fffff | unlocked | 64
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x400000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_read
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_read
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_read2
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_test
831e9e5cc6efa7d3afe7b0584100549d93b9953d64ad237fd1df15f790f23ae6 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003fffff | locked | 64
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=4194304
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=64
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 4063232 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003dffff | unlocked | 62
003e0000-003fffff | locked | 2
+ flash_lock -u /dev/mtd0 4063232 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003effff | unlocked | 63
003f0000-003fffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-003fffff | unlocked | 62
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-003fffff | unlocked | 63
+ all_but_one=63
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 63
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-003fffff | locked | 63
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-003fffff | locked | 62
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 63
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003effff | locked | 63
003f0000-003fffff | unlocked | 1
+ flash_lock -u /dev/mtd0 4063232 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003dffff | locked | 62
003e0000-003fffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 8c1cad9e21b4..69c02732d5db 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -243,7 +243,7 @@ static const struct flash_info winbond_nor_parts[] = {
.size = SZ_1M,
.no_sfdp_flags = SECT_4K,
}, {
- /* W25Q32JV-Q/N */
+ /* W25Q32JV-Q/N, W25Q32RV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x16),
.name = "w25q32",
.size = SZ_4M,
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 09/23] mtd: spi-nor: winbond: Add support for W25Q32RV-Q/N
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef4016
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0100ff00080117800000ffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f9ffffffff0144eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001432010183e314c2e96376337a757a75
f7a2d55c39f66dffe930f8800000000000002c0000000000f6f4ffff0f00
0000060d44bd27ed080d
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
2c0c54d6e360dae30b72615eac5f0faff59463aeb2237d46d08d6cfd77d6c9f6 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x03
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3b
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbb
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6b
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x02
1S-1S-4S
opcode 0x32
+ cat /sys/kernel/debug/spi-nor/spi0.0/p[ 84.112272] random: crng init done
arams
name (null)
id ef 40 16 00 00 00
size 4.00 MiB
write size 1
page size 256
address nbytes 3
flags HAS_SR_TB | HAS_LOCK | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xeb
dummy cycles 6
erase 0xd8
program 0x32
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
20 (4.00 KiB) [1]
52 (32.0 KiB) [2]
d8 (64.0 KiB) [3]
c7 (4.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-003fffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003fffff | unlocked | 64
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_read
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 4194304 (4M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x400000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_read
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003fffff | unlocked | 64
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x400000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_read
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_read
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_read2
9f76d5d40e1d8fc620967a019cc0cf223a3b11cf9c5bed9a02fb8e2c06b1c805 spi_test
831e9e5cc6efa7d3afe7b0584100549d93b9953d64ad237fd1df15f790f23ae6 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003fffff | locked | 64
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=4194304
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=64
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 4063232 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003dffff | unlocked | 62
003e0000-003fffff | locked | 2
+ flash_lock -u /dev/mtd0 4063232 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003effff | unlocked | 63
003f0000-003fffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-003fffff | unlocked | 62
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-003fffff | unlocked | 63
+ all_but_one=63
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 63
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-003fffff | locked | 63
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-003fffff | locked | 62
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 63
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003effff | locked | 63
003f0000-003fffff | unlocked | 1
+ flash_lock -u /dev/mtd0 4063232 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003dffff | locked | 62
003e0000-003fffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 8c1cad9e21b4..69c02732d5db 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -243,7 +243,7 @@ static const struct flash_info winbond_nor_parts[] = {
.size = SZ_1M,
.no_sfdp_flags = SECT_4K,
}, {
- /* W25Q32JV-Q/N */
+ /* W25Q32JV-Q/N, W25Q32RV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x16),
.name = "w25q32",
.size = SZ_4M,
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 10/23] mtd: spi-nor: winbond: Add support for W25Q64RV-Q/N
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef4017
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f3ffffffff0344eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d80000d639a50081d614c3e96376337a757a75
f7a4d55c39de6dffe970f9a50000000000002c000000000066ffffff0000
00000000000000000000ffffffffff0a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
c7fa99bdcdef9a930e609215704dd349dbed161487dee0ece8ea1b25d2d4dd25 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 40 17 00 00 00
size 8.00 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (8.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-007fffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 7.803395] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_read
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 8388608 (8M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_read
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_read
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_read
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_read2
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_test
64f4a5c5a05eae4a6dffb9e76171d97328257a96110214f52222870681b7b28c spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | locked | 64
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=8388608
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=64
+ ss=131072
+ bps=2
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 8126464 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | unlocked | 62
007c0000-007fffff | locked | 2
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | unlocked | 63
007e0000-007fffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | locked | 2
00040000-007fffff | unlocked | 62
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 1
00020000-007fffff | unlocked | 63
+ all_but_one=126
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 131072 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 1
00020000-007fffff | locked | 63
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | unlocked | 2
00040000-007fffff | locked | 62
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | locked | 63
007e0000-007fffff | unlocked | 1
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | locked | 62
007c0000-007fffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 69c02732d5db..24f3ff52427b 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -250,7 +250,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q64JV-Q/N */
+ /* W25Q64JV-Q/N, W25Q64RV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x17),
.name = "w25q64",
.size = SZ_8M,
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 10/23] mtd: spi-nor: winbond: Add support for W25Q64RV-Q/N
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef4017
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f3ffffffff0344eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d80000d639a50081d614c3e96376337a757a75
f7a4d55c39de6dffe970f9a50000000000002c000000000066ffffff0000
00000000000000000000ffffffffff0a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
c7fa99bdcdef9a930e609215704dd349dbed161487dee0ece8ea1b25d2d4dd25 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 40 17 00 00 00
size 8.00 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (8.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-007fffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 7.803395] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_read
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 8388608 (8M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_read
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_read
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_read
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_read2
eca2ec05a4fbf9f14490a0147e43c8f3616298bf8f6e2b59f5c5e5076c1cfd02 spi_test
64f4a5c5a05eae4a6dffb9e76171d97328257a96110214f52222870681b7b28c spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | locked | 64
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=8388608
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=64
+ ss=131072
+ bps=2
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 8126464 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | unlocked | 62
007c0000-007fffff | locked | 2
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | unlocked | 63
007e0000-007fffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | locked | 2
00040000-007fffff | unlocked | 62
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 1
00020000-007fffff | unlocked | 63
+ all_but_one=126
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 131072 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 1
00020000-007fffff | locked | 63
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | unlocked | 2
00040000-007fffff | locked | 62
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | locked | 63
007e0000-007fffff | unlocked | 1
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | locked | 62
007c0000-007fffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 69c02732d5db..24f3ff52427b 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -250,7 +250,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q64JV-Q/N */
+ /* W25Q64JV-Q/N, W25Q64RV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x17),
.name = "w25q64",
.size = SZ_8M,
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 11/23] mtd: spi-nor: winbond: Add support for W25Q12RV-Q/N
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef4018
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0100ff00080117800000ffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f9ffffffff0344eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d80000142a010186e114c1e96376337a757a75
f7a2d55c39f66dffe930f880000000000000ac0000000000f7f5ffff0f00
0000060d44bd27ed080d
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
94b52d6e903a2046e144eab0760384b6932c6fdbfec17eb7336f1778c3898daf /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x03
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3b
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbb
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6b
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x02
1S-1S-4S
opcode 0x32
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 40 18 00 00 00
size 8.00 MiB
write size 1
page size 256
address nbytes 3
flags HAS_SR_TB | HAS_LOCK | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xeb
dummy cycles 6
erase 0xd8
program 0x32
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
20 (4.00 KiB) [1]
52 (32.0 KiB) [2]
d8 (64.0 KiB) [3]
c7 (8.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-007fffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 15.791564] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_read
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 8388608 (8M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_read
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_read
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_read
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_read2
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_test
884cedd0494868db17c609edc62e2471ef344025e30cd511fa28b41b9b50e50d spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | locked | 64
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=8388608
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=64
+ ss=131072
+ bps=2
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 8126464 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | unlocked | 62
007c0000-007fffff | locked | 2
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | unlocked | 63
007e0000-007fffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | locked | 2
00040000-007fffff | unlocked | 62
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 1
00020000-007fffff | unlocked | 63
+ all_but_one=126
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 131072 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 1
00020000-007fffff | locked | 63
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | unlocked | 2
00040000-007fffff | locked | 62
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | locked | 63
007e0000-007fffff | unlocked | 1
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | locked | 62
007c0000-007fffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 24f3ff52427b..568dc05d3c25 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -257,7 +257,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q128JV-Q/N */
+ /* W25Q128JV-Q/N, W25Q12RV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x18),
/* Flavors w/ and w/o SFDP. */
.name = "w25q128",
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 11/23] mtd: spi-nor: winbond: Add support for W25Q12RV-Q/N
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef4018
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0100ff00080117800000ffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f9ffffffff0344eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d80000142a010186e114c1e96376337a757a75
f7a2d55c39f66dffe930f880000000000000ac0000000000f7f5ffff0f00
0000060d44bd27ed080d
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
94b52d6e903a2046e144eab0760384b6932c6fdbfec17eb7336f1778c3898daf /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x03
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3b
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbb
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6b
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x02
1S-1S-4S
opcode 0x32
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 40 18 00 00 00
size 8.00 MiB
write size 1
page size 256
address nbytes 3
flags HAS_SR_TB | HAS_LOCK | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xeb
dummy cycles 6
erase 0xd8
program 0x32
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
20 (4.00 KiB) [1]
52 (32.0 KiB) [2]
d8 (64.0 KiB) [3]
c7 (8.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-007fffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 15.791564] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_read
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 8388608 (8M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_read
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_read
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_read
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_read2
b3260b68e0373cd253fc558fa9a5c89009d3edb2393f4110702318f69a6d74c2 spi_test
884cedd0494868db17c609edc62e2471ef344025e30cd511fa28b41b9b50e50d spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | locked | 64
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=8388608
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=64
+ ss=131072
+ bps=2
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 8126464 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | unlocked | 62
007c0000-007fffff | locked | 2
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | unlocked | 63
007e0000-007fffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | locked | 2
00040000-007fffff | unlocked | 62
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 1
00020000-007fffff | unlocked | 63
+ all_but_one=126
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 131072 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 1
00020000-007fffff | locked | 63
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | unlocked | 2
00040000-007fffff | locked | 62
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | locked | 63
007e0000-007fffff | unlocked | 1
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | locked | 62
007c0000-007fffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 24f3ff52427b..568dc05d3c25 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -257,7 +257,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q128JV-Q/N */
+ /* W25Q128JV-Q/N, W25Q12RV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x18),
/* Flavors w/ and w/o SFDP. */
.name = "w25q128",
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 12/23] mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef4020
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f3ffffffff1f44eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001602a60081e214dde96376337a757a75
f7a4d55c39f66dffe970f9a50000000000002c0c0000000066ffffff0000
00000000000000000000ffffffffff0a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
74d21fecc7faa297b3f77f1136b1dc53f78b2a432629e226675b6384153fd9f9 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 40 20 00 00 00
size 64.0 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (64.0 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-03ffffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | unlocked | 1024
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 25.427347] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 67108864 (64M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x4000000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | unlocked | 1024
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x4000000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read2
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test
f506020804f91fb750e8250e091fb2f732319221a645ed575e1b6ed3553d584c spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | locked | 1024
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=67108864
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=1024
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 66977792 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03fdffff | unlocked | 1022
03fe0000-03ffffff | locked | 2
+ flash_lock -u /dev/mtd0 66977792 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03feffff | unlocked | 1023
03ff0000-03ffffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 58720256 128
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-037fffff | unlocked | 896
03800000-03ffffff | locked | 128
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-03ffffff | unlocked | 1022
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-03ffffff | unlocked | 1023
+ all_but_one=1023
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 1023
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-03ffffff | locked | 1023
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-03ffffff | locked | 1022
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 1023
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03feffff | locked | 1023
03ff0000-03ffffff | unlocked | 1
+ flash_lock -u /dev/mtd0 66977792 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03fdffff | locked | 1022
03fe0000-03ffffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 568dc05d3c25..47a5c2cf71de 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -273,7 +273,7 @@ static const struct flash_info winbond_nor_parts[] = {
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
- /* W25Q512JV-Q/N */
+ /* W25Q512JV-Q/N, W25Q51RV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x20),
.name = "w25q512jvq",
.size = SZ_64M,
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 12/23] mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef4020
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f3ffffffff1f44eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001602a60081e214dde96376337a757a75
f7a4d55c39f66dffe970f9a50000000000002c0c0000000066ffffff0000
00000000000000000000ffffffffff0a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
74d21fecc7faa297b3f77f1136b1dc53f78b2a432629e226675b6384153fd9f9 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 40 20 00 00 00
size 64.0 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (64.0 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-03ffffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | unlocked | 1024
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 25.427347] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 67108864 (64M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x4000000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | unlocked | 1024
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x4000000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_read2
cd699acc82353b7769b98547efed68d5300854ed0bbc84bf831b07937bf941a5 spi_test
f506020804f91fb750e8250e091fb2f732319221a645ed575e1b6ed3553d584c spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | locked | 1024
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=67108864
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=1024
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 66977792 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03fdffff | unlocked | 1022
03fe0000-03ffffff | locked | 2
+ flash_lock -u /dev/mtd0 66977792 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03feffff | unlocked | 1023
03ff0000-03ffffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 58720256 128
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-037fffff | unlocked | 896
03800000-03ffffff | locked | 128
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-03ffffff | unlocked | 1022
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-03ffffff | unlocked | 1023
+ all_but_one=1023
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 1023
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-03ffffff | locked | 1023
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-03ffffff | locked | 1022
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 1023
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03feffff | locked | 1023
03ff0000-03ffffff | unlocked | 1
+ flash_lock -u /dev/mtd0 66977792 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03fdffff | locked | 1022
03fe0000-03ffffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 568dc05d3c25..47a5c2cf71de 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -273,7 +273,7 @@ static const struct flash_info winbond_nor_parts[] = {
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
- /* W25Q512JV-Q/N */
+ /* W25Q512JV-Q/N, W25Q51RV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x20),
.name = "w25q512jvq",
.size = SZ_64M,
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 13/23] mtd: spi-nor: winbond: Add support for W25Q01RV-Q/N
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef4020
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f3ffffffff1f44eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001602a60081e214dde96376337a757a75
f7a4d55c39f66dffe970f9a50000000000002c0c0000000066ffffff0000
00000000000000000000ffffffffff0a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
74d21fecc7faa297b3f77f1136b1dc53f78b2a432629e226675b6384153fd9f9 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 40 20 00 00 00
size 64.0 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (64.0 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-03ffffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | unlocked | 1024
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_read
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 67108864 (64M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x4000000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_read
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | unlocked | 1024
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x4000000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_read
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_read
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_read2
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_test
643412dbe0f46c2780ec8d4f609d369923829945f4bc3d7842138b2fbbc86046 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | locked | 1024
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=67108864
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=1024
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 66977792 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03fdffff | unlocked | 1022
03fe0000-03ffffff | locked | 2
+ flash_lock -u /dev/mtd0 66977792 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03feffff | unlocked | 1023
03ff0000-03ffffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 58720256 128
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-037fffff | unlocked | 896
03800000-03ffffff | locked | 128
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-03ffffff | unlocked | 1022
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-03ffffff | unlocked | 1023
+ all_but_one=1023
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 1023
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-03ffffff | locked | 1023
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-03ffffff | locked | 1022
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 1023
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03feffff | locked | 1023
03ff0000-03ffffff | unlocked | 1
+ flash_lock -u /dev/mtd0 66977792 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03fdffff | locked | 1022
03fe0000-03ffffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 47a5c2cf71de..1c67a652ddcd 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -281,7 +281,7 @@ static const struct flash_info winbond_nor_parts[] = {
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
- /* W25Q01JV-Q/N */
+ /* W25Q01JV-Q/N, W25Q01RV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x21),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 13/23] mtd: spi-nor: winbond: Add support for W25Q01RV-Q/N
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef4020
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f3ffffffff1f44eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001602a60081e214dde96376337a757a75
f7a4d55c39f66dffe970f9a50000000000002c0c0000000066ffffff0000
00000000000000000000ffffffffff0a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
74d21fecc7faa297b3f77f1136b1dc53f78b2a432629e226675b6384153fd9f9 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 40 20 00 00 00
size 64.0 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (64.0 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-03ffffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | unlocked | 1024
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_read
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 67108864 (64M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x4000000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_read
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | unlocked | 1024
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x4000000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_read
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_read
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_read2
950cbc701e7f6ed69837b30bbf4145fe776e6c07a7bc5b8f346d42242bdd7a63 spi_test
643412dbe0f46c2780ec8d4f609d369923829945f4bc3d7842138b2fbbc86046 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | locked | 1024
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=67108864
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=1024
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 66977792 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03fdffff | unlocked | 1022
03fe0000-03ffffff | locked | 2
+ flash_lock -u /dev/mtd0 66977792 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03feffff | unlocked | 1023
03ff0000-03ffffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 58720256 128
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-037fffff | unlocked | 896
03800000-03ffffff | locked | 128
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-03ffffff | unlocked | 1022
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-03ffffff | unlocked | 1023
+ all_but_one=1023
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 1023
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-03ffffff | locked | 1023
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-03ffffff | locked | 1022
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 1023
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03feffff | locked | 1023
03ff0000-03ffffff | unlocked | 1
+ flash_lock -u /dev/mtd0 66977792 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03fdffff | locked | 1022
03fe0000-03ffffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 47a5c2cf71de..1c67a652ddcd 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -281,7 +281,7 @@ static const struct flash_info winbond_nor_parts[] = {
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
- /* W25Q01JV-Q/N */
+ /* W25Q01JV-Q/N, W25Q01RV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x21),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 14/23] mtd: spi-nor: winbond: Add support for W25Q02RV-Q/N
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef4022
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f3ffffffff7f44eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001602a60081e214dde9e378477a757a75
f7a4d55c39f66dffe970f9a50000000000002c0c0000000066ffffff0000
00000000000000000000ffffffffff0a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
623c2663966d70cc6418f65db6c182a7d9146e15b190263f46ea81d9a934866c /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 40 22 00 00 00
size 256 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
SR1 read 0x05
SR2 read 0x35
SR1 write 0x01
SR2 write 0x31
QE SR2 bit 1
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (256 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-0fffffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0fffffff | unlocked | 4096
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 14.840645] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_read
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 268435456 (256M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x10000000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_read
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0fffffff | unlocked | 4096
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x10000000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_read
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_read
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_read2
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_test
28e04c28384aafd356a3e545ba79bf02e995cfb1e765ec663e35924c3f92b88d spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0fffffff | locked | 4096
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=268435456
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=4096
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 268304384 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffdffff | unlocked | 4094
0ffe0000-0fffffff | locked | 2
+ flash_lock -u /dev/mtd0 268304384 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffeffff | unlocked | 4095
0fff0000-0fffffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 260046848 128
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0f7fffff | unlocked | 3968
0f800000-0fffffff | locked | 128
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-0fffffff | unlocked | 4094
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-0fffffff | unlocked | 4095
+ all_but_one=4095
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 4095
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-0fffffff | locked | 4095
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-0fffffff | locked | 4094
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 4095
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffeffff | locked | 4095
0fff0000-0fffffff | unlocked | 1
+ flash_lock -u /dev/mtd0 268304384 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffdffff | locked | 4094
0ffe0000-0fffffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 1c67a652ddcd..055c5833f687 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -285,6 +285,11 @@ static const struct flash_info winbond_nor_parts[] = {
.id = SNOR_ID(0xef, 0x40, 0x21),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
+ }, {
+ /* W25Q02RV-Q/N */
+ .id = SNOR_ID(0xef, 0x40, 0x22),
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
+ SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
.id = SNOR_ID(0xef, 0x50, 0x12),
.name = "w25q20bw",
@@ -601,6 +606,8 @@ static const struct spi_nor_fixup winbond_fixups[] = {
.fixups = &winbond_nor_partname_fixups },
{ .id = SNOR_ID(0xef, 0x40, 0x21), .match = winbond_jv_match,
.fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x40, 0x22), .match = winbond_jv_match,
+ .fixups = &winbond_nor_multi_die_fixups },
{ .id = SNOR_ID(0xef, 0x70, 0x21), .match = winbond_jv_match,
.fixups = &winbond_nor_multi_die_fixups },
{ .id = SNOR_ID(0xef, 0x70, 0x22), .match = winbond_jv_match,
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 14/23] mtd: spi-nor: winbond: Add support for W25Q02RV-Q/N
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef4022
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f3ffffffff7f44eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001602a60081e214dde9e378477a757a75
f7a4d55c39f66dffe970f9a50000000000002c0c0000000066ffffff0000
00000000000000000000ffffffffff0a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
623c2663966d70cc6418f65db6c182a7d9146e15b190263f46ea81d9a934866c /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 40 22 00 00 00
size 256 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
SR1 read 0x05
SR2 read 0x35
SR1 write 0x01
SR2 write 0x31
QE SR2 bit 1
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (256 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-0fffffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0fffffff | unlocked | 4096
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 14.840645] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_read
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 268435456 (256M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x10000000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_read
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0fffffff | unlocked | 4096
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x10000000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_read
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_read
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_read2
c1c18ff55582ccab09e88cd6e6c14fe46c601c6461cb0012ac79949615f6c682 spi_test
28e04c28384aafd356a3e545ba79bf02e995cfb1e765ec663e35924c3f92b88d spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0fffffff | locked | 4096
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=268435456
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=4096
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 268304384 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffdffff | unlocked | 4094
0ffe0000-0fffffff | locked | 2
+ flash_lock -u /dev/mtd0 268304384 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffeffff | unlocked | 4095
0fff0000-0fffffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 260046848 128
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0f7fffff | unlocked | 3968
0f800000-0fffffff | locked | 128
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-0fffffff | unlocked | 4094
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-0fffffff | unlocked | 4095
+ all_but_one=4095
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 4095
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-0fffffff | locked | 4095
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-0fffffff | locked | 4094
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 4095
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffeffff | locked | 4095
0fff0000-0fffffff | unlocked | 1
+ flash_lock -u /dev/mtd0 268304384 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffdffff | locked | 4094
0ffe0000-0fffffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 1c67a652ddcd..055c5833f687 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -285,6 +285,11 @@ static const struct flash_info winbond_nor_parts[] = {
.id = SNOR_ID(0xef, 0x40, 0x21),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
+ }, {
+ /* W25Q02RV-Q/N */
+ .id = SNOR_ID(0xef, 0x40, 0x22),
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
+ SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
.id = SNOR_ID(0xef, 0x50, 0x12),
.name = "w25q20bw",
@@ -601,6 +606,8 @@ static const struct spi_nor_fixup winbond_fixups[] = {
.fixups = &winbond_nor_partname_fixups },
{ .id = SNOR_ID(0xef, 0x40, 0x21), .match = winbond_jv_match,
.fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x40, 0x22), .match = winbond_jv_match,
+ .fixups = &winbond_nor_multi_die_fixups },
{ .id = SNOR_ID(0xef, 0x70, 0x21), .match = winbond_jv_match,
.fixups = &winbond_nor_multi_die_fixups },
{ .id = SNOR_ID(0xef, 0x70, 0x22), .match = winbond_jv_match,
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 15/23] mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-M parts
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision between the JV and RV families. Both chips are
very similar in practice, it is mostly a matter of electrical
differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
The new SFDP (rev F) field which forces an alternate write SR2 opcode
(0x31).
Since they share the IDs but not the names, we must hide the names using
a fixup.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/winbond.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 055c5833f687..b86458b22838 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -608,6 +608,8 @@ static const struct spi_nor_fixup winbond_fixups[] = {
.fixups = &winbond_nor_multi_die_fixups },
{ .id = SNOR_ID(0xef, 0x40, 0x22), .match = winbond_jv_match,
.fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x70), .match = winbond_rv_match,
+ .fixups = &winbond_nor_partname_fixups },
{ .id = SNOR_ID(0xef, 0x70, 0x21), .match = winbond_jv_match,
.fixups = &winbond_nor_multi_die_fixups },
{ .id = SNOR_ID(0xef, 0x70, 0x22), .match = winbond_jv_match,
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 15/23] mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-M parts
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision between the JV and RV families. Both chips are
very similar in practice, it is mostly a matter of electrical
differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
The new SFDP (rev F) field which forces an alternate write SR2 opcode
(0x31).
Since they share the IDs but not the names, we must hide the names using
a fixup.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/winbond.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 055c5833f687..b86458b22838 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -608,6 +608,8 @@ static const struct spi_nor_fixup winbond_fixups[] = {
.fixups = &winbond_nor_multi_die_fixups },
{ .id = SNOR_ID(0xef, 0x40, 0x22), .match = winbond_jv_match,
.fixups = &winbond_nor_multi_die_fixups },
+ { .id = SNOR_ID(0xef, 0x70), .match = winbond_rv_match,
+ .fixups = &winbond_nor_partname_fixups },
{ .id = SNOR_ID(0xef, 0x70, 0x21), .match = winbond_jv_match,
.fixups = &winbond_nor_multi_die_fixups },
{ .id = SNOR_ID(0xef, 0x70, 0x22), .match = winbond_jv_match,
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 16/23] mtd: spi-nor: winbond: Add support for W25Q32RV-M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef7016
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0100ff00080117800000ffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f9ffffffff0144eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001432010183e314c2e96376337a757a75
f7a2d55c39f66dffe930f8800000000000002c0000000000f6f4ffff0f00
0000060d44bd27ed080d
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
2c0c54d6e360dae30b72615eac5f0faff59463aeb2237d46d08d6cfd77d6c9f6 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x03
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3b
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbb
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6b
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x02
1S-1S-4S
opcode 0x32
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 70 16 00 00 00
size 4.00 MiB
write size 1
page size 256
address nbytes 3
flags HAS_SR_TB | HAS_LOCK | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xeb
dummy cycles 6
erase 0xd8
program 0x32
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
20 (4.00 KiB) [1]
52 (32.0 KiB) [2]
d8 (64.0 KiB) [3]
c7 (4.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-003fffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003fffff | unlocked | 64
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 15.820716] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_read
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 4194304 (4M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x400000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_read
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003fffff | unlocked | 64
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x400000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_read
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_read
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_read2
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_test
d26d11f7de825c1f2397e52307997c9befb07b93e6cd520d15a87d06abef2529 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003fffff | locked | 64
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=4194304
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=64
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 4063232 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003dffff | unlocked | 62
003e0000-003fffff | locked | 2
+ flash_lock -u /dev/mtd0 4063232 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003effff | unlocked | 63
003f0000-003fffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-003fffff | unlocked | 62
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-003fffff | unlocked | 63
+ all_but_one=63
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 63
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-003fffff | locked | 63
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-003fffff | locked | 62
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 63
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003effff | locked | 63
003f0000-003fffff | unlocked | 1
+ flash_lock -u /dev/mtd0 4063232 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003dffff | locked | 62
003e0000-003fffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index b86458b22838..3fe0af416178 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -356,7 +356,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q32JV-M */
+ /* W25Q32JV-M, W25Q32RV-M */
.id = SNOR_ID(0xef, 0x70, 0x16),
.name = "w25q32jv",
.size = SZ_4M,
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 16/23] mtd: spi-nor: winbond: Add support for W25Q32RV-M
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef7016
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0100ff00080117800000ffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f9ffffffff0144eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001432010183e314c2e96376337a757a75
f7a2d55c39f66dffe930f8800000000000002c0000000000f6f4ffff0f00
0000060d44bd27ed080d
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
2c0c54d6e360dae30b72615eac5f0faff59463aeb2237d46d08d6cfd77d6c9f6 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x03
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3b
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbb
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6b
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x02
1S-1S-4S
opcode 0x32
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 70 16 00 00 00
size 4.00 MiB
write size 1
page size 256
address nbytes 3
flags HAS_SR_TB | HAS_LOCK | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xeb
dummy cycles 6
erase 0xd8
program 0x32
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
20 (4.00 KiB) [1]
52 (32.0 KiB) [2]
d8 (64.0 KiB) [3]
c7 (4.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-003fffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003fffff | unlocked | 64
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 15.820716] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_read
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 4194304 (4M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x400000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_read
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003fffff | unlocked | 64
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x400000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_read
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_read
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_read2
c73e2828631d8f745c118e706e4ea7179328e6e03e49cb2d30784eb73ff6167f spi_test
d26d11f7de825c1f2397e52307997c9befb07b93e6cd520d15a87d06abef2529 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003fffff | locked | 64
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=4194304
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=64
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 4063232 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003dffff | unlocked | 62
003e0000-003fffff | locked | 2
+ flash_lock -u /dev/mtd0 4063232 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003effff | unlocked | 63
003f0000-003fffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-003fffff | unlocked | 62
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-003fffff | unlocked | 63
+ all_but_one=63
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 63
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-003fffff | locked | 63
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-003fffff | locked | 62
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 63
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003effff | locked | 63
003f0000-003fffff | unlocked | 1
+ flash_lock -u /dev/mtd0 4063232 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-003dffff | locked | 62
003e0000-003fffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index b86458b22838..3fe0af416178 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -356,7 +356,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q32JV-M */
+ /* W25Q32JV-M, W25Q32RV-M */
.id = SNOR_ID(0xef, 0x70, 0x16),
.name = "w25q32jv",
.size = SZ_4M,
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 17/23] mtd: spi-nor: winbond: Add support for W25Q64RV-M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef7017
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520fbffffffff0344eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d80000d639a50081d614c3e96376337a757a75
f7a4d55c39de6dffe970f9a50000000000002c00000000006655ffff0f00
0000060d44bd27ed080dffffffffff8a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
ef6c5eb61fa86c6daac85436446b97ca078a46e4cfd4c0fed4c9f9400d79fa86 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 70 17 00 00 00
size 8.00 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (8.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-007fffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 15.931750] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_read
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 8388608 (8M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_read
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_read
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_read
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_read2
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_test
154432cc7e89d18c1e4ddb1604dfd2a0038c75aa5521a74808944ce19a320a42 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | locked | 64
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=8388608
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=64
+ ss=131072
+ bps=2
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 8126464 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | unlocked | 62
007c0000-007fffff | locked | 2
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | unlocked | 63
007e0000-007fffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | locked | 2
00040000-007fffff | unlocked | 62
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 1
00020000-007fffff | unlocked | 63
+ all_but_one=126
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 131072 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 1
00020000-007fffff | locked | 63
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | unlocked | 2
00040000-007fffff | locked | 62
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | locked | 63
007e0000-007fffff | unlocked | 1
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | locked | 62
007c0000-007fffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 3fe0af416178..3019258bf65e 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -363,7 +363,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q64JV-M */
+ /* W25Q64JV-M, W25Q64RV-M */
.id = SNOR_ID(0xef, 0x70, 0x17),
.name = "w25q64jvm",
.size = SZ_8M,
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 17/23] mtd: spi-nor: winbond: Add support for W25Q64RV-M
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef7017
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520fbffffffff0344eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d80000d639a50081d614c3e96376337a757a75
f7a4d55c39de6dffe970f9a50000000000002c00000000006655ffff0f00
0000060d44bd27ed080dffffffffff8a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
ef6c5eb61fa86c6daac85436446b97ca078a46e4cfd4c0fed4c9f9400d79fa86 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 70 17 00 00 00
size 8.00 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (8.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-007fffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 15.931750] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_read
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 8388608 (8M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_read
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_read
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_read
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_read2
d4a37ad2760e69823409d7e9321471b7f7ed6728d40f7f15329921fbe7393db6 spi_test
154432cc7e89d18c1e4ddb1604dfd2a0038c75aa5521a74808944ce19a320a42 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | locked | 64
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=8388608
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=64
+ ss=131072
+ bps=2
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 8126464 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | unlocked | 62
007c0000-007fffff | locked | 2
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | unlocked | 63
007e0000-007fffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | locked | 2
00040000-007fffff | unlocked | 62
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 1
00020000-007fffff | unlocked | 63
+ all_but_one=126
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 131072 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 1
00020000-007fffff | locked | 63
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | unlocked | 2
00040000-007fffff | locked | 62
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | locked | 63
007e0000-007fffff | unlocked | 1
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | locked | 62
007c0000-007fffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 3fe0af416178..3019258bf65e 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -363,7 +363,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q64JV-M */
+ /* W25Q64JV-M, W25Q64RV-M */
.id = SNOR_ID(0xef, 0x70, 0x17),
.name = "w25q64jvm",
.size = SZ_8M,
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 18/23] mtd: spi-nor: winbond: Add support for W25Q12RV-M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef7018
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0100ff00080117800000ffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f9ffffffff0344eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d80000142a010186e114c1e96376337a757a75
f7a2d55c39f66dffe930f880000000000000ac0000000000f7f5ffff0f00
0000060d44bd27ed080d
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
94b52d6e903a2046e144eab0760384b6932c6fdbfec17eb7336f1778c3898daf /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x03
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3b
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbb
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6b
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x02
1S-1S-4S
opcode 0x32
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 70 18 00 00 00
size 8.00 MiB
write size 1
page size 256
address nbytes 3
flags HAS_SR_TB | HAS_LOCK | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xeb
dummy cycles 6
erase 0xd8
program 0x32
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
20 (4.00 KiB) [1]
52 (32.0 KiB) [2]
d8 (64.0 KiB) [3]
c7 (8.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-007fffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 28.249430] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_read
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 8388608 (8M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_read
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_read
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_read
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_read2
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_test
df6c52ecc59473c5ed9bd10a0479b52ee248adbf7d032aa7cde35e86acd461ca spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | locked | 64
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=8388608
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=64
+ ss=131072
+ bps=2
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 8126464 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | unlocked | 62
007c0000-007fffff | locked | 2
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | unlocked | 63
007e0000-007fffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | locked | 2
00040000-007fffff | unlocked | 62
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 1
00020000-007fffff | unlocked | 63
+ all_but_one=126
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 131072 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 1
00020000-007fffff | locked | 63
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | unlocked | 2
00040000-007fffff | locked | 62
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | locked | 63
007e0000-007fffff | unlocked | 1
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | locked | 62
007c0000-007fffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 3019258bf65e..b661e2c56474 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -370,7 +370,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q128JV-M */
+ /* W25Q128JV-M, W25Q12RV-M */
.id = SNOR_ID(0xef, 0x70, 0x18),
.name = "w25q128jv",
.size = SZ_16M,
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 18/23] mtd: spi-nor: winbond: Add support for W25Q12RV-M
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef7018
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0100ff00080117800000ffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520f9ffffffff0344eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d80000142a010186e114c1e96376337a757a75
f7a2d55c39f66dffe930f880000000000000ac0000000000f7f5ffff0f00
0000060d44bd27ed080d
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
94b52d6e903a2046e144eab0760384b6932c6fdbfec17eb7336f1778c3898daf /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x03
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3b
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbb
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6b
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xeb
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x02
1S-1S-4S
opcode 0x32
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 70 18 00 00 00
size 8.00 MiB
write size 1
page size 256
address nbytes 3
flags HAS_SR_TB | HAS_LOCK | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xeb
dummy cycles 6
erase 0xd8
program 0x32
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
20 (4.00 KiB) [1]
52 (32.0 KiB) [2]
d8 (64.0 KiB) [3]
c7 (8.00 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-007fffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 28.249430] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_read
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 8388608 (8M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_read
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | unlocked | 64
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x800000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_read
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_read
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_read2
48b1df493c0c35b1c6c8a50880c6e10adcd103c383a7324033cb760d20d9acf0 spi_test
df6c52ecc59473c5ed9bd10a0479b52ee248adbf7d032aa7cde35e86acd461ca spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007fffff | locked | 64
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=8388608
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=64
+ ss=131072
+ bps=2
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 8126464 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | unlocked | 62
007c0000-007fffff | locked | 2
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | unlocked | 63
007e0000-007fffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 4
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | locked | 2
00040000-007fffff | unlocked | 62
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 1
00020000-007fffff | unlocked | 63
+ all_but_one=126
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 131072 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 1
00020000-007fffff | locked | 63
+ flash_lock -u /dev/mtd0 131072 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0003ffff | unlocked | 2
00040000-007fffff | locked | 62
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 126
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007dffff | locked | 63
007e0000-007fffff | unlocked | 1
+ flash_lock -u /dev/mtd0 8126464 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-007bffff | locked | 62
007c0000-007fffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 3019258bf65e..b661e2c56474 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -370,7 +370,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q128JV-M */
+ /* W25Q128JV-M, W25Q12RV-M */
.id = SNOR_ID(0xef, 0x70, 0x18),
.name = "w25q128jv",
.size = SZ_16M,
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 19/23] mtd: spi-nor: winbond: Add support for W25Q51RV-M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef7020
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520fbffffffff1f44eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001602a60081e214dde96376337a757a75
f7a4d55c39f66dffe970f9a50000000000002c0c000000006655ffff0f00
0000060d44bd27ed080dffffffffff8a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
d74b1b27fa4e5b8fba7db8fcac198bfe5a28c5e17a565d5e694a6b8d21b62104 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 70 20 00 00 00
size 64.0 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
SR1 read 0x05
SR2 read 0x35
SR1 write 0x01
SR2 write 0x31
QE SR2 bit 1
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (64.0 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-03ffffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | unlocked | 1024
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_read
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 67108864 (64M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x4000000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_read
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | unlocked | 1024
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x4000000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_read
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_read
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_read2
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_test
12582dd4eecd173d184b51b0281065e10062901d66d0f6b1709f4240227b81a9 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | locked | 1024
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=67108864
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=1024
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 66977792 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03fdffff | unlocked | 1022
03fe0000-03ffffff | locked | 2
+ flash_lock -u /dev/mtd0 66977792 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03feffff | unlocked | 1023
03ff0000-03ffffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 58720256 128
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-037fffff | unlocked | 896
03800000-03ffffff | locked | 128
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-03ffffff | unlocked | 1022
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-03ffffff | unlocked | 1023
+ all_but_one=1023
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 1023
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-03ffffff | locked | 1023
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-03ffffff | locked | 1022
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 1023
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03feffff | locked | 1023
03ff0000-03ffffff | unlocked | 1
+ flash_lock -u /dev/mtd0 66977792 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03fdffff | locked | 1022
03fe0000-03ffffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index b661e2c56474..fc9e84e500c5 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -383,7 +383,7 @@ static const struct flash_info winbond_nor_parts[] = {
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
- /* W25Q512JV-M */
+ /* W25Q512JV-M, W25Q51RV-M */
.id = SNOR_ID(0xef, 0x70, 0x20),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 19/23] mtd: spi-nor: winbond: Add support for W25Q51RV-M
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef7020
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520fbffffffff1f44eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001602a60081e214dde96376337a757a75
f7a4d55c39f66dffe970f9a50000000000002c0c000000006655ffff0f00
0000060d44bd27ed080dffffffffff8a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
d74b1b27fa4e5b8fba7db8fcac198bfe5a28c5e17a565d5e694a6b8d21b62104 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 70 20 00 00 00
size 64.0 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
SR1 read 0x05
SR2 read 0x35
SR1 write 0x01
SR2 write 0x31
QE SR2 bit 1
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (64.0 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-03ffffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | unlocked | 1024
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_read
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 67108864 (64M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x4000000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_read
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | unlocked | 1024
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x4000000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_read
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_read
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_read2
640094386802e8c1ddca74f4f4848140736a1b275dfc5a2cefbd7f6acd0e6727 spi_test
12582dd4eecd173d184b51b0281065e10062901d66d0f6b1709f4240227b81a9 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03ffffff | locked | 1024
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=67108864
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=1024
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 66977792 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03fdffff | unlocked | 1022
03fe0000-03ffffff | locked | 2
+ flash_lock -u /dev/mtd0 66977792 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03feffff | unlocked | 1023
03ff0000-03ffffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 58720256 128
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-037fffff | unlocked | 896
03800000-03ffffff | locked | 128
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-03ffffff | unlocked | 1022
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-03ffffff | unlocked | 1023
+ all_but_one=1023
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 1023
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-03ffffff | locked | 1023
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-03ffffff | locked | 1022
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 1023
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03feffff | locked | 1023
03ff0000-03ffffff | unlocked | 1
+ flash_lock -u /dev/mtd0 66977792 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-03fdffff | locked | 1022
03fe0000-03ffffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index b661e2c56474..fc9e84e500c5 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -383,7 +383,7 @@ static const struct flash_info winbond_nor_parts[] = {
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
- /* W25Q512JV-M */
+ /* W25Q512JV-M, W25Q51RV-M */
.id = SNOR_ID(0xef, 0x70, 0x20),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 20/23] mtd: spi-nor: winbond: Add support for W25Q01RV-M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef7021
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520fbffffffff3f44eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001602a60081e214dde9e378477a757a75
f7a4d55c39f66dffe970f9a50000000000002c0c000000006655ffff0f00
0000060d44bd27ed080dffffffffff8a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
f0ba26954c84f126916616ac4311057151ea46cae2eda1752709c3a5adfe4b55 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 70 21 00 00 00
size 128 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (128 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-07ffffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07ffffff | unlocked | 2048
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 19.799786] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_read
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 134217728 (128M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x8000000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_read
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07ffffff | unlocked | 2048
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x8000000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_read
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_read
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_read2
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_test
792b00a5bf62350ee8f4868980820577046401c3e6f79075ea636034cff7cef2 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07ffffff | locked | 2048
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=134217728
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=2048
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 134086656 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07fdffff | unlocked | 2046
07fe0000-07ffffff | locked | 2
+ flash_lock -u /dev/mtd0 134086656 1
+ grep -A4 'locked sectors' /sys/kernel/debbg//spi-nr/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07feffff | unlocked | 2047
07ff0000-07ffffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 125829120 128
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-077fffff | unlocked | 1920
07800000-07ffffff | locked | 128
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-07ffffff | unlocked | 2046
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-07ffffff | unlocked | 2047
+ all_but_one=2047
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 2047
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-07ffffff | locked | 2047
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-07ffffff | locked | 2046
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2047
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07feffff | locked | 2047
07ff0000-07ffffff | unlocked | 1
+ flash_lock -u /dev/mtd0 134086656 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07fdffff | locked | 2046
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index fc9e84e500c5..8bcfc63a75f3 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -388,7 +388,7 @@ static const struct flash_info winbond_nor_parts[] = {
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
- /* W25Q01JV-M */
+ /* W25Q01JV-M, W25Q01RV-M */
.id = SNOR_ID(0xef, 0x70, 0x21),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 20/23] mtd: spi-nor: winbond: Add support for W25Q01RV-M
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef7021
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520fbffffffff3f44eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001602a60081e214dde9e378477a757a75
f7a4d55c39f66dffe970f9a50000000000002c0c000000006655ffff0f00
0000060d44bd27ed080dffffffffff8a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
f0ba26954c84f126916616ac4311057151ea46cae2eda1752709c3a5adfe4b55 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 70 21 00 00 00
size 128 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (128 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-07ffffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07ffffff | unlocked | 2048
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 19.799786] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_read
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 134217728 (128M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x8000000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_read
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07ffffff | unlocked | 2048
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x8000000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_read
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_read
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_read2
89d206670689b1bdd4688313bcc0ea3ac67a9ac055e75fd76220387c9e4fde3e spi_test
792b00a5bf62350ee8f4868980820577046401c3e6f79075ea636034cff7cef2 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07ffffff | locked | 2048
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=134217728
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=2048
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 134086656 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07fdffff | unlocked | 2046
07fe0000-07ffffff | locked | 2
+ flash_lock -u /dev/mtd0 134086656 1
+ grep -A4 'locked sectors' /sys/kernel/debbg//spi-nr/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07feffff | unlocked | 2047
07ff0000-07ffffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 125829120 128
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-077fffff | unlocked | 1920
07800000-07ffffff | locked | 128
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-07ffffff | unlocked | 2046
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-07ffffff | unlocked | 2047
+ all_but_one=2047
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 2047
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-07ffffff | locked | 2047
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-07ffffff | locked | 2046
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2047
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07feffff | locked | 2047
07ff0000-07ffffff | unlocked | 1
+ flash_lock -u /dev/mtd0 134086656 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-07fdffff | locked | 2046
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index fc9e84e500c5..8bcfc63a75f3 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -388,7 +388,7 @@ static const struct flash_info winbond_nor_parts[] = {
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
- /* W25Q01JV-M */
+ /* W25Q01JV-M, W25Q01RV-M */
.id = SNOR_ID(0xef, 0x70, 0x21),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 21/23] mtd: spi-nor: winbond: Add support for W25Q02RV-M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef7022
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520fbffffffff7f44eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001602a60081e214dde9e378477a757a75
f7a4d55c39f66dffe970f9a50000000000002c0c000000006655ffff0f00
0000060d44bd27ed080dffffffffff8a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
fe929abb1ba38dd6a8668200051298a8140bfeb56bd6d58f56b86b074a150f12 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 70 22 00 00 00
size 256 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (256 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-0fffffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0fffffff | unlocked | 4096
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 11.527038] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 268435456 (256M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x10000000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0fffffff | unlocked | 4096
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x10000000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read2
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test
4b1329df073cd497567d8cb6878aa20af6af71df98cc7c445d31a69eaf0d69f1 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0fffffff | locked | 4096
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=268435456
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=4096
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 268304384 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffdffff | unlocked | 4094
0ffe0000-0fffffff | locked | 2
+ flash_lock -u /dev/mtd0 268304384 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffeffff | unlocked | 4095
0fff0000-0fffffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 260046848 128
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0f7fffff | unlocked | 3968
0f800000-0fffffff | locked | 128
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-0fffffff | unlocked | 4094
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-0fffffff | unlocked | 4095
+ all_but_one=4095
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 4095
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-0fffffff | locked | 4095
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-0fffffff | locked | 4094
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 4095
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffeffff | locked | 4095
0fff0000-0fffffff | unlocked | 1
+ flash_lock -u /dev/mtd0 268304384 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffdffff | locked | 4094
0ffe0000-0fffffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 8bcfc63a75f3..6ad7d4a7da8d 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -393,7 +393,7 @@ static const struct flash_info winbond_nor_parts[] = {
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
- /* W25Q02JV-M */
+ /* W25Q02JV-M, W25Q02RV-M */
.id = SNOR_ID(0xef, 0x70, 0x22),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 21/23] mtd: spi-nor: winbond: Add support for W25Q02RV-M
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
There is an ID collision with the chip of same density from the JV
family. Both chips are very similar in practice, it is mostly a matter
of electrical differences (mostly power consumption being lower).
As a significant difference, RV chips identify themselves as supporting
the new SFDP (rev F) field which forces an alternate write SR2
opcode (0x31).
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
ef7022
+ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
winbond
+ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
534644500a0101ff00080117800000ff84010102e00000ffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffe520fbffffffff7f44eb086b083b42bbfeffffffffff
0000ffff44eb0c200f5210d800001602a60081e214dde9e378477a757a75
f7a4d55c39f66dffe970f9a50000000000002c0c000000006655ffff0f00
0000060d44bd27ed080dffffffffff8a00fe21ffdcff
+ sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
fe929abb1ba38dd6a8668200051298a8140bfeb56bd6d58f56b86b074a150f12 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
+ cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-2S
opcode 0x3c
mode cycles 0
dummy cycles 8
1S-2S-2S
opcode 0xbc
mode cycles 2
dummy cycles 2
1S-1S-4S
opcode 0x6c
mode cycles 0
dummy cycles 8
1S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
4S-4S-4S
opcode 0xec
mode cycles 2
dummy cycles 4
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
1S-1S-4S
opcode 0x34
+ cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id ef 70 22 00 00 00
size 256 MiB
write size 1
page size 256
address nbytes 4
flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET | NO_WP | HAS_SR2_CMP_BIT6
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
8D extension repeat
protocols
read 1S-4S-4S
write 1S-1S-4S
register 1S-1S-1S
erase commands
21 (4.00 KiB) [1]
dc (64.0 KiB) [3]
c7 (256 MiB)
sector map
region (in hex) | erase mask | overlaid
------------------+------------+---------
00000000-0fffffff | [ 3] | no
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0fffffff | unlocked | 4096
+ dd 'if=/dev/urandom' 'of=./spi_test' 'bs=1M' 'count=2'
[ 11.527038] random: crng init done
2+0 records in
2+0 records out
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
+ sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test
+ mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 268435456 (256M)
mtd.erasesize = 65536 (64K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
+ alias 'show_sectors=grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params'
+ flash_lock -u /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x10000000
Lock status: unlocked
Return code: 0
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0fffffff | unlocked | 4096
+ flash_lock -l /dev/mtd0
+ flash_lock -i /dev/mtd0
Device: /dev/mtd0
Start: 0
Len: 0x10000000
Lock status: locked
Return code: 1
+ mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
+ sha256sum spi_read spi_test
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test
+ dd 'if=/dev/urandom' 'of=./spi_test2' 'bs=1M' 'count=2'
2+0 records in
2+0 records out
+ mtd_debug write /dev/mtd0 0 2097152 spi_test2
Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash
+ mtd_debug read /dev/mtd0 0 2097152 spi_read2
Copied 2097152 bytes from address 0x00000000 in flash to spi_read2
+ sha256sum spi_read spi_read2 spi_test spi_test2
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_read2
32e1a8def4cf674413ff0b7a2738e704f03f7bddcaf7ee2d320ab83aa7bf813e spi_test
4b1329df073cd497567d8cb6878aa20af6af71df98cc7c445d31a69eaf0d69f1 spi_test2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0fffffff | locked | 4096
+ flash_lock -u /dev/mtd0
+ cat /sys/class/mtd/mtd0/size
+ size=268435456
+ cat /sys/class/mtd/mtd0/erasesize
+ bs=65536
+ grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params
+ sed -e 's/.*unlocked | //'
+ nsectors=4096
+ ss=65536
+ bps=1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 268304384 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffdffff | unlocked | 4094
0ffe0000-0fffffff | locked | 2
+ flash_lock -u /dev/mtd0 268304384 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffeffff | unlocked | 4095
0fff0000-0fffffff | locked | 1
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 260046848 128
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0f7fffff | unlocked | 3968
0f800000-0fffffff | locked | 128
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 2
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | locked | 2
00020000-0fffffff | unlocked | 4094
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | locked | 1
00010000-0fffffff | unlocked | 4095
+ all_but_one=4095
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 65536 4095
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0000ffff | unlocked | 1
00010000-0fffffff | locked | 4095
+ flash_lock -u /dev/mtd0 65536 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0001ffff | unlocked | 2
00020000-0fffffff | locked | 4094
+ flash_lock -u /dev/mtd0
+ flash_lock -l /dev/mtd0 0 4095
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffeffff | locked | 4095
0fff0000-0fffffff | unlocked | 1
+ flash_lock -u /dev/mtd0 268304384 1
+ grep -A4 'locked sectors' /sys/kernel/debug/spi-nor/spi0.0/params
locked sectors
region (in hex) | status | #sectors
------------------+----------+---------
00000000-0ffdffff | locked | 4094
0ffe0000-0fffffff | unlocked | 2
---
drivers/mtd/spi-nor/winbond.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 8bcfc63a75f3..6ad7d4a7da8d 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -393,7 +393,7 @@ static const struct flash_info winbond_nor_parts[] = {
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
}, {
- /* W25Q02JV-M */
+ /* W25Q02JV-M, W25Q02RV-M */
.id = SNOR_ID(0xef, 0x70, 0x22),
.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 22/23] mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N/M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
I currently do not have access to any chips from the W25Q25RV
density. Yet, I successfully tested the entire JV family and all other
chips from the RV family. They all behaved strictly identically, so I
propose to nevertheless add the missing comments for the sake of clarity
and completeness.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/winbond.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 6ad7d4a7da8d..b4ed41c692a8 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -265,7 +265,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q256JV-Q/N */
+ /* W25Q256JV-Q/N, W25Q25RV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x19),
.name = "w25q256",
.size = SZ_32M,
@@ -377,7 +377,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q256JV-M */
+ /* W25Q256JV-M, W25Q25RV-M */
.id = SNOR_ID(0xef, 0x70, 0x19),
.name = "w25q256jvm",
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 22/23] mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N/M
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
I currently do not have access to any chips from the W25Q25RV
density. Yet, I successfully tested the entire JV family and all other
chips from the RV family. They all behaved strictly identically, so I
propose to nevertheless add the missing comments for the sake of clarity
and completeness.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/winbond.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
index 6ad7d4a7da8d..b4ed41c692a8 100644
--- a/drivers/mtd/spi-nor/winbond.c
+++ b/drivers/mtd/spi-nor/winbond.c
@@ -265,7 +265,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q256JV-Q/N */
+ /* W25Q256JV-Q/N, W25Q25RV-Q/N */
.id = SNOR_ID(0xef, 0x40, 0x19),
.name = "w25q256",
.size = SZ_32M,
@@ -377,7 +377,7 @@ static const struct flash_info winbond_nor_parts[] = {
.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
}, {
- /* W25Q256JV-M */
+ /* W25Q256JV-M, W25Q25RV-M */
.id = SNOR_ID(0xef, 0x70, 0x19),
.name = "w25q256jvm",
.flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
--
2.54.0
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 23/23] mtd: spi-nor: debugfs: Expose SR opcodes and QE mask
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-13 15:19 ` Miquel Raynal
-1 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
Expose Status Register opcodes based on the flash capabilities
discovered while parsing the SFDP QER field.
Value '0' indicates an absence of opcode (non supported), we do not
print anything in that case.
The QE bit is also displayed.
Example on a W25Q02JV-M:
$ grep opcodes -A10 /sys/kernel/debug/spi-nor/spi0.0/params
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
SR1 read 0x05
SR2 read 0x35
SR1+SR2 write 0x01
QE SR2 bit 1
8D extension none
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/debugfs.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
index 275671222588..a82858f0328a 100644
--- a/drivers/mtd/spi-nor/debugfs.c
+++ b/drivers/mtd/spi-nor/debugfs.c
@@ -105,6 +105,21 @@ static int spi_nor_params_show(struct seq_file *s, void *data)
seq_printf(s, " dummy cycles\t%u\n", nor->read_dummy);
seq_printf(s, " erase\t\t0x%02x\n", nor->erase_opcode);
seq_printf(s, " program\t0x%02x\n", nor->program_opcode);
+ seq_printf(s, " SR1 read\t0x%02x\n", params->opcodes.read_sr1);
+ if (params->opcodes.read_sr2)
+ seq_printf(s, " SR2 read\t0x%02x\n", params->opcodes.read_sr2);
+ if (params->opcodes.write_sr1)
+ seq_printf(s, " SR1 write\t0x%02x\n", params->opcodes.write_sr1);
+ if (params->opcodes.write_sr2)
+ seq_printf(s, " SR2 write\t0x%02x\n", params->opcodes.write_sr2);
+ if (params->opcodes.write_sr1_and_sr2)
+ seq_printf(s, " SR1+SR2 write\t0x%02x\n",
+ params->opcodes.write_sr1_and_sr2);
+
+ if (params->qe_mask[0] || params->qe_mask[1])
+ seq_printf(s, " QE\t\tSR%d bit %d\n",
+ params->qe_mask[0] ? 1 : 2,
+ ffs(params->qe_mask[0] | params->qe_mask[1]) - 1);
switch (nor->cmd_ext_type) {
case SPI_NOR_EXT_NONE:
--
2.54.0
^ permalink raw reply related [flat|nested] 92+ messages in thread
* [PATCH v3 23/23] mtd: spi-nor: debugfs: Expose SR opcodes and QE mask
@ 2026-08-13 15:19 ` Miquel Raynal
0 siblings, 0 replies; 92+ messages in thread
From: Miquel Raynal @ 2026-08-13 15:19 UTC (permalink / raw)
To: Pratyush Yadav, Michael Walle, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc, Miquel Raynal
Expose Status Register opcodes based on the flash capabilities
discovered while parsing the SFDP QER field.
Value '0' indicates an absence of opcode (non supported), we do not
print anything in that case.
The QE bit is also displayed.
Example on a W25Q02JV-M:
$ grep opcodes -A10 /sys/kernel/debug/spi-nor/spi0.0/params
opcodes
read 0xec
dummy cycles 6
erase 0xdc
program 0x34
SR1 read 0x05
SR2 read 0x35
SR1+SR2 write 0x01
QE SR2 bit 1
8D extension none
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/spi-nor/debugfs.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
index 275671222588..a82858f0328a 100644
--- a/drivers/mtd/spi-nor/debugfs.c
+++ b/drivers/mtd/spi-nor/debugfs.c
@@ -105,6 +105,21 @@ static int spi_nor_params_show(struct seq_file *s, void *data)
seq_printf(s, " dummy cycles\t%u\n", nor->read_dummy);
seq_printf(s, " erase\t\t0x%02x\n", nor->erase_opcode);
seq_printf(s, " program\t0x%02x\n", nor->program_opcode);
+ seq_printf(s, " SR1 read\t0x%02x\n", params->opcodes.read_sr1);
+ if (params->opcodes.read_sr2)
+ seq_printf(s, " SR2 read\t0x%02x\n", params->opcodes.read_sr2);
+ if (params->opcodes.write_sr1)
+ seq_printf(s, " SR1 write\t0x%02x\n", params->opcodes.write_sr1);
+ if (params->opcodes.write_sr2)
+ seq_printf(s, " SR2 write\t0x%02x\n", params->opcodes.write_sr2);
+ if (params->opcodes.write_sr1_and_sr2)
+ seq_printf(s, " SR1+SR2 write\t0x%02x\n",
+ params->opcodes.write_sr1_and_sr2);
+
+ if (params->qe_mask[0] || params->qe_mask[1])
+ seq_printf(s, " QE\t\tSR%d bit %d\n",
+ params->qe_mask[0] ? 1 : 2,
+ ffs(params->qe_mask[0] | params->qe_mask[1]) - 1);
switch (nor->cmd_ext_type) {
case SPI_NOR_EXT_NONE:
--
2.54.0
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^ permalink raw reply related [flat|nested] 92+ messages in thread
* Re: [PATCH v3 01/23] mtd: spi-nor: Rename BFPT_DWORD15_QER_SR2_BIT1_BUGGY
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 7:30 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 7:30 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 690 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> The _BUGGY suffix is not super accurate. There is a behavior that indeed
> seems strange, but it is somewhat documented. The fact is, with this QER
> field the status register is considered 16-bit wide and if one writes
> the first 8 bits (SR1) without the next 8 bits (SR2) then the content of
> SR2 will be assumed to be 0x00 and will be cleared.
>
> Rename it BFPT_DWORD15_QER_SR2_BIT1_NO_1B_WR to align with the other
> namings (_NO_RD) and clarify the meaning of this field.
>
> No functional change.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
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^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 01/23] mtd: spi-nor: Rename BFPT_DWORD15_QER_SR2_BIT1_BUGGY
@ 2026-08-14 7:30 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 7:30 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 690 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> The _BUGGY suffix is not super accurate. There is a behavior that indeed
> seems strange, but it is somewhat documented. The fact is, with this QER
> field the status register is considered 16-bit wide and if one writes
> the first 8 bits (SR1) without the next 8 bits (SR2) then the content of
> SR2 will be assumed to be 0x00 and will be cleared.
>
> Rename it BFPT_DWORD15_QER_SR2_BIT1_NO_1B_WR to align with the other
> namings (_NO_RD) and clarify the meaning of this field.
>
> No functional change.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
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^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 02/23] mtd: spi-nor: Create a structure containing the flash opcodes
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 7:31 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 7:31 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 561 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> Create a structure named opcodes in the flash parameters structures to
> store all the flash specific opcodes. They are typically discovered
> dynamically through SFDP parsing. Move the die_erase opcode
> inside. Later on we will add new fields there, like the supported
> opcodes for accessing the status registers, which are almost vendor
> specific.
>
> No fonctional change.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
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^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 02/23] mtd: spi-nor: Create a structure containing the flash opcodes
@ 2026-08-14 7:31 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 7:31 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 561 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> Create a structure named opcodes in the flash parameters structures to
> store all the flash specific opcodes. They are typically discovered
> dynamically through SFDP parsing. Move the die_erase opcode
> inside. Later on we will add new fields there, like the supported
> opcodes for accessing the status registers, which are almost vendor
> specific.
>
> No fonctional change.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 05/23] mtd: spi-nor: Create the concept of fixup table with match function
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:40 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:40 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 37951 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> Manufacturer ID tables increase and fixup() hooks proliferate. Having
> one possible structure per chip was fine until the fixups started being
> more and more common and needed, to some extend due to ID reuses. Mixing
> fixups and chips becomes hard and requires extra helpers to sort which
> ones are needed for a given chip, which every time this happens requires
> a lot of rework.
Thanks, this patch looks really promising!
> Replace the two-level fixup association (a manufacturer wide hook and a
> per flash_info hook) with a per-manufacturer list of fixups that can be
> looked up by flash ID and/or match function.
>
> The match logic works as follows:
> - If there is an ID, it must match
> - If there is a match function, it must match (cumulative)
> - If there is no identifier (no ID nor any match function), it's a
> catch-all entry typically used for flagging manufacturer fixups.
This mimics, how it's currently handled. But since the fixups are
now treated as a separate list, i.e. it has it's own SNOR_ID, we
shall move away from this manufacturer thingy too. IMHO that really
clutters the code. As a fun fact, spi_nor_match_id() will have the
unexpected side effect of setting nor->manufacturer.
So here's how I'd do it:
(1) remove spi_nor_manufacturer.
(2) have a list of initcalls in the core to call into the individual
vendor modules (that could later be replaced by something more
sophiticated)
(3) that initcall will then call spi_nor_register_parts(const struct
flash_info *parts, int nparts)
(4) (optionally) calls spi_nor_register_fixups(const struct
spi_nor_fixup *fixups, int nfixups)
Also both could be a macro, then we can get rid of the size
argument.
The current manufacturer fixups gets registered with a
"SNOR_ID(vendor)".
That leaves us with the manufacturer name, which should be set by
that vendor catch all fixup.
Btw, I'm fine with deprecating the name as well as the manufacturer
sysfs entry, but it shouldn't be as in "it just goes away". There
should be a transition period. Although I'm not sure, how a user
could be notified, that this property will go away soon, honestly.
Print a warning on the kernel buffer? Not sure someone actually
notice that. Put it behind a Kconfig option which is "default y"
then after some time, that default is dropped and eventually removed
altogether? Looks like quite some churn and distros might just
enable it in their config. Any other ideas?
> Suggested-by: Michael Walle <mwalle@kernel.org>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> drivers/mtd/spi-nor/atmel.c | 23 ++++++-----
> drivers/mtd/spi-nor/core.c | 82 ++++++++++++++++++++++++++++------------
> drivers/mtd/spi-nor/core.h | 23 +++++++++--
> drivers/mtd/spi-nor/everspin.c | 7 +++-
> drivers/mtd/spi-nor/gigadevice.c | 7 +++-
> drivers/mtd/spi-nor/issi.c | 22 ++++++++---
> drivers/mtd/spi-nor/macronix.c | 23 ++++++-----
> drivers/mtd/spi-nor/micron-st.c | 43 +++++++++++++++------
> drivers/mtd/spi-nor/sfdp.c | 56 ++++++++++++++++++---------
> drivers/mtd/spi-nor/spansion.c | 41 +++++++++++---------
> drivers/mtd/spi-nor/sst.c | 11 ++++--
> drivers/mtd/spi-nor/winbond.c | 17 ++++++---
> 12 files changed, 247 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
> index 8741c0bda497..bccc702a2c4a 100644
> --- a/drivers/mtd/spi-nor/atmel.c
> +++ b/drivers/mtd/spi-nor/atmel.c
> @@ -194,47 +194,40 @@ static const struct flash_info atmel_nor_parts[] = {
> .size = SZ_512K,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &atmel_nor_global_protection_fixups,
> }, {
> .id = SNOR_ID(0x1f, 0x45, 0x01),
> .name = "at26df081a",
> .size = SZ_1M,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &atmel_nor_global_protection_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x46, 0x01),
> .name = "at26df161a",
> .size = SZ_2M,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &atmel_nor_global_protection_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x47, 0x00),
> .name = "at25df321",
> .size = SZ_4M,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &atmel_nor_global_protection_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x47, 0x01),
> .name = "at25df321a",
> .size = SZ_4M,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &atmel_nor_global_protection_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x47, 0x08),
> .name = "at25ff321a",
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> - .fixups = &atmel_nor_global_protection_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x48, 0x00),
> .name = "at25df641",
> .size = SZ_8M,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &atmel_nor_global_protection_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x66, 0x01),
> .name = "at25fs010",
> @@ -242,14 +235,12 @@ static const struct flash_info atmel_nor_parts[] = {
> .size = SZ_128K,
> .flags = SPI_NOR_HAS_LOCK,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &at25fs_nor_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x66, 0x04),
> .name = "at25fs040",
> .size = SZ_512K,
> .flags = SPI_NOR_HAS_LOCK,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &at25fs_nor_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x87, 0x01),
> .size = SZ_4M,
> @@ -257,8 +248,22 @@ static const struct flash_info atmel_nor_parts[] = {
> },
> };
>
> +static const struct spi_nor_fixup atmel_fixups[] = {
> + { .id = SNOR_ID(0x1f, 0x44, 0x01), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x45, 0x01), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x46, 0x01), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x47, 0x00), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x47, 0x01), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x47, 0x08), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x48, 0x00), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x66, 0x01), .fixups = &at25fs_nor_fixups },
> + { .id = SNOR_ID(0x1f, 0x66, 0x04), .fixups = &at25fs_nor_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_atmel = {
> .name = "atmel",
> .parts = atmel_nor_parts,
> .nparts = ARRAY_SIZE(atmel_nor_parts),
> + .fixups = atmel_fixups,
> + .nfixups = ARRAY_SIZE(atmel_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index ac7812562047..3a611283a9e6 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -2367,19 +2367,24 @@ int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
> const struct sfdp_parameter_header *bfpt_header,
> const struct sfdp_bfpt *bfpt)
> {
> + const struct spi_nor_fixup *fixups;
> int ret;
> + unsigned int i;
>
> - if (nor->manufacturer && nor->manufacturer->fixups &&
> - nor->manufacturer->fixups->post_bfpt) {
> - ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,
> - bfpt);
> - if (ret)
> - return ret;
> + if (!nor->manufacturer || !nor->manufacturer->fixups)
> + return 0;
> +
> + fixups = nor->manufacturer->fixups;
> +
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->post_bfpt &&
> + spi_nor_fixup_match(nor, &fixups[i])) {
> + ret = fixups[i].fixups->post_bfpt(nor, bfpt_header, bfpt);
> + if (ret)
> + return ret;
> + }
This is repeated several times, can we have something like
spi_nor_apply_fixups(struct spi_nor *nor, int (*fixup_fn), void *fixup_args);
int spi_nor_post_bfpt_fixup(struct spi_nor *nor, const struct spi_nor_fixup *fixup, void *_args)
{
struct post_bfpt_fixup_args *args = _args;
if (!fixup->post_bfpt)
return 0;
return fixup->post_bfpt(nor, args->bfpt_header, args->bfpt);
}
which then will be called with
spi_nor_apply_fixups(nor, spi_nor_post_bfpt_fixup, args);
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->post_bfpt &&
> + spi_nor_fixup_match(nor, &fixups[i])) {
> + ret = fixups[i].fixups->post_bfpt(nor, bfpt_header, bfpt);
> + if (ret)
> + return ret;
> }
>
> - if (nor->info->fixups && nor->info->fixups->post_bfpt)
> - return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt);
> -
> return 0;
> }
>
> @@ -2636,6 +2641,26 @@ static int spi_nor_setup(struct spi_nor *nor,
> return spi_nor_set_addr_nbytes(nor);
> }
>
> +bool spi_nor_fixup_match(const struct spi_nor *nor,
> + const struct spi_nor_fixup *fixup)
> +{
> + const struct spi_nor_id *id = nor->info ? nor->info->id : NULL;
> +
> + /* Filter by ID first, if available */
> + if (fixup->id) {
> + if (!id || fixup->id->len > id->len ||
> + memcmp(id->bytes, fixup->id->bytes, fixup->id->len))
> + return false;
> + }
> +
> + /* Further filter with the match callback, if provided */
> + if (fixup->match)
> + return fixup->match(nor);
> +
> + /* Either there was an ID and it matched, or it is a catch-all entry */
> + return true;
> +}
> +
> /**
> * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
> * settings based on MFR register and ->default_init() hook.
> @@ -2643,12 +2668,19 @@ static int spi_nor_setup(struct spi_nor *nor,
> */
> static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
> {
> - if (nor->manufacturer && nor->manufacturer->fixups &&
> - nor->manufacturer->fixups->default_init)
> - nor->manufacturer->fixups->default_init(nor);
> + const struct spi_nor_fixup *fixups;
> + unsigned int i;
>
> - if (nor->info->fixups && nor->info->fixups->default_init)
> - nor->info->fixups->default_init(nor);
> + if (!nor->manufacturer || !nor->manufacturer->fixups)
> + return;
> +
> + fixups = nor->manufacturer->fixups;
> +
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->default_init &&
> + spi_nor_fixup_match(nor, &fixups[i]))
> + fixups[i].fixups->default_init(nor);
> + }
> }
>
> /**
> @@ -2797,22 +2829,24 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor)
> static int spi_nor_late_init_params(struct spi_nor *nor)
> {
> struct spi_nor_flash_parameter *params = nor->params;
> + const struct spi_nor_fixup *fixups;
> + unsigned int i;
> int ret;
>
> /* Needed by some late_init hooks */
> spi_nor_init_flags(nor);
>
> - if (nor->manufacturer && nor->manufacturer->fixups &&
> - nor->manufacturer->fixups->late_init) {
> - ret = nor->manufacturer->fixups->late_init(nor);
> - if (ret)
> - return ret;
> - }
> + if (nor->manufacturer && nor->manufacturer->fixups) {
> + fixups = nor->manufacturer->fixups;
>
> - if (nor->info->fixups && nor->info->fixups->late_init) {
> - ret = nor->info->fixups->late_init(nor);
> - if (ret)
> - return ret;
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->late_init &&
> + spi_nor_fixup_match(nor, &fixups[i])) {
> + ret = fixups[i].fixups->late_init(nor);
> + if (ret)
> + return ret;
> + }
> + }
> }
>
> if (!nor->params->opcodes.die_erase)
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 7d43d3ba47ee..b650778a10de 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -445,6 +445,19 @@ struct spi_nor_fixups {
> int (*late_init)(struct spi_nor *nor);
> };
>
> +/**
> + * struct spi_nor_fixup - SPI NOR fixup registration.
> + * @id: (optional) flash ID this fixup applies to, may only match the
> + * ID prefix, eg. just the first few bytes to match a whole family
> + * @match: (optional) custom match function (can be used together with @id)
> + * @fixups: the fixup hooks to apply when this entry matches
> + */
> +struct spi_nor_fixup {
> + const struct spi_nor_id *id;
> + bool (*match)(const struct spi_nor *nor);
> + const struct spi_nor_fixups *fixups;
> +};
> +
> /**
> * struct spi_nor_id - SPI NOR flash ID.
> *
> @@ -560,7 +573,6 @@ struct flash_info {
> u8 mfr_flags;
>
> const struct spi_nor_otp_organization *otp;
> - const struct spi_nor_fixups *fixups;
> };
>
> #define SNOR_ID(...) \
> @@ -582,13 +594,16 @@ struct flash_info {
> * @name: manufacturer name
> * @parts: array of parts supported by this manufacturer
> * @nparts: number of entries in the parts array
> - * @fixups: hooks called at various points in time during spi_nor_scan()
> + * @fixups: list of fixups, each matched by ID (or a custom match function),
> + * applied to any part of this manufacturer.
> + * @nfixups: number of entries in the fixups array
> */
> struct spi_nor_manufacturer {
> const char *name;
> const struct flash_info *parts;
> unsigned int nparts;
> - const struct spi_nor_fixups *fixups;
> + const struct spi_nor_fixup *fixups;
> + unsigned int nfixups;
> };
>
> /**
> @@ -619,6 +634,8 @@ extern const struct spi_nor_manufacturer spi_nor_xmc;
>
> extern const struct attribute_group *spi_nor_sysfs_groups[];
>
> +bool spi_nor_fixup_match(const struct spi_nor *nor,
> + const struct spi_nor_fixup *fixup);
> void spi_nor_spimem_setup_op(const struct spi_nor *nor,
> struct spi_mem_op *op,
> const enum spi_nor_protocol proto);
> diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c
> index add37104d673..864dffba0e9c 100644
> --- a/drivers/mtd/spi-nor/everspin.c
> +++ b/drivers/mtd/spi-nor/everspin.c
> @@ -44,9 +44,14 @@ static const struct spi_nor_fixups everspin_nor_fixups = {
> .default_init = everspin_nor_default_init,
> };
>
> +static const struct spi_nor_fixup everspin_fixups[] = {
> + { .fixups = &everspin_nor_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_everspin = {
> .name = "everspin",
> .parts = everspin_nor_parts,
> .nparts = ARRAY_SIZE(everspin_nor_parts),
> - .fixups = &everspin_nor_fixups,
> + .fixups = everspin_fixups,
> + .nfixups = ARRAY_SIZE(everspin_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
> index 4070a692e968..f76fd0dedd0a 100644
> --- a/drivers/mtd/spi-nor/gigadevice.c
> +++ b/drivers/mtd/spi-nor/gigadevice.c
> @@ -64,7 +64,6 @@ static const struct flash_info gigadevice_nor_parts[] = {
> .id = SNOR_ID(0xc8, 0x40, 0x19),
> .name = "gd25q256",
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6,
> - .fixups = &gd25q256_fixups,
> .fixup_flags = SPI_NOR_4B_OPCODES,
The fixup_flags should also go into the fixups list.
> }, {
> .id = SNOR_ID(0xc8, 0x60, 0x16),
> @@ -87,8 +86,14 @@ static const struct flash_info gigadevice_nor_parts[] = {
> },
> };
>
> +static const struct spi_nor_fixup gigadevice_fixups[] = {
> + { .id = SNOR_ID(0xc8, 0x40, 0x19), .fixups = &gd25q256_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_gigadevice = {
> .name = "gigadevice",
> .parts = gigadevice_nor_parts,
> .nparts = ARRAY_SIZE(gigadevice_nor_parts),
> + .fixups = gigadevice_fixups,
> + .nfixups = ARRAY_SIZE(gigadevice_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
> index 04db42b5141e..4842f8acd074 100644
> --- a/drivers/mtd/spi-nor/issi.c
> +++ b/drivers/mtd/spi-nor/issi.c
> @@ -52,13 +52,11 @@ static const struct flash_info issi_nor_parts[] = {
> .sector_size = SZ_32K,
> .size = SZ_64K,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &pm25lv_nor_fixups
> }, {
> .name = "pm25lv010",
> .sector_size = SZ_32K,
> .size = SZ_128K,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &pm25lv_nor_fixups
> }, {
> .id = SNOR_ID(0x7f, 0x9d, 0x20),
> .name = "is25cd512",
> @@ -103,7 +101,6 @@ static const struct flash_info issi_nor_parts[] = {
> }, {
> .id = SNOR_ID(0x9d, 0x60, 0x19),
> .name = "is25lp256",
> - .fixups = &is25lp256_fixups,
> .fixup_flags = SPI_NOR_4B_OPCODES,
> }, {
> .id = SNOR_ID(0x9d, 0x70, 0x16),
> @@ -124,7 +121,6 @@ static const struct flash_info issi_nor_parts[] = {
> .id = SNOR_ID(0x9d, 0x70, 0x19),
> .name = "is25wp256",
> .flags = SPI_NOR_QUAD_PP,
> - .fixups = &is25lp256_fixups,
> .fixup_flags = SPI_NOR_4B_OPCODES,
> }
> };
> @@ -139,9 +135,25 @@ static const struct spi_nor_fixups issi_fixups = {
> .default_init = issi_nor_default_init,
> };
>
> +/* PM25LV parts have no JEDEC ID and are likely matched by name */
> +static bool issi_pm25lv_match(const struct spi_nor *nor)
> +{
> + const char *name = nor->info ? nor->info->name : NULL;
> +
> + return name && !strncmp(name, "pm25lv", 6);
Won't just strcmp("pm25lv", name) do it? Both arguments are
guaranteed to be NUL terminated. The above would also match
"pm25lvextrabytes", no, and we get rid of that redundant size
argument.
> +}
> +
> +static const struct spi_nor_fixup issi_fixup_list[] = {
> + { .fixups = &issi_fixups },
> + { .match = issi_pm25lv_match, .fixups = &pm25lv_nor_fixups },
> + { .id = SNOR_ID(0x9d, 0x60, 0x19), .fixups = &is25lp256_fixups },
> + { .id = SNOR_ID(0x9d, 0x70, 0x19), .fixups = &is25lp256_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_issi = {
> .name = "issi",
> .parts = issi_nor_parts,
> .nparts = ARRAY_SIZE(issi_nor_parts),
> - .fixups = &issi_fixups,
> + .fixups = issi_fixup_list,
> + .nfixups = ARRAY_SIZE(issi_fixup_list),
> };
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index 55612237c1ef..04b431bf5f13 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -137,20 +137,16 @@ static const struct flash_info macronix_nor_parts[] = {
> }, {
> /* MX25L25635E, MX25L25645G */
> .id = SNOR_ID(0xc2, 0x20, 0x19),
> - .fixups = &mx25l25635_fixups
> }, {
> /* MX66L51235F */
> .id = SNOR_ID(0xc2, 0x20, 0x1a),
> .fixup_flags = SPI_NOR_4B_OPCODES,
> - .fixups = ¯onix_qpp4b_fixups,
> }, {
> /* MX66L1G45G */
> .id = SNOR_ID(0xc2, 0x20, 0x1b),
> - .fixups = ¯onix_qpp4b_fixups,
> }, {
> /* MX66L2G45G */
> .id = SNOR_ID(0xc2, 0x20, 0x1c),
> - .fixups = ¯onix_qpp4b_fixups,
> }, {
> .id = SNOR_ID(0xc2, 0x23, 0x14),
> .name = "mx25v8035f",
> @@ -189,15 +185,12 @@ static const struct flash_info macronix_nor_parts[] = {
> }, {
> /* MX25U51245G */
> .id = SNOR_ID(0xc2, 0x25, 0x3a),
> - .fixups = ¯onix_qpp4b_fixups,
> }, {
> /* MX66U1G45G */
> .id = SNOR_ID(0xc2, 0x25, 0x3b),
> - .fixups = ¯onix_qpp4b_fixups,
> }, {
> /* MX66U2G45G */
> .id = SNOR_ID(0xc2, 0x25, 0x3c),
> - .fixups = ¯onix_qpp4b_fixups,
> }, {
> .id = SNOR_ID(0xc2, 0x26, 0x18),
> .name = "mx25l12855e",
> @@ -229,7 +222,6 @@ static const struct flash_info macronix_nor_parts[] = {
> }, {
> /* MX25L3255E */
> .id = SNOR_ID(0xc2, 0x9e, 0x16),
> - .fixups = &mx25l3255e_fixups,
> },
> /*
> * This spares us of adding new flash entries for flashes that can be
> @@ -333,9 +325,22 @@ static const struct spi_nor_fixups macronix_nor_fixups = {
> .late_init = macronix_nor_late_init,
> };
>
> +static const struct spi_nor_fixup macronix_fixups[] = {
> + { .fixups = ¯onix_nor_fixups },
> + { .id = SNOR_ID(0xc2, 0x20, 0x19), .fixups = &mx25l25635_fixups },
> + { .id = SNOR_ID(0xc2, 0x20, 0x1a), .fixups = ¯onix_qpp4b_fixups },
> + { .id = SNOR_ID(0xc2, 0x20, 0x1b), .fixups = ¯onix_qpp4b_fixups },
> + { .id = SNOR_ID(0xc2, 0x20, 0x1c), .fixups = ¯onix_qpp4b_fixups },
> + { .id = SNOR_ID(0xc2, 0x25, 0x3a), .fixups = ¯onix_qpp4b_fixups },
> + { .id = SNOR_ID(0xc2, 0x25, 0x3b), .fixups = ¯onix_qpp4b_fixups },
> + { .id = SNOR_ID(0xc2, 0x25, 0x3c), .fixups = ¯onix_qpp4b_fixups },
> + { .id = SNOR_ID(0xc2, 0x9e, 0x16), .fixups = &mx25l3255e_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_macronix = {
> .name = "macronix",
> .parts = macronix_nor_parts,
> .nparts = ARRAY_SIZE(macronix_nor_parts),
> - .fixups = ¯onix_nor_fixups,
> + .fixups = macronix_fixups,
> + .nfixups = ARRAY_SIZE(macronix_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
> index 344539d2a36a..2aabd6d487ba 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -206,13 +206,11 @@ static const struct flash_info micron_nor_parts[] = {
> .id = SNOR_ID(0x2c, 0x5b, 0x1a),
> .mfr_flags = USE_FSR,
> .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE,
> - .fixups = &mt35xu512aba_fixups,
> }, {
> /* MT35XU01GBBA */
> .id = SNOR_ID(0x2c, 0x5b, 0x1b),
> .mfr_flags = USE_FSR,
> .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE,
> - .fixups = &mt35_two_die_fixups,
> }, {
> .id = SNOR_ID(0x2c, 0x5b, 0x1c),
> .name = "mt35xu02g",
> @@ -221,7 +219,6 @@ static const struct flash_info micron_nor_parts[] = {
> .no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ,
> .mfr_flags = USE_FSR,
> .fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,
> - .fixups = &mt35_two_die_fixups,
> },
> };
>
> @@ -233,6 +230,17 @@ static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor,
> return 0;
> }
>
> +/*
> + * n25q00a parts share the first same 3 ID bytes with mt25qu01g.
> + * In order to not mix the fixups, further filter out using the part name.
How would that work? The part name is also set by the duplicated ID,
so the first one wins, no?
-michael
> + */
> +static bool n25q00a_match(const struct spi_nor *nor)
> +{
> + const char *name = nor->info ? nor->info->name : NULL;
> +
> + return name && !strncmp(name, "n25q00a", 7);
> +}
> +
> static const struct spi_nor_fixups mt25qu512a_fixups = {
> .post_bfpt = mt25qu512a_post_bfpt_fixup,
> };
> @@ -426,14 +434,12 @@ static const struct flash_info st_nor_parts[] = {
> SPI_NOR_BP3_SR_BIT6,
> .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
> .mfr_flags = USE_FSR,
> - .fixups = &n25q00_fixups,
> }, {
> .id = SNOR_ID(0x20, 0xba, 0x22),
> .name = "mt25ql02g",
> .size = SZ_256M,
> .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
> .mfr_flags = USE_FSR,
> - .fixups = &mt25q02_fixups,
> }, {
> .id = SNOR_ID(0x20, 0xbb, 0x15),
> .name = "n25q016a",
> @@ -480,7 +486,6 @@ static const struct flash_info st_nor_parts[] = {
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
> SPI_NOR_BP3_SR_BIT6,
> .mfr_flags = USE_FSR,
> - .fixups = &mt25qu512a_fixups,
> }, {
> .id = SNOR_ID(0x20, 0xbb, 0x20),
> .name = "n25q512a",
> @@ -493,21 +498,18 @@ static const struct flash_info st_nor_parts[] = {
> .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00),
> .name = "mt25qu01g",
> .mfr_flags = USE_FSR,
> - .fixups = &mt25q01_fixups,
> }, {
> .id = SNOR_ID(0x20, 0xbb, 0x21),
> .name = "n25q00a",
> .size = SZ_128M,
> .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
> .mfr_flags = USE_FSR,
> - .fixups = &n25q00_fixups,
> }, {
> .id = SNOR_ID(0x20, 0xbb, 0x22),
> .name = "mt25qu02g",
> .size = SZ_256M,
> .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> .mfr_flags = USE_FSR,
> - .fixups = &mt25q02_fixups,
> }
> };
>
> @@ -657,16 +659,35 @@ static const struct spi_nor_fixups micron_st_nor_fixups = {
> .late_init = micron_st_nor_late_init,
> };
>
> +static const struct spi_nor_fixup micron_fixups[] = {
> + { .fixups = µn_st_nor_fixups },
> + { .id = SNOR_ID(0x2c, 0x5b, 0x1a), .fixups = &mt35xu512aba_fixups },
> + { .id = SNOR_ID(0x2c, 0x5b, 0x1b), .fixups = &mt35_two_die_fixups },
> + { .id = SNOR_ID(0x2c, 0x5b, 0x1c), .fixups = &mt35_two_die_fixups },
> +};
> +
> +static const struct spi_nor_fixup st_fixups[] = {
> + { .fixups = µn_st_nor_fixups },
> + { .id = SNOR_ID(0x20, 0xba, 0x21), .fixups = &n25q00_fixups },
> + { .id = SNOR_ID(0x20, 0xba, 0x22), .fixups = &mt25q02_fixups },
> + { .id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00), .fixups = &mt25qu512a_fixups },
> + { .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00), .fixups = &mt25q01_fixups },
> + { .id = SNOR_ID(0x20, 0xbb, 0x21), .match = n25q00a_match, .fixups = &n25q00_fixups },
> + { .id = SNOR_ID(0x20, 0xbb, 0x22), .fixups = &mt25q02_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_micron = {
> .name = "micron",
> .parts = micron_nor_parts,
> .nparts = ARRAY_SIZE(micron_nor_parts),
> - .fixups = µn_st_nor_fixups,
> + .fixups = micron_fixups,
> + .nfixups = ARRAY_SIZE(micron_fixups),
> };
>
> const struct spi_nor_manufacturer spi_nor_st = {
> .name = "st",
> .parts = st_nor_parts,
> .nparts = ARRAY_SIZE(st_nor_parts),
> - .fixups = µn_st_nor_fixups,
> + .fixups = st_fixups,
> + .nfixups = ARRAY_SIZE(st_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
> index 285ac781fba8..39cb8ac3a037 100644
> --- a/drivers/mtd/spi-nor/sfdp.c
> +++ b/drivers/mtd/spi-nor/sfdp.c
> @@ -727,12 +727,19 @@ static u8 spi_nor_smpt_addr_nbytes(const struct spi_nor *nor, const u32 settings
> static void spi_nor_smpt_read_dummy_fixups(const struct spi_nor *nor,
> u8 *read_dummy)
> {
> - if (nor->manufacturer && nor->manufacturer->fixups &&
> - nor->manufacturer->fixups->smpt_read_dummy)
> - nor->manufacturer->fixups->smpt_read_dummy(nor, read_dummy);
> + const struct spi_nor_fixup *fixups;
> + unsigned int i;
>
> - if (nor->info->fixups && nor->info->fixups->smpt_read_dummy)
> - nor->info->fixups->smpt_read_dummy(nor, read_dummy);
> + if (!nor->manufacturer || !nor->manufacturer->fixups)
> + return;
> +
> + fixups = nor->manufacturer->fixups;
> +
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->smpt_read_dummy &&
> + spi_nor_fixup_match(nor, &fixups[i]))
> + fixups[i].fixups->smpt_read_dummy(nor, read_dummy);
> + }
> }
>
> /**
> @@ -757,12 +764,19 @@ static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings)
>
> static void spi_nor_smpt_map_id_fixups(const struct spi_nor *nor, u8 *map_id)
> {
> - if (nor->manufacturer && nor->manufacturer->fixups &&
> - nor->manufacturer->fixups->smpt_map_id)
> - nor->manufacturer->fixups->smpt_map_id(nor, map_id);
> + const struct spi_nor_fixup *fixups;
> + unsigned int i;
>
> - if (nor->info->fixups && nor->info->fixups->smpt_map_id)
> - nor->info->fixups->smpt_map_id(nor, map_id);
> + if (!nor->manufacturer || !nor->manufacturer->fixups)
> + return;
> +
> + fixups = nor->manufacturer->fixups;
> +
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->smpt_map_id &&
> + spi_nor_fixup_match(nor, &fixups[i]))
> + fixups[i].fixups->smpt_map_id(nor, map_id);
> + }
> }
>
> /**
> @@ -1406,17 +1420,23 @@ static int spi_nor_parse_sccr_mc(struct spi_nor *nor,
> */
> static int spi_nor_post_sfdp_fixups(struct spi_nor *nor)
> {
> + const struct spi_nor_fixup *fixups;
> + unsigned int i;
> int ret;
>
> - if (nor->manufacturer && nor->manufacturer->fixups &&
> - nor->manufacturer->fixups->post_sfdp) {
> - ret = nor->manufacturer->fixups->post_sfdp(nor);
> - if (ret)
> - return ret;
> - }
> + if (!nor->manufacturer || !nor->manufacturer->fixups)
> + return 0;
>
> - if (nor->info->fixups && nor->info->fixups->post_sfdp)
> - return nor->info->fixups->post_sfdp(nor);
> + fixups = nor->manufacturer->fixups;
> +
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->post_sfdp &&
> + spi_nor_fixup_match(nor, &fixups[i])) {
> + ret = fixups[i].fixups->post_sfdp(nor);
> + if (ret)
> + return ret;
> + }
> + }
>
> return 0;
> }
> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
> index ca2703a5a338..f3862eb1a23a 100644
> --- a/drivers/mtd/spi-nor/spansion.c
> +++ b/drivers/mtd/spi-nor/spansion.c
> @@ -905,7 +905,6 @@ static const struct flash_info spansion_nor_parts[] = {
> .sector_size = SZ_256K,
> .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> .mfr_flags = USE_CLSR,
> - .fixups = &s25fs_s_nor_fixups,
> }, {
> .id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x00),
> .name = "s25sl12800",
> @@ -941,7 +940,6 @@ static const struct flash_info spansion_nor_parts[] = {
> .size = SZ_16M,
> .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> .mfr_flags = USE_CLSR,
> - .fixups = &s25fs_s_nor_fixups,
> }, {
> .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01),
> .name = "s25fl129p1",
> @@ -1001,76 +999,61 @@ static const struct flash_info spansion_nor_parts[] = {
> .id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90),
> .name = "s25hl512t",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25hx_t_fixups
> }, {
> .id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90),
> .name = "s25hl01gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25hx_t_fixups
> }, {
> .id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90),
> .name = "s25hl02gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25hx_t_fixups
> }, {
> .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90),
> .name = "s25fs256t",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25fs256t_fixups
> }, {
> .id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90),
> .name = "s25hs512t",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25hx_t_fixups
> }, {
> .id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90),
> .name = "s25hs01gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25hx_t_fixups
> }, {
> .id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90),
> .name = "s25hs02gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25hx_t_fixups
> }, {
> /* S28HL256T */
> .id = SNOR_ID(0x34, 0x5a, 0x19),
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0x34, 0x5a, 0x1a),
> .name = "s28hl512t",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0x34, 0x5a, 0x1b),
> .name = "s28hl01gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> /* S28HL02GT */
> .id = SNOR_ID(0x34, 0x5a, 0x1c),
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0x34, 0x5b, 0x19),
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0x34, 0x5b, 0x1a),
> .name = "s28hs512t",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0x34, 0x5b, 0x1b),
> .name = "s28hs01gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0x34, 0x5b, 0x1c),
> .name = "s28hs02gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0xef, 0x40, 0x13),
> .name = "s25fl004k",
> @@ -1170,9 +1153,31 @@ static const struct spi_nor_fixups spansion_nor_fixups = {
> .late_init = spansion_nor_late_init,
> };
>
> +static const struct spi_nor_fixup spansion_fixups[] = {
> + { .fixups = &spansion_nor_fixups },
> + { .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x81), .fixups = &s25fs_s_nor_fixups },
> + { .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x81), .fixups = &s25fs_s_nor_fixups },
> + { .id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90), .fixups = &s25hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90), .fixups = &s25fs256t_fixups },
> + { .id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90), .fixups = &s25hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5a, 0x19), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5a, 0x1a), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5a, 0x1b), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5a, 0x1c), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5b, 0x19), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5b, 0x1a), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5b, 0x1b), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5b, 0x1c), .fixups = &s28hx_t_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_spansion = {
> .name = "spansion",
> .parts = spansion_nor_parts,
> .nparts = ARRAY_SIZE(spansion_nor_parts),
> - .fixups = &spansion_nor_fixups,
> + .fixups = spansion_fixups,
> + .nfixups = ARRAY_SIZE(spansion_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
> index 77a0bc41d4e5..c460803b278b 100644
> --- a/drivers/mtd/spi-nor/sst.c
> +++ b/drivers/mtd/spi-nor/sst.c
> @@ -152,14 +152,12 @@ static const struct flash_info sst_nor_parts[] = {
> .id = SNOR_ID(0xbf, 0x26, 0x42),
> .name = "sst26vf032b",
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> - .fixups = &sst26vf_nor_fixups,
> }, {
> .id = SNOR_ID(0xbf, 0x26, 0x43),
> .name = "sst26vf064b",
> .size = SZ_8M,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> - .fixups = &sst26vf_nor_fixups,
> }, {
> .id = SNOR_ID(0xbf, 0x26, 0x51),
> .name = "sst26wf016b",
> @@ -278,9 +276,16 @@ static const struct spi_nor_fixups sst_nor_fixups = {
> .late_init = sst_nor_late_init,
> };
>
> +static const struct spi_nor_fixup sst_fixups[] = {
> + { .fixups = &sst_nor_fixups },
> + { .id = SNOR_ID(0xbf, 0x26, 0x42), .fixups = &sst26vf_nor_fixups },
> + { .id = SNOR_ID(0xbf, 0x26, 0x43), .fixups = &sst26vf_nor_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_sst = {
> .name = "sst",
> .parts = sst_nor_parts,
> .nparts = ARRAY_SIZE(sst_nor_parts),
> - .fixups = &sst_nor_fixups,
> + .fixups = sst_fixups,
> + .nfixups = ARRAY_SIZE(sst_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
> index 01a693033448..583b1669270f 100644
> --- a/drivers/mtd/spi-nor/winbond.c
> +++ b/drivers/mtd/spi-nor/winbond.c
> @@ -219,7 +219,6 @@ static const struct flash_info winbond_nor_parts[] = {
> .size = SZ_16M,
> .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> .flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
> - .fixups = &w25q128_fixups,
> }, {
> /* W25Q256JV-Q/N */
> .id = SNOR_ID(0xef, 0x40, 0x19),
> @@ -228,7 +227,6 @@ static const struct flash_info winbond_nor_parts[] = {
> .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> .flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
> SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
> - .fixups = &w25q256_fixups,
> }, {
> /* W25Q512JV-Q/N */
> .id = SNOR_ID(0xef, 0x40, 0x20),
> @@ -242,7 +240,6 @@ static const struct flash_info winbond_nor_parts[] = {
> .id = SNOR_ID(0xef, 0x40, 0x21),
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
> SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
> - .fixups = &winbond_nor_multi_die_fixups,
> }, {
> .id = SNOR_ID(0xef, 0x50, 0x12),
> .name = "w25q20bw",
> @@ -345,13 +342,11 @@ static const struct flash_info winbond_nor_parts[] = {
> .id = SNOR_ID(0xef, 0x70, 0x21),
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
> SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
> - .fixups = &winbond_nor_multi_die_fixups,
> }, {
> /* W25Q02JV-M */
> .id = SNOR_ID(0xef, 0x70, 0x22),
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
> SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
> - .fixups = &winbond_nor_multi_die_fixups,
> }, {
> .id = SNOR_ID(0xef, 0x71, 0x19),
> .name = "w25m512jv",
> @@ -553,9 +548,19 @@ static const struct spi_nor_fixups winbond_nor_fixups = {
> .late_init = winbond_nor_late_init,
> };
>
> +static const struct spi_nor_fixup winbond_fixups[] = {
> + { .fixups = &winbond_nor_fixups },
> + { .id = SNOR_ID(0xef, 0x40, 0x18), .fixups = &w25q128_fixups },
> + { .id = SNOR_ID(0xef, 0x40, 0x19), .fixups = &w25q256_fixups },
> + { .id = SNOR_ID(0xef, 0x40, 0x21), .fixups = &winbond_nor_multi_die_fixups },
> + { .id = SNOR_ID(0xef, 0x70, 0x21), .fixups = &winbond_nor_multi_die_fixups },
> + { .id = SNOR_ID(0xef, 0x70, 0x22), .fixups = &winbond_nor_multi_die_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_winbond = {
> .name = "winbond",
> .parts = winbond_nor_parts,
> .nparts = ARRAY_SIZE(winbond_nor_parts),
> - .fixups = &winbond_nor_fixups,
> + .fixups = winbond_fixups,
> + .nfixups = ARRAY_SIZE(winbond_fixups),
> };
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______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 05/23] mtd: spi-nor: Create the concept of fixup table with match function
@ 2026-08-14 9:40 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:40 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 37951 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> Manufacturer ID tables increase and fixup() hooks proliferate. Having
> one possible structure per chip was fine until the fixups started being
> more and more common and needed, to some extend due to ID reuses. Mixing
> fixups and chips becomes hard and requires extra helpers to sort which
> ones are needed for a given chip, which every time this happens requires
> a lot of rework.
Thanks, this patch looks really promising!
> Replace the two-level fixup association (a manufacturer wide hook and a
> per flash_info hook) with a per-manufacturer list of fixups that can be
> looked up by flash ID and/or match function.
>
> The match logic works as follows:
> - If there is an ID, it must match
> - If there is a match function, it must match (cumulative)
> - If there is no identifier (no ID nor any match function), it's a
> catch-all entry typically used for flagging manufacturer fixups.
This mimics, how it's currently handled. But since the fixups are
now treated as a separate list, i.e. it has it's own SNOR_ID, we
shall move away from this manufacturer thingy too. IMHO that really
clutters the code. As a fun fact, spi_nor_match_id() will have the
unexpected side effect of setting nor->manufacturer.
So here's how I'd do it:
(1) remove spi_nor_manufacturer.
(2) have a list of initcalls in the core to call into the individual
vendor modules (that could later be replaced by something more
sophiticated)
(3) that initcall will then call spi_nor_register_parts(const struct
flash_info *parts, int nparts)
(4) (optionally) calls spi_nor_register_fixups(const struct
spi_nor_fixup *fixups, int nfixups)
Also both could be a macro, then we can get rid of the size
argument.
The current manufacturer fixups gets registered with a
"SNOR_ID(vendor)".
That leaves us with the manufacturer name, which should be set by
that vendor catch all fixup.
Btw, I'm fine with deprecating the name as well as the manufacturer
sysfs entry, but it shouldn't be as in "it just goes away". There
should be a transition period. Although I'm not sure, how a user
could be notified, that this property will go away soon, honestly.
Print a warning on the kernel buffer? Not sure someone actually
notice that. Put it behind a Kconfig option which is "default y"
then after some time, that default is dropped and eventually removed
altogether? Looks like quite some churn and distros might just
enable it in their config. Any other ideas?
> Suggested-by: Michael Walle <mwalle@kernel.org>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> drivers/mtd/spi-nor/atmel.c | 23 ++++++-----
> drivers/mtd/spi-nor/core.c | 82 ++++++++++++++++++++++++++++------------
> drivers/mtd/spi-nor/core.h | 23 +++++++++--
> drivers/mtd/spi-nor/everspin.c | 7 +++-
> drivers/mtd/spi-nor/gigadevice.c | 7 +++-
> drivers/mtd/spi-nor/issi.c | 22 ++++++++---
> drivers/mtd/spi-nor/macronix.c | 23 ++++++-----
> drivers/mtd/spi-nor/micron-st.c | 43 +++++++++++++++------
> drivers/mtd/spi-nor/sfdp.c | 56 ++++++++++++++++++---------
> drivers/mtd/spi-nor/spansion.c | 41 +++++++++++---------
> drivers/mtd/spi-nor/sst.c | 11 ++++--
> drivers/mtd/spi-nor/winbond.c | 17 ++++++---
> 12 files changed, 247 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
> index 8741c0bda497..bccc702a2c4a 100644
> --- a/drivers/mtd/spi-nor/atmel.c
> +++ b/drivers/mtd/spi-nor/atmel.c
> @@ -194,47 +194,40 @@ static const struct flash_info atmel_nor_parts[] = {
> .size = SZ_512K,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &atmel_nor_global_protection_fixups,
> }, {
> .id = SNOR_ID(0x1f, 0x45, 0x01),
> .name = "at26df081a",
> .size = SZ_1M,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &atmel_nor_global_protection_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x46, 0x01),
> .name = "at26df161a",
> .size = SZ_2M,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &atmel_nor_global_protection_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x47, 0x00),
> .name = "at25df321",
> .size = SZ_4M,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &atmel_nor_global_protection_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x47, 0x01),
> .name = "at25df321a",
> .size = SZ_4M,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &atmel_nor_global_protection_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x47, 0x08),
> .name = "at25ff321a",
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> - .fixups = &atmel_nor_global_protection_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x48, 0x00),
> .name = "at25df641",
> .size = SZ_8M,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &atmel_nor_global_protection_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x66, 0x01),
> .name = "at25fs010",
> @@ -242,14 +235,12 @@ static const struct flash_info atmel_nor_parts[] = {
> .size = SZ_128K,
> .flags = SPI_NOR_HAS_LOCK,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &at25fs_nor_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x66, 0x04),
> .name = "at25fs040",
> .size = SZ_512K,
> .flags = SPI_NOR_HAS_LOCK,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &at25fs_nor_fixups
> }, {
> .id = SNOR_ID(0x1f, 0x87, 0x01),
> .size = SZ_4M,
> @@ -257,8 +248,22 @@ static const struct flash_info atmel_nor_parts[] = {
> },
> };
>
> +static const struct spi_nor_fixup atmel_fixups[] = {
> + { .id = SNOR_ID(0x1f, 0x44, 0x01), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x45, 0x01), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x46, 0x01), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x47, 0x00), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x47, 0x01), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x47, 0x08), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x48, 0x00), .fixups = &atmel_nor_global_protection_fixups },
> + { .id = SNOR_ID(0x1f, 0x66, 0x01), .fixups = &at25fs_nor_fixups },
> + { .id = SNOR_ID(0x1f, 0x66, 0x04), .fixups = &at25fs_nor_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_atmel = {
> .name = "atmel",
> .parts = atmel_nor_parts,
> .nparts = ARRAY_SIZE(atmel_nor_parts),
> + .fixups = atmel_fixups,
> + .nfixups = ARRAY_SIZE(atmel_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index ac7812562047..3a611283a9e6 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -2367,19 +2367,24 @@ int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
> const struct sfdp_parameter_header *bfpt_header,
> const struct sfdp_bfpt *bfpt)
> {
> + const struct spi_nor_fixup *fixups;
> int ret;
> + unsigned int i;
>
> - if (nor->manufacturer && nor->manufacturer->fixups &&
> - nor->manufacturer->fixups->post_bfpt) {
> - ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,
> - bfpt);
> - if (ret)
> - return ret;
> + if (!nor->manufacturer || !nor->manufacturer->fixups)
> + return 0;
> +
> + fixups = nor->manufacturer->fixups;
> +
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->post_bfpt &&
> + spi_nor_fixup_match(nor, &fixups[i])) {
> + ret = fixups[i].fixups->post_bfpt(nor, bfpt_header, bfpt);
> + if (ret)
> + return ret;
> + }
This is repeated several times, can we have something like
spi_nor_apply_fixups(struct spi_nor *nor, int (*fixup_fn), void *fixup_args);
int spi_nor_post_bfpt_fixup(struct spi_nor *nor, const struct spi_nor_fixup *fixup, void *_args)
{
struct post_bfpt_fixup_args *args = _args;
if (!fixup->post_bfpt)
return 0;
return fixup->post_bfpt(nor, args->bfpt_header, args->bfpt);
}
which then will be called with
spi_nor_apply_fixups(nor, spi_nor_post_bfpt_fixup, args);
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->post_bfpt &&
> + spi_nor_fixup_match(nor, &fixups[i])) {
> + ret = fixups[i].fixups->post_bfpt(nor, bfpt_header, bfpt);
> + if (ret)
> + return ret;
> }
>
> - if (nor->info->fixups && nor->info->fixups->post_bfpt)
> - return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt);
> -
> return 0;
> }
>
> @@ -2636,6 +2641,26 @@ static int spi_nor_setup(struct spi_nor *nor,
> return spi_nor_set_addr_nbytes(nor);
> }
>
> +bool spi_nor_fixup_match(const struct spi_nor *nor,
> + const struct spi_nor_fixup *fixup)
> +{
> + const struct spi_nor_id *id = nor->info ? nor->info->id : NULL;
> +
> + /* Filter by ID first, if available */
> + if (fixup->id) {
> + if (!id || fixup->id->len > id->len ||
> + memcmp(id->bytes, fixup->id->bytes, fixup->id->len))
> + return false;
> + }
> +
> + /* Further filter with the match callback, if provided */
> + if (fixup->match)
> + return fixup->match(nor);
> +
> + /* Either there was an ID and it matched, or it is a catch-all entry */
> + return true;
> +}
> +
> /**
> * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
> * settings based on MFR register and ->default_init() hook.
> @@ -2643,12 +2668,19 @@ static int spi_nor_setup(struct spi_nor *nor,
> */
> static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
> {
> - if (nor->manufacturer && nor->manufacturer->fixups &&
> - nor->manufacturer->fixups->default_init)
> - nor->manufacturer->fixups->default_init(nor);
> + const struct spi_nor_fixup *fixups;
> + unsigned int i;
>
> - if (nor->info->fixups && nor->info->fixups->default_init)
> - nor->info->fixups->default_init(nor);
> + if (!nor->manufacturer || !nor->manufacturer->fixups)
> + return;
> +
> + fixups = nor->manufacturer->fixups;
> +
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->default_init &&
> + spi_nor_fixup_match(nor, &fixups[i]))
> + fixups[i].fixups->default_init(nor);
> + }
> }
>
> /**
> @@ -2797,22 +2829,24 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor)
> static int spi_nor_late_init_params(struct spi_nor *nor)
> {
> struct spi_nor_flash_parameter *params = nor->params;
> + const struct spi_nor_fixup *fixups;
> + unsigned int i;
> int ret;
>
> /* Needed by some late_init hooks */
> spi_nor_init_flags(nor);
>
> - if (nor->manufacturer && nor->manufacturer->fixups &&
> - nor->manufacturer->fixups->late_init) {
> - ret = nor->manufacturer->fixups->late_init(nor);
> - if (ret)
> - return ret;
> - }
> + if (nor->manufacturer && nor->manufacturer->fixups) {
> + fixups = nor->manufacturer->fixups;
>
> - if (nor->info->fixups && nor->info->fixups->late_init) {
> - ret = nor->info->fixups->late_init(nor);
> - if (ret)
> - return ret;
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->late_init &&
> + spi_nor_fixup_match(nor, &fixups[i])) {
> + ret = fixups[i].fixups->late_init(nor);
> + if (ret)
> + return ret;
> + }
> + }
> }
>
> if (!nor->params->opcodes.die_erase)
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 7d43d3ba47ee..b650778a10de 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -445,6 +445,19 @@ struct spi_nor_fixups {
> int (*late_init)(struct spi_nor *nor);
> };
>
> +/**
> + * struct spi_nor_fixup - SPI NOR fixup registration.
> + * @id: (optional) flash ID this fixup applies to, may only match the
> + * ID prefix, eg. just the first few bytes to match a whole family
> + * @match: (optional) custom match function (can be used together with @id)
> + * @fixups: the fixup hooks to apply when this entry matches
> + */
> +struct spi_nor_fixup {
> + const struct spi_nor_id *id;
> + bool (*match)(const struct spi_nor *nor);
> + const struct spi_nor_fixups *fixups;
> +};
> +
> /**
> * struct spi_nor_id - SPI NOR flash ID.
> *
> @@ -560,7 +573,6 @@ struct flash_info {
> u8 mfr_flags;
>
> const struct spi_nor_otp_organization *otp;
> - const struct spi_nor_fixups *fixups;
> };
>
> #define SNOR_ID(...) \
> @@ -582,13 +594,16 @@ struct flash_info {
> * @name: manufacturer name
> * @parts: array of parts supported by this manufacturer
> * @nparts: number of entries in the parts array
> - * @fixups: hooks called at various points in time during spi_nor_scan()
> + * @fixups: list of fixups, each matched by ID (or a custom match function),
> + * applied to any part of this manufacturer.
> + * @nfixups: number of entries in the fixups array
> */
> struct spi_nor_manufacturer {
> const char *name;
> const struct flash_info *parts;
> unsigned int nparts;
> - const struct spi_nor_fixups *fixups;
> + const struct spi_nor_fixup *fixups;
> + unsigned int nfixups;
> };
>
> /**
> @@ -619,6 +634,8 @@ extern const struct spi_nor_manufacturer spi_nor_xmc;
>
> extern const struct attribute_group *spi_nor_sysfs_groups[];
>
> +bool spi_nor_fixup_match(const struct spi_nor *nor,
> + const struct spi_nor_fixup *fixup);
> void spi_nor_spimem_setup_op(const struct spi_nor *nor,
> struct spi_mem_op *op,
> const enum spi_nor_protocol proto);
> diff --git a/drivers/mtd/spi-nor/everspin.c b/drivers/mtd/spi-nor/everspin.c
> index add37104d673..864dffba0e9c 100644
> --- a/drivers/mtd/spi-nor/everspin.c
> +++ b/drivers/mtd/spi-nor/everspin.c
> @@ -44,9 +44,14 @@ static const struct spi_nor_fixups everspin_nor_fixups = {
> .default_init = everspin_nor_default_init,
> };
>
> +static const struct spi_nor_fixup everspin_fixups[] = {
> + { .fixups = &everspin_nor_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_everspin = {
> .name = "everspin",
> .parts = everspin_nor_parts,
> .nparts = ARRAY_SIZE(everspin_nor_parts),
> - .fixups = &everspin_nor_fixups,
> + .fixups = everspin_fixups,
> + .nfixups = ARRAY_SIZE(everspin_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
> index 4070a692e968..f76fd0dedd0a 100644
> --- a/drivers/mtd/spi-nor/gigadevice.c
> +++ b/drivers/mtd/spi-nor/gigadevice.c
> @@ -64,7 +64,6 @@ static const struct flash_info gigadevice_nor_parts[] = {
> .id = SNOR_ID(0xc8, 0x40, 0x19),
> .name = "gd25q256",
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6,
> - .fixups = &gd25q256_fixups,
> .fixup_flags = SPI_NOR_4B_OPCODES,
The fixup_flags should also go into the fixups list.
> }, {
> .id = SNOR_ID(0xc8, 0x60, 0x16),
> @@ -87,8 +86,14 @@ static const struct flash_info gigadevice_nor_parts[] = {
> },
> };
>
> +static const struct spi_nor_fixup gigadevice_fixups[] = {
> + { .id = SNOR_ID(0xc8, 0x40, 0x19), .fixups = &gd25q256_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_gigadevice = {
> .name = "gigadevice",
> .parts = gigadevice_nor_parts,
> .nparts = ARRAY_SIZE(gigadevice_nor_parts),
> + .fixups = gigadevice_fixups,
> + .nfixups = ARRAY_SIZE(gigadevice_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
> index 04db42b5141e..4842f8acd074 100644
> --- a/drivers/mtd/spi-nor/issi.c
> +++ b/drivers/mtd/spi-nor/issi.c
> @@ -52,13 +52,11 @@ static const struct flash_info issi_nor_parts[] = {
> .sector_size = SZ_32K,
> .size = SZ_64K,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &pm25lv_nor_fixups
> }, {
> .name = "pm25lv010",
> .sector_size = SZ_32K,
> .size = SZ_128K,
> .no_sfdp_flags = SECT_4K,
> - .fixups = &pm25lv_nor_fixups
> }, {
> .id = SNOR_ID(0x7f, 0x9d, 0x20),
> .name = "is25cd512",
> @@ -103,7 +101,6 @@ static const struct flash_info issi_nor_parts[] = {
> }, {
> .id = SNOR_ID(0x9d, 0x60, 0x19),
> .name = "is25lp256",
> - .fixups = &is25lp256_fixups,
> .fixup_flags = SPI_NOR_4B_OPCODES,
> }, {
> .id = SNOR_ID(0x9d, 0x70, 0x16),
> @@ -124,7 +121,6 @@ static const struct flash_info issi_nor_parts[] = {
> .id = SNOR_ID(0x9d, 0x70, 0x19),
> .name = "is25wp256",
> .flags = SPI_NOR_QUAD_PP,
> - .fixups = &is25lp256_fixups,
> .fixup_flags = SPI_NOR_4B_OPCODES,
> }
> };
> @@ -139,9 +135,25 @@ static const struct spi_nor_fixups issi_fixups = {
> .default_init = issi_nor_default_init,
> };
>
> +/* PM25LV parts have no JEDEC ID and are likely matched by name */
> +static bool issi_pm25lv_match(const struct spi_nor *nor)
> +{
> + const char *name = nor->info ? nor->info->name : NULL;
> +
> + return name && !strncmp(name, "pm25lv", 6);
Won't just strcmp("pm25lv", name) do it? Both arguments are
guaranteed to be NUL terminated. The above would also match
"pm25lvextrabytes", no, and we get rid of that redundant size
argument.
> +}
> +
> +static const struct spi_nor_fixup issi_fixup_list[] = {
> + { .fixups = &issi_fixups },
> + { .match = issi_pm25lv_match, .fixups = &pm25lv_nor_fixups },
> + { .id = SNOR_ID(0x9d, 0x60, 0x19), .fixups = &is25lp256_fixups },
> + { .id = SNOR_ID(0x9d, 0x70, 0x19), .fixups = &is25lp256_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_issi = {
> .name = "issi",
> .parts = issi_nor_parts,
> .nparts = ARRAY_SIZE(issi_nor_parts),
> - .fixups = &issi_fixups,
> + .fixups = issi_fixup_list,
> + .nfixups = ARRAY_SIZE(issi_fixup_list),
> };
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index 55612237c1ef..04b431bf5f13 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -137,20 +137,16 @@ static const struct flash_info macronix_nor_parts[] = {
> }, {
> /* MX25L25635E, MX25L25645G */
> .id = SNOR_ID(0xc2, 0x20, 0x19),
> - .fixups = &mx25l25635_fixups
> }, {
> /* MX66L51235F */
> .id = SNOR_ID(0xc2, 0x20, 0x1a),
> .fixup_flags = SPI_NOR_4B_OPCODES,
> - .fixups = ¯onix_qpp4b_fixups,
> }, {
> /* MX66L1G45G */
> .id = SNOR_ID(0xc2, 0x20, 0x1b),
> - .fixups = ¯onix_qpp4b_fixups,
> }, {
> /* MX66L2G45G */
> .id = SNOR_ID(0xc2, 0x20, 0x1c),
> - .fixups = ¯onix_qpp4b_fixups,
> }, {
> .id = SNOR_ID(0xc2, 0x23, 0x14),
> .name = "mx25v8035f",
> @@ -189,15 +185,12 @@ static const struct flash_info macronix_nor_parts[] = {
> }, {
> /* MX25U51245G */
> .id = SNOR_ID(0xc2, 0x25, 0x3a),
> - .fixups = ¯onix_qpp4b_fixups,
> }, {
> /* MX66U1G45G */
> .id = SNOR_ID(0xc2, 0x25, 0x3b),
> - .fixups = ¯onix_qpp4b_fixups,
> }, {
> /* MX66U2G45G */
> .id = SNOR_ID(0xc2, 0x25, 0x3c),
> - .fixups = ¯onix_qpp4b_fixups,
> }, {
> .id = SNOR_ID(0xc2, 0x26, 0x18),
> .name = "mx25l12855e",
> @@ -229,7 +222,6 @@ static const struct flash_info macronix_nor_parts[] = {
> }, {
> /* MX25L3255E */
> .id = SNOR_ID(0xc2, 0x9e, 0x16),
> - .fixups = &mx25l3255e_fixups,
> },
> /*
> * This spares us of adding new flash entries for flashes that can be
> @@ -333,9 +325,22 @@ static const struct spi_nor_fixups macronix_nor_fixups = {
> .late_init = macronix_nor_late_init,
> };
>
> +static const struct spi_nor_fixup macronix_fixups[] = {
> + { .fixups = ¯onix_nor_fixups },
> + { .id = SNOR_ID(0xc2, 0x20, 0x19), .fixups = &mx25l25635_fixups },
> + { .id = SNOR_ID(0xc2, 0x20, 0x1a), .fixups = ¯onix_qpp4b_fixups },
> + { .id = SNOR_ID(0xc2, 0x20, 0x1b), .fixups = ¯onix_qpp4b_fixups },
> + { .id = SNOR_ID(0xc2, 0x20, 0x1c), .fixups = ¯onix_qpp4b_fixups },
> + { .id = SNOR_ID(0xc2, 0x25, 0x3a), .fixups = ¯onix_qpp4b_fixups },
> + { .id = SNOR_ID(0xc2, 0x25, 0x3b), .fixups = ¯onix_qpp4b_fixups },
> + { .id = SNOR_ID(0xc2, 0x25, 0x3c), .fixups = ¯onix_qpp4b_fixups },
> + { .id = SNOR_ID(0xc2, 0x9e, 0x16), .fixups = &mx25l3255e_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_macronix = {
> .name = "macronix",
> .parts = macronix_nor_parts,
> .nparts = ARRAY_SIZE(macronix_nor_parts),
> - .fixups = ¯onix_nor_fixups,
> + .fixups = macronix_fixups,
> + .nfixups = ARRAY_SIZE(macronix_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
> index 344539d2a36a..2aabd6d487ba 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -206,13 +206,11 @@ static const struct flash_info micron_nor_parts[] = {
> .id = SNOR_ID(0x2c, 0x5b, 0x1a),
> .mfr_flags = USE_FSR,
> .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE,
> - .fixups = &mt35xu512aba_fixups,
> }, {
> /* MT35XU01GBBA */
> .id = SNOR_ID(0x2c, 0x5b, 0x1b),
> .mfr_flags = USE_FSR,
> .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE,
> - .fixups = &mt35_two_die_fixups,
> }, {
> .id = SNOR_ID(0x2c, 0x5b, 0x1c),
> .name = "mt35xu02g",
> @@ -221,7 +219,6 @@ static const struct flash_info micron_nor_parts[] = {
> .no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ,
> .mfr_flags = USE_FSR,
> .fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,
> - .fixups = &mt35_two_die_fixups,
> },
> };
>
> @@ -233,6 +230,17 @@ static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor,
> return 0;
> }
>
> +/*
> + * n25q00a parts share the first same 3 ID bytes with mt25qu01g.
> + * In order to not mix the fixups, further filter out using the part name.
How would that work? The part name is also set by the duplicated ID,
so the first one wins, no?
-michael
> + */
> +static bool n25q00a_match(const struct spi_nor *nor)
> +{
> + const char *name = nor->info ? nor->info->name : NULL;
> +
> + return name && !strncmp(name, "n25q00a", 7);
> +}
> +
> static const struct spi_nor_fixups mt25qu512a_fixups = {
> .post_bfpt = mt25qu512a_post_bfpt_fixup,
> };
> @@ -426,14 +434,12 @@ static const struct flash_info st_nor_parts[] = {
> SPI_NOR_BP3_SR_BIT6,
> .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
> .mfr_flags = USE_FSR,
> - .fixups = &n25q00_fixups,
> }, {
> .id = SNOR_ID(0x20, 0xba, 0x22),
> .name = "mt25ql02g",
> .size = SZ_256M,
> .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
> .mfr_flags = USE_FSR,
> - .fixups = &mt25q02_fixups,
> }, {
> .id = SNOR_ID(0x20, 0xbb, 0x15),
> .name = "n25q016a",
> @@ -480,7 +486,6 @@ static const struct flash_info st_nor_parts[] = {
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
> SPI_NOR_BP3_SR_BIT6,
> .mfr_flags = USE_FSR,
> - .fixups = &mt25qu512a_fixups,
> }, {
> .id = SNOR_ID(0x20, 0xbb, 0x20),
> .name = "n25q512a",
> @@ -493,21 +498,18 @@ static const struct flash_info st_nor_parts[] = {
> .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00),
> .name = "mt25qu01g",
> .mfr_flags = USE_FSR,
> - .fixups = &mt25q01_fixups,
> }, {
> .id = SNOR_ID(0x20, 0xbb, 0x21),
> .name = "n25q00a",
> .size = SZ_128M,
> .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
> .mfr_flags = USE_FSR,
> - .fixups = &n25q00_fixups,
> }, {
> .id = SNOR_ID(0x20, 0xbb, 0x22),
> .name = "mt25qu02g",
> .size = SZ_256M,
> .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> .mfr_flags = USE_FSR,
> - .fixups = &mt25q02_fixups,
> }
> };
>
> @@ -657,16 +659,35 @@ static const struct spi_nor_fixups micron_st_nor_fixups = {
> .late_init = micron_st_nor_late_init,
> };
>
> +static const struct spi_nor_fixup micron_fixups[] = {
> + { .fixups = µn_st_nor_fixups },
> + { .id = SNOR_ID(0x2c, 0x5b, 0x1a), .fixups = &mt35xu512aba_fixups },
> + { .id = SNOR_ID(0x2c, 0x5b, 0x1b), .fixups = &mt35_two_die_fixups },
> + { .id = SNOR_ID(0x2c, 0x5b, 0x1c), .fixups = &mt35_two_die_fixups },
> +};
> +
> +static const struct spi_nor_fixup st_fixups[] = {
> + { .fixups = µn_st_nor_fixups },
> + { .id = SNOR_ID(0x20, 0xba, 0x21), .fixups = &n25q00_fixups },
> + { .id = SNOR_ID(0x20, 0xba, 0x22), .fixups = &mt25q02_fixups },
> + { .id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00), .fixups = &mt25qu512a_fixups },
> + { .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00), .fixups = &mt25q01_fixups },
> + { .id = SNOR_ID(0x20, 0xbb, 0x21), .match = n25q00a_match, .fixups = &n25q00_fixups },
> + { .id = SNOR_ID(0x20, 0xbb, 0x22), .fixups = &mt25q02_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_micron = {
> .name = "micron",
> .parts = micron_nor_parts,
> .nparts = ARRAY_SIZE(micron_nor_parts),
> - .fixups = µn_st_nor_fixups,
> + .fixups = micron_fixups,
> + .nfixups = ARRAY_SIZE(micron_fixups),
> };
>
> const struct spi_nor_manufacturer spi_nor_st = {
> .name = "st",
> .parts = st_nor_parts,
> .nparts = ARRAY_SIZE(st_nor_parts),
> - .fixups = µn_st_nor_fixups,
> + .fixups = st_fixups,
> + .nfixups = ARRAY_SIZE(st_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
> index 285ac781fba8..39cb8ac3a037 100644
> --- a/drivers/mtd/spi-nor/sfdp.c
> +++ b/drivers/mtd/spi-nor/sfdp.c
> @@ -727,12 +727,19 @@ static u8 spi_nor_smpt_addr_nbytes(const struct spi_nor *nor, const u32 settings
> static void spi_nor_smpt_read_dummy_fixups(const struct spi_nor *nor,
> u8 *read_dummy)
> {
> - if (nor->manufacturer && nor->manufacturer->fixups &&
> - nor->manufacturer->fixups->smpt_read_dummy)
> - nor->manufacturer->fixups->smpt_read_dummy(nor, read_dummy);
> + const struct spi_nor_fixup *fixups;
> + unsigned int i;
>
> - if (nor->info->fixups && nor->info->fixups->smpt_read_dummy)
> - nor->info->fixups->smpt_read_dummy(nor, read_dummy);
> + if (!nor->manufacturer || !nor->manufacturer->fixups)
> + return;
> +
> + fixups = nor->manufacturer->fixups;
> +
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->smpt_read_dummy &&
> + spi_nor_fixup_match(nor, &fixups[i]))
> + fixups[i].fixups->smpt_read_dummy(nor, read_dummy);
> + }
> }
>
> /**
> @@ -757,12 +764,19 @@ static u8 spi_nor_smpt_read_dummy(const struct spi_nor *nor, const u32 settings)
>
> static void spi_nor_smpt_map_id_fixups(const struct spi_nor *nor, u8 *map_id)
> {
> - if (nor->manufacturer && nor->manufacturer->fixups &&
> - nor->manufacturer->fixups->smpt_map_id)
> - nor->manufacturer->fixups->smpt_map_id(nor, map_id);
> + const struct spi_nor_fixup *fixups;
> + unsigned int i;
>
> - if (nor->info->fixups && nor->info->fixups->smpt_map_id)
> - nor->info->fixups->smpt_map_id(nor, map_id);
> + if (!nor->manufacturer || !nor->manufacturer->fixups)
> + return;
> +
> + fixups = nor->manufacturer->fixups;
> +
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->smpt_map_id &&
> + spi_nor_fixup_match(nor, &fixups[i]))
> + fixups[i].fixups->smpt_map_id(nor, map_id);
> + }
> }
>
> /**
> @@ -1406,17 +1420,23 @@ static int spi_nor_parse_sccr_mc(struct spi_nor *nor,
> */
> static int spi_nor_post_sfdp_fixups(struct spi_nor *nor)
> {
> + const struct spi_nor_fixup *fixups;
> + unsigned int i;
> int ret;
>
> - if (nor->manufacturer && nor->manufacturer->fixups &&
> - nor->manufacturer->fixups->post_sfdp) {
> - ret = nor->manufacturer->fixups->post_sfdp(nor);
> - if (ret)
> - return ret;
> - }
> + if (!nor->manufacturer || !nor->manufacturer->fixups)
> + return 0;
>
> - if (nor->info->fixups && nor->info->fixups->post_sfdp)
> - return nor->info->fixups->post_sfdp(nor);
> + fixups = nor->manufacturer->fixups;
> +
> + for (i = 0; i < nor->manufacturer->nfixups; i++) {
> + if (fixups[i].fixups->post_sfdp &&
> + spi_nor_fixup_match(nor, &fixups[i])) {
> + ret = fixups[i].fixups->post_sfdp(nor);
> + if (ret)
> + return ret;
> + }
> + }
>
> return 0;
> }
> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
> index ca2703a5a338..f3862eb1a23a 100644
> --- a/drivers/mtd/spi-nor/spansion.c
> +++ b/drivers/mtd/spi-nor/spansion.c
> @@ -905,7 +905,6 @@ static const struct flash_info spansion_nor_parts[] = {
> .sector_size = SZ_256K,
> .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> .mfr_flags = USE_CLSR,
> - .fixups = &s25fs_s_nor_fixups,
> }, {
> .id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x00),
> .name = "s25sl12800",
> @@ -941,7 +940,6 @@ static const struct flash_info spansion_nor_parts[] = {
> .size = SZ_16M,
> .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> .mfr_flags = USE_CLSR,
> - .fixups = &s25fs_s_nor_fixups,
> }, {
> .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01),
> .name = "s25fl129p1",
> @@ -1001,76 +999,61 @@ static const struct flash_info spansion_nor_parts[] = {
> .id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90),
> .name = "s25hl512t",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25hx_t_fixups
> }, {
> .id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90),
> .name = "s25hl01gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25hx_t_fixups
> }, {
> .id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90),
> .name = "s25hl02gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25hx_t_fixups
> }, {
> .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90),
> .name = "s25fs256t",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25fs256t_fixups
> }, {
> .id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90),
> .name = "s25hs512t",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25hx_t_fixups
> }, {
> .id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90),
> .name = "s25hs01gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25hx_t_fixups
> }, {
> .id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90),
> .name = "s25hs02gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s25hx_t_fixups
> }, {
> /* S28HL256T */
> .id = SNOR_ID(0x34, 0x5a, 0x19),
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0x34, 0x5a, 0x1a),
> .name = "s28hl512t",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0x34, 0x5a, 0x1b),
> .name = "s28hl01gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> /* S28HL02GT */
> .id = SNOR_ID(0x34, 0x5a, 0x1c),
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0x34, 0x5b, 0x19),
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0x34, 0x5b, 0x1a),
> .name = "s28hs512t",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0x34, 0x5b, 0x1b),
> .name = "s28hs01gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0x34, 0x5b, 0x1c),
> .name = "s28hs02gt",
> .mfr_flags = USE_CLPEF,
> - .fixups = &s28hx_t_fixups,
> }, {
> .id = SNOR_ID(0xef, 0x40, 0x13),
> .name = "s25fl004k",
> @@ -1170,9 +1153,31 @@ static const struct spi_nor_fixups spansion_nor_fixups = {
> .late_init = spansion_nor_late_init,
> };
>
> +static const struct spi_nor_fixup spansion_fixups[] = {
> + { .fixups = &spansion_nor_fixups },
> + { .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x81), .fixups = &s25fs_s_nor_fixups },
> + { .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x81), .fixups = &s25fs_s_nor_fixups },
> + { .id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90), .fixups = &s25hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90), .fixups = &s25fs256t_fixups },
> + { .id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90), .fixups = &s25hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90), .fixups = &s25hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5a, 0x19), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5a, 0x1a), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5a, 0x1b), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5a, 0x1c), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5b, 0x19), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5b, 0x1a), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5b, 0x1b), .fixups = &s28hx_t_fixups },
> + { .id = SNOR_ID(0x34, 0x5b, 0x1c), .fixups = &s28hx_t_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_spansion = {
> .name = "spansion",
> .parts = spansion_nor_parts,
> .nparts = ARRAY_SIZE(spansion_nor_parts),
> - .fixups = &spansion_nor_fixups,
> + .fixups = spansion_fixups,
> + .nfixups = ARRAY_SIZE(spansion_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
> index 77a0bc41d4e5..c460803b278b 100644
> --- a/drivers/mtd/spi-nor/sst.c
> +++ b/drivers/mtd/spi-nor/sst.c
> @@ -152,14 +152,12 @@ static const struct flash_info sst_nor_parts[] = {
> .id = SNOR_ID(0xbf, 0x26, 0x42),
> .name = "sst26vf032b",
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> - .fixups = &sst26vf_nor_fixups,
> }, {
> .id = SNOR_ID(0xbf, 0x26, 0x43),
> .name = "sst26vf064b",
> .size = SZ_8M,
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE,
> .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> - .fixups = &sst26vf_nor_fixups,
> }, {
> .id = SNOR_ID(0xbf, 0x26, 0x51),
> .name = "sst26wf016b",
> @@ -278,9 +276,16 @@ static const struct spi_nor_fixups sst_nor_fixups = {
> .late_init = sst_nor_late_init,
> };
>
> +static const struct spi_nor_fixup sst_fixups[] = {
> + { .fixups = &sst_nor_fixups },
> + { .id = SNOR_ID(0xbf, 0x26, 0x42), .fixups = &sst26vf_nor_fixups },
> + { .id = SNOR_ID(0xbf, 0x26, 0x43), .fixups = &sst26vf_nor_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_sst = {
> .name = "sst",
> .parts = sst_nor_parts,
> .nparts = ARRAY_SIZE(sst_nor_parts),
> - .fixups = &sst_nor_fixups,
> + .fixups = sst_fixups,
> + .nfixups = ARRAY_SIZE(sst_fixups),
> };
> diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
> index 01a693033448..583b1669270f 100644
> --- a/drivers/mtd/spi-nor/winbond.c
> +++ b/drivers/mtd/spi-nor/winbond.c
> @@ -219,7 +219,6 @@ static const struct flash_info winbond_nor_parts[] = {
> .size = SZ_16M,
> .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> .flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_HAS_CMP,
> - .fixups = &w25q128_fixups,
> }, {
> /* W25Q256JV-Q/N */
> .id = SNOR_ID(0xef, 0x40, 0x19),
> @@ -228,7 +227,6 @@ static const struct flash_info winbond_nor_parts[] = {
> .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
> .flags = SPI_NOR_QUAD_PP | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
> SPI_NOR_TB_SR_BIT6 | SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
> - .fixups = &w25q256_fixups,
> }, {
> /* W25Q512JV-Q/N */
> .id = SNOR_ID(0xef, 0x40, 0x20),
> @@ -242,7 +240,6 @@ static const struct flash_info winbond_nor_parts[] = {
> .id = SNOR_ID(0xef, 0x40, 0x21),
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
> SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
> - .fixups = &winbond_nor_multi_die_fixups,
> }, {
> .id = SNOR_ID(0xef, 0x50, 0x12),
> .name = "w25q20bw",
> @@ -345,13 +342,11 @@ static const struct flash_info winbond_nor_parts[] = {
> .id = SNOR_ID(0xef, 0x70, 0x21),
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
> SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
> - .fixups = &winbond_nor_multi_die_fixups,
> }, {
> /* W25Q02JV-M */
> .id = SNOR_ID(0xef, 0x70, 0x22),
> .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |
> SPI_NOR_4BIT_BP | SPI_NOR_HAS_CMP,
> - .fixups = &winbond_nor_multi_die_fixups,
> }, {
> .id = SNOR_ID(0xef, 0x71, 0x19),
> .name = "w25m512jv",
> @@ -553,9 +548,19 @@ static const struct spi_nor_fixups winbond_nor_fixups = {
> .late_init = winbond_nor_late_init,
> };
>
> +static const struct spi_nor_fixup winbond_fixups[] = {
> + { .fixups = &winbond_nor_fixups },
> + { .id = SNOR_ID(0xef, 0x40, 0x18), .fixups = &w25q128_fixups },
> + { .id = SNOR_ID(0xef, 0x40, 0x19), .fixups = &w25q256_fixups },
> + { .id = SNOR_ID(0xef, 0x40, 0x21), .fixups = &winbond_nor_multi_die_fixups },
> + { .id = SNOR_ID(0xef, 0x70, 0x21), .fixups = &winbond_nor_multi_die_fixups },
> + { .id = SNOR_ID(0xef, 0x70, 0x22), .fixups = &winbond_nor_multi_die_fixups },
> +};
> +
> const struct spi_nor_manufacturer spi_nor_winbond = {
> .name = "winbond",
> .parts = winbond_nor_parts,
> .nparts = ARRAY_SIZE(winbond_nor_parts),
> - .fixups = &winbond_nor_fixups,
> + .fixups = winbond_fixups,
> + .nfixups = ARRAY_SIZE(winbond_fixups),
> };
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^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 06/23] mtd: spi-nor: Create an indirection on the part name
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:41 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:41 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
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On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> We currently print through sysfs and debugfs the name of the part if the
> .name field, which is legacy, has been filled in the ID table (otherwise
> "(null)" is printed). These IDs had an interest until manufacturers
> started re-using more and more extensively the so called unique JEDEC
> IDs. At this stage, a name that was tailored for a chip sold in 2016 may
> no longer be relevant for a chip sold in 2026. Still showing this name
> through the various filesystems may confuse people, removing these names
> cannot be done since they are now part of the user ABI (because of
> sysfs).
>
> In order to allow overwriting the .name field (which is part of a
> read-only structure), let's create a spi-nor pointer which will by
> default point to that .name, but which can be cleared in fixup hooks to
> make sure the name is hidden on newer parts.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
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______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 06/23] mtd: spi-nor: Create an indirection on the part name
@ 2026-08-14 9:41 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:41 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 1040 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> We currently print through sysfs and debugfs the name of the part if the
> .name field, which is legacy, has been filled in the ID table (otherwise
> "(null)" is printed). These IDs had an interest until manufacturers
> started re-using more and more extensively the so called unique JEDEC
> IDs. At this stage, a name that was tailored for a chip sold in 2016 may
> no longer be relevant for a chip sold in 2026. Still showing this name
> through the various filesystems may confuse people, removing these names
> cannot be done since they are now part of the user ABI (because of
> sysfs).
>
> In order to allow overwriting the .name field (which is part of a
> read-only structure), let's create a spi-nor pointer which will by
> default point to that .name, but which can be cleared in fixup hooks to
> make sure the name is hidden on newer parts.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
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^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 07/23] mtd: spi-nor: Move the SFDP header structure to a C header
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:41 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:41 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
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On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> The sfdp_header structure is currently defined in sfdp.c, whereas the
> sfdp_parameter_header structure is defined in sfdp.h. In order to ease
> the reuse of this structure outside of the sfdp.c file, move this
> structure to the sfdp C header (.h).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
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^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 07/23] mtd: spi-nor: Move the SFDP header structure to a C header
@ 2026-08-14 9:41 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:41 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 430 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> The sfdp_header structure is currently defined in sfdp.c, whereas the
> sfdp_parameter_header structure is defined in sfdp.h. In order to ease
> the reuse of this structure outside of the sfdp.c file, move this
> structure to the sfdp C header (.h).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
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______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 08/23] mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-Q/N parts
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:46 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:46 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 4157 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision between the JV and RV families. Both chips are
> very similar in practice, it is mostly a matter of electrical
> differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2 opcode
> (0x31). They also do not require the multi-die fixups which must remain
> assigned to the JV chips.
>
> Finally, since they share the IDs but not the names, we must hide the
> names using a fixup.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
With a comment below.
> ---
> drivers/mtd/spi-nor/winbond.c | 56 ++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 53 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
> index 583b1669270f..8c1cad9e21b4 100644
> --- a/drivers/mtd/spi-nor/winbond.c
> +++ b/drivers/mtd/spi-nor/winbond.c
> @@ -146,6 +146,51 @@ static const struct spi_nor_fixups winbond_nor_multi_die_fixups = {
> .post_sfdp = winbond_nor_multi_die_post_sfdp_fixups,
> };
>
> +static int winbond_nor_partname_post_sfdp_fixups(struct spi_nor *nor)
> +{
> + /*
> + * W25QxxRV parts re-use the JEDEC IDs of the JV family. Their name
> + * being a legacy field, it is kept for the already established JV parts
> + * but must not be exposed by the newer RV ones.
> + */
> + nor->partname = NULL;
> +
> + return 0;
> +}
> +
> +static const struct spi_nor_fixups winbond_nor_partname_fixups = {
> + .post_sfdp = winbond_nor_partname_post_sfdp_fixups,
> +};
> +
> +static bool is_w25qxxrv(const struct spi_nor *nor)
> +{
> + struct sfdp_header *sfdp_h = (struct sfdp_header *)nor->sfdp->dwords;
nitpick, spi_nor_sfdp_get_header()?
> +
> + /*
> + * W25QxxRV chips re-use the same ID as the W25QxxJV family.
> + *
> + * Chips are very similar, W25QxxRV brings mostly performance and power
> + * consumption improvements. The RV family does not require the multi
> + * die fixup.
> + *
> + * They can be distinguished based on their SFDP minor revision:
> + * W25QxxJV: JESD216A, minor revision == 05h
> + * W25Q512/01/02JV: JESD216B, minor revision == 06h
> + * W25QxxRV: JESD216F, minor revision >= 0Ah
> + */
> + return sfdp_h->minor >= SFDP_JESD216F_MINOR;
> +}
> +
> +static bool winbond_jv_match(const struct spi_nor *nor)
> +{
> + return !nor->sfdp || !is_w25qxxrv(nor);
So how do we know if nor->sfdp is already there for a given fixup.
Without having looked at the code, there could potentially be fixups
before SFDP is parsed (and the nor->sfdp is populated), right? Might
be worth to be mentioned somewhere.
-michael
> +}
> +
> +static bool winbond_rv_match(const struct spi_nor *nor)
> +{
> + return nor->sfdp && is_w25qxxrv(nor);
> +}
> +
> static const struct flash_info winbond_nor_parts[] = {
> {
> .id = SNOR_ID(0xef, 0x30, 0x10),
> @@ -552,9 +597,14 @@ static const struct spi_nor_fixup winbond_fixups[] = {
> { .fixups = &winbond_nor_fixups },
> { .id = SNOR_ID(0xef, 0x40, 0x18), .fixups = &w25q128_fixups },
> { .id = SNOR_ID(0xef, 0x40, 0x19), .fixups = &w25q256_fixups },
> - { .id = SNOR_ID(0xef, 0x40, 0x21), .fixups = &winbond_nor_multi_die_fixups },
> - { .id = SNOR_ID(0xef, 0x70, 0x21), .fixups = &winbond_nor_multi_die_fixups },
> - { .id = SNOR_ID(0xef, 0x70, 0x22), .fixups = &winbond_nor_multi_die_fixups },
> + { .id = SNOR_ID(0xef, 0x40), .match = winbond_rv_match,
> + .fixups = &winbond_nor_partname_fixups },
> + { .id = SNOR_ID(0xef, 0x40, 0x21), .match = winbond_jv_match,
> + .fixups = &winbond_nor_multi_die_fixups },
> + { .id = SNOR_ID(0xef, 0x70, 0x21), .match = winbond_jv_match,
> + .fixups = &winbond_nor_multi_die_fixups },
> + { .id = SNOR_ID(0xef, 0x70, 0x22), .match = winbond_jv_match,
> + .fixups = &winbond_nor_multi_die_fixups },
> };
>
> const struct spi_nor_manufacturer spi_nor_winbond = {
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______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 08/23] mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-Q/N parts
@ 2026-08-14 9:46 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:46 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 4157 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision between the JV and RV families. Both chips are
> very similar in practice, it is mostly a matter of electrical
> differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2 opcode
> (0x31). They also do not require the multi-die fixups which must remain
> assigned to the JV chips.
>
> Finally, since they share the IDs but not the names, we must hide the
> names using a fixup.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
With a comment below.
> ---
> drivers/mtd/spi-nor/winbond.c | 56 ++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 53 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
> index 583b1669270f..8c1cad9e21b4 100644
> --- a/drivers/mtd/spi-nor/winbond.c
> +++ b/drivers/mtd/spi-nor/winbond.c
> @@ -146,6 +146,51 @@ static const struct spi_nor_fixups winbond_nor_multi_die_fixups = {
> .post_sfdp = winbond_nor_multi_die_post_sfdp_fixups,
> };
>
> +static int winbond_nor_partname_post_sfdp_fixups(struct spi_nor *nor)
> +{
> + /*
> + * W25QxxRV parts re-use the JEDEC IDs of the JV family. Their name
> + * being a legacy field, it is kept for the already established JV parts
> + * but must not be exposed by the newer RV ones.
> + */
> + nor->partname = NULL;
> +
> + return 0;
> +}
> +
> +static const struct spi_nor_fixups winbond_nor_partname_fixups = {
> + .post_sfdp = winbond_nor_partname_post_sfdp_fixups,
> +};
> +
> +static bool is_w25qxxrv(const struct spi_nor *nor)
> +{
> + struct sfdp_header *sfdp_h = (struct sfdp_header *)nor->sfdp->dwords;
nitpick, spi_nor_sfdp_get_header()?
> +
> + /*
> + * W25QxxRV chips re-use the same ID as the W25QxxJV family.
> + *
> + * Chips are very similar, W25QxxRV brings mostly performance and power
> + * consumption improvements. The RV family does not require the multi
> + * die fixup.
> + *
> + * They can be distinguished based on their SFDP minor revision:
> + * W25QxxJV: JESD216A, minor revision == 05h
> + * W25Q512/01/02JV: JESD216B, minor revision == 06h
> + * W25QxxRV: JESD216F, minor revision >= 0Ah
> + */
> + return sfdp_h->minor >= SFDP_JESD216F_MINOR;
> +}
> +
> +static bool winbond_jv_match(const struct spi_nor *nor)
> +{
> + return !nor->sfdp || !is_w25qxxrv(nor);
So how do we know if nor->sfdp is already there for a given fixup.
Without having looked at the code, there could potentially be fixups
before SFDP is parsed (and the nor->sfdp is populated), right? Might
be worth to be mentioned somewhere.
-michael
> +}
> +
> +static bool winbond_rv_match(const struct spi_nor *nor)
> +{
> + return nor->sfdp && is_w25qxxrv(nor);
> +}
> +
> static const struct flash_info winbond_nor_parts[] = {
> {
> .id = SNOR_ID(0xef, 0x30, 0x10),
> @@ -552,9 +597,14 @@ static const struct spi_nor_fixup winbond_fixups[] = {
> { .fixups = &winbond_nor_fixups },
> { .id = SNOR_ID(0xef, 0x40, 0x18), .fixups = &w25q128_fixups },
> { .id = SNOR_ID(0xef, 0x40, 0x19), .fixups = &w25q256_fixups },
> - { .id = SNOR_ID(0xef, 0x40, 0x21), .fixups = &winbond_nor_multi_die_fixups },
> - { .id = SNOR_ID(0xef, 0x70, 0x21), .fixups = &winbond_nor_multi_die_fixups },
> - { .id = SNOR_ID(0xef, 0x70, 0x22), .fixups = &winbond_nor_multi_die_fixups },
> + { .id = SNOR_ID(0xef, 0x40), .match = winbond_rv_match,
> + .fixups = &winbond_nor_partname_fixups },
> + { .id = SNOR_ID(0xef, 0x40, 0x21), .match = winbond_jv_match,
> + .fixups = &winbond_nor_multi_die_fixups },
> + { .id = SNOR_ID(0xef, 0x70, 0x21), .match = winbond_jv_match,
> + .fixups = &winbond_nor_multi_die_fixups },
> + { .id = SNOR_ID(0xef, 0x70, 0x22), .match = winbond_jv_match,
> + .fixups = &winbond_nor_multi_die_fixups },
> };
>
> const struct spi_nor_manufacturer spi_nor_winbond = {
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^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 09/23] mtd: spi-nor: winbond: Add support for W25Q32RV-Q/N
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:46 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:46 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 549 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 09/23] mtd: spi-nor: winbond: Add support for W25Q32RV-Q/N
@ 2026-08-14 9:46 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:46 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 549 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 10/23] mtd: spi-nor: winbond: Add support for W25Q64RV-Q/N
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:46 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:46 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 549 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 10/23] mtd: spi-nor: winbond: Add support for W25Q64RV-Q/N
@ 2026-08-14 9:46 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:46 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 549 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 11/23] mtd: spi-nor: winbond: Add support for W25Q12RV-Q/N
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:47 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:47 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 549 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 11/23] mtd: spi-nor: winbond: Add support for W25Q12RV-Q/N
@ 2026-08-14 9:47 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:47 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 549 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 12/23] mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:47 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:47 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 547 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 12/23] mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N
@ 2026-08-14 9:47 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:47 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 547 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 13/23] mtd: spi-nor: winbond: Add support for W25Q01RV-Q/N
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:47 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:47 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 486 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 13/23] mtd: spi-nor: winbond: Add support for W25Q01RV-Q/N
@ 2026-08-14 9:47 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:47 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 486 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 14/23] mtd: spi-nor: winbond: Add support for W25Q02RV-Q/N
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:48 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:48 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 547 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 14/23] mtd: spi-nor: winbond: Add support for W25Q02RV-Q/N
@ 2026-08-14 9:48 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:48 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 547 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 15/23] mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-M parts
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:50 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:50 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 620 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision between the JV and RV families. Both chips are
> very similar in practice, it is mostly a matter of electrical
> differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> The new SFDP (rev F) field which forces an alternate write SR2 opcode
> (0x31).
>
> Since they share the IDs but not the names, we must hide the names using
> a fixup.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 15/23] mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-M parts
@ 2026-08-14 9:50 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:50 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 620 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision between the JV and RV families. Both chips are
> very similar in practice, it is mostly a matter of electrical
> differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> The new SFDP (rev F) field which forces an alternate write SR2 opcode
> (0x31).
>
> Since they share the IDs but not the names, we must hide the names using
> a fixup.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 16/23] mtd: spi-nor: winbond: Add support for W25Q32RV-M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:50 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:50 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 547 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 16/23] mtd: spi-nor: winbond: Add support for W25Q32RV-M
@ 2026-08-14 9:50 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:50 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 547 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 17/23] mtd: spi-nor: winbond: Add support for W25Q64RV-M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:51 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:51 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 547 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 17/23] mtd: spi-nor: winbond: Add support for W25Q64RV-M
@ 2026-08-14 9:51 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:51 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 547 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 18/23] mtd: spi-nor: winbond: Add support for W25Q12RV-M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:51 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:51 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 547 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 18/23] mtd: spi-nor: winbond: Add support for W25Q12RV-M
@ 2026-08-14 9:51 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:51 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 547 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 19/23] mtd: spi-nor: winbond: Add support for W25Q51RV-M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:52 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:52 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 549 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 19/23] mtd: spi-nor: winbond: Add support for W25Q51RV-M
@ 2026-08-14 9:52 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:52 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 549 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 20/23] mtd: spi-nor: winbond: Add support for W25Q01RV-M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:52 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:52 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 549 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 20/23] mtd: spi-nor: winbond: Add support for W25Q01RV-M
@ 2026-08-14 9:52 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:52 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 549 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 21/23] mtd: spi-nor: winbond: Add support for W25Q02RV-M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:52 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:52 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 549 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 21/23] mtd: spi-nor: winbond: Add support for W25Q02RV-M
@ 2026-08-14 9:52 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:52 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 549 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> There is an ID collision with the chip of same density from the JV
> family. Both chips are very similar in practice, it is mostly a matter
> of electrical differences (mostly power consumption being lower).
>
> As a significant difference, RV chips identify themselves as supporting
> the new SFDP (rev F) field which forces an alternate write SR2
> opcode (0x31).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 22/23] mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N/M
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 9:53 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:53 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 481 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> I currently do not have access to any chips from the W25Q25RV
> density. Yet, I successfully tested the entire JV family and all other
> chips from the RV family. They all behaved strictly identically, so I
> propose to nevertheless add the missing comments for the sake of clarity
> and completeness.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
[-- Attachment #2: Type: text/plain, Size: 144 bytes --]
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 22/23] mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N/M
@ 2026-08-14 9:53 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 9:53 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 481 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> I currently do not have access to any chips from the W25Q25RV
> density. Yet, I successfully tested the entire JV family and all other
> chips from the RV family. They all behaved strictly identically, so I
> propose to nevertheless add the missing comments for the sake of clarity
> and completeness.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 03/23] mtd: spi-nor: Refactor Read Status/Write Status support
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 12:25 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 12:25 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 61787 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> SPI NOR has a lot of history. Additions over additions, the subtleties
> of the JESD216 specification, their implementations by the manufacturers
> and the hardware mistakes have generated a gigantic maze, let's try to
> understand what is really needed.
>
> The specification explains the QE (Quad Enable) bitfield as describing
> where the bit to enable the Quad capability is, but also how to set
> it. Unfortunately, the specification is not precise about what opcodes
> are supported exactly in all the cases. There is an introduction that
> basically states:
> - Opcode 0x05 reads SR1
> - Opcode 0x35 reads SR2
> - Opcode 0x01 writes SR1, and then SR2 if another byte is written
>
> Then the bitfield, among indicating the location of the QE bit, may
> indicate:
> - Reading SR1 and SR2 in one operation is not possible (loops over the
> content of SR1)
> - Reading SR2 directly is possible
> - Only writing SR1 zeroes SR2.
>
> One problem with the current implementation, is that it only focuses on
> the QE bit. A quad_enable function was created for each case, even
> though in practice, the logic was always the same: read, modify, write,
> read back and verify. One problem comes when other features need to play
> with the status registers, like software block protection or OTP: you
> never know how to properly handle the QE bit, nor where it is, nor how
> to read/write the Status registers. This lead to
> approximations/guessing (in swp.c, otp.c and obviously in legacy
> controller drivers like atmel.c) but also to the implementation of a
> gazillon of helpers for reading/writing/checking the status registers.
>
> In addition, I believe some design decisions had a negative impact over
> the years.
>
> - All possible situations had to be flagged by the core. This is likely
> wrong, because we no longer know why we need specific quirks. It was
> ineherent to the state of the SPI NOR core before the great cleanup
> that had happened the past few years. I believe this creates confusion
> in the core today, and we should push this to vendor fixups
> instead. As an example, in 2023 Hsin-Yi was facing an issue because
> his chip was setting the wrong QER value, leading to RDCR being
> prevented, thus falling into a condition blindly setting a random QE
> bit (I strongy believe it is done like that for wrong reasons). His
> chip actually had RDCR support! The correct fix should have been to
> mark the capability in a device fixup instead of handling this in the
> core.
>
> Link: https://lore.kernel.org/lkml/CAJMQK-hR0eaO0b4Vd0U8_KAndLyZapqdHjVLAoe42rWi9rdLkA@mail.gmail.com/
>
> - SFDP parsing is over cautious. I believe
> BFPT_DWORD15_QER_SR2_BIT1_NO_RD is abusive (nothing states that RDCR is
> not supported), and BFPT_DWORD15_QER_SR2_BIT1 is also out of
> specification when forcing 16-bit Status writes.
>
> - SNOR_F_HAS_16BIT_SR is only imposing 16bit Status writes, whereas
> reads can still be 8-bit wide.
>
> - The usage of helpers verifying the writes was also spread for IMHO no
> really good reason. Why shouldn't we trust spi operations when it
> comes to Status Registers? We do not read back our page reads, so why
> status registers should be treated with so much care, if it's not
> because we are unsure of what is being done? My proposal includes a
> check when it comes to the QE bit (done once) but we don't need these
> checks otherwise. If the QE bit was written properly, there are high
> chances that the other register accesses will just be fine, no?
>
> Asde from my main quest, I also observed no good reason to ask the
> read/write status register callers to use nor->bouncebuf while the
> low-level helpers could do it themselves (we are talking about one or
> two bytes being copied).
>
> So after these observations, my proposal is the following:
> - Create private low level helpers that just read or write a status
> register. They are flexible, we can give the opcode (which varies
> based on the SFDP QER field) and the length (1 or 2).
> - Create public generic accessors which will be used to read/write sr1
> and/or sr2. This is where all the cleverness shall be. The helpers use
> the available opcodes for a given chip in order to fullfill the
> request.
> - Provide a single generic ->quad_enable() hook which generically does
> all the steps mentioned above (read, modify, write, read back and
> verify).
> - Create a list of opcodes for all 6 possible situations:
> {read, write} {sr1, sr2, sr1 and sr2}. These opcodes are
> filled/cleared based on the QER field. An opcode set to 0 indicates
> the absence of support (there is no 0x00 opcode in SPI NOR).
>
> I tried my best to analyze the current behavior and to mimic it as much
> as possible, but this is a risky cleanup. However, if we go for this, it
> will be *much* easier in the future to handle all kind of chip
> variations. We won't be limited to a couple of flags anymore, but rather
> we'll be able to just disable a read or write capability using a single
> line.
>
> Known deviations:
> - The Atmel manufacturer driver drives non SFDP chips which by default
> were receiving the HAS_16B_WR flag, forcing SR2 writes all the times,
> but it was deliberately making single bytes writes to SR1 for its
> locking operations. The flag is likely wrong for them, so I removed
> it.
> - I am proposing on purpose a single quad_enable helper. It should match
> all the cases, with 1 identified difference which I believe is
> harmless: in the SR2_BIT7 case, the helper would make an extra SR1
> read/write which was not done before. This entry explicitly supports
> reading and writing the two registers. Note: no manufacturer has been
> identified to actually use that entry yet.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> This is a really hard to review patch, it is big, full of changes
> everywhere, but I cannot really split it further. The commit log is
> really important, it tries to explain the steps I went through when
> trying to refactor the whole QE/SR handling for which I received
> feedback from Michael, Tudor and Sashiko.
>
> Ideally we could expect test coverage of each case:
> - BFPT_DWORD15_QER_NONE: Probably not needed
> - BFPT_DWORD15_QER_SR2_BIT1_BUGGY: Expected from Hsin-Yi (flag is being
> renamed _NO_1B_WR)
> - BFPT_DWORD15_QER_SR2_BIT1_NO_RD: Tested with a chip re-enabling RDCR
> in a fixup
> - BFPT_DWORD15_QER_SR1_BIT6: TBD
> - BFPT_DWORD15_QER_SR2_BIT7: TBD
> - BFPT_DWORD15_QER_SR2_BIT1: TBD
> - BFPT_DWORD15_QER_SR2_BIT1_1B: Done.
> There will probably be breakages on older chips. These cannot be
> guessed because they are not properly listed in manufacturer
> fixups (yet). If we want a cleanup/simplification, we will have to cope
> with this risk.
>
> I hope the diff stats will motivate people to have a look and report
> their testing.
>
> I will also eagerly monitor Sashiko's output which will probably be
> very useful to catch niche weird cases where these changes might break.
Honestly, I'm still not sold at the sr1 and sr2 split. But since
spi-nor is know for it's code churn. I could just rework that later
:)
Still I had some questions in the old thread:
I don't get why there should be any endianess problems?
Just the low level read and write would have to figure out how to
read and write the status registers.
> ---
> Documentation/driver-api/mtd/spi-nor.rst | 2 +-
> drivers/mtd/spi-nor/atmel.c | 52 +-
> drivers/mtd/spi-nor/core.c | 784 +++++++++++--------------------
> drivers/mtd/spi-nor/core.h | 57 +--
> drivers/mtd/spi-nor/debugfs.c | 2 -
> drivers/mtd/spi-nor/gigadevice.c | 6 +-
> drivers/mtd/spi-nor/issi.c | 3 +-
> drivers/mtd/spi-nor/macronix.c | 12 +-
> drivers/mtd/spi-nor/micron-st.c | 4 +-
> drivers/mtd/spi-nor/otp.c | 16 +-
> drivers/mtd/spi-nor/sfdp.c | 41 +-
> drivers/mtd/spi-nor/spansion.c | 16 +-
> drivers/mtd/spi-nor/sst.c | 5 +-
> drivers/mtd/spi-nor/swp.c | 58 +--
> drivers/mtd/spi-nor/winbond.c | 4 +-
> include/linux/mtd/spi-nor.h | 4 -
> 16 files changed, 416 insertions(+), 650 deletions(-)
>
> diff --git a/Documentation/driver-api/mtd/spi-nor.rst b/Documentation/driver-api/mtd/spi-nor.rst
> index 747a326fb6c0..5441fa7d4f04 100644
> --- a/Documentation/driver-api/mtd/spi-nor.rst
> +++ b/Documentation/driver-api/mtd/spi-nor.rst
> @@ -118,7 +118,7 @@ section, after the ``---`` marker.
> write size 1
> page size 256
> address nbytes 3
> - flags HAS_LOCK | HAS_16BIT_SR | SOFT_RESET | SWP_IS_VOLATILE
> + flags HAS_LOCK | SOFT_RESET | SWP_IS_VOLATILE
>
> opcodes
> read 0xeb
> diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
> index 82c592f0a1e1..8741c0bda497 100644
> --- a/drivers/mtd/spi-nor/atmel.c
> +++ b/drivers/mtd/spi-nor/atmel.c
> @@ -23,18 +23,28 @@ static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len)
>
> static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
> {
> + /* Write 0x00 to the status register to disable write protection */
> + u8 sr = 0;
> int ret;
>
> /* We only support unlocking the whole flash array */
> if (ofs || len != nor->params->size)
> return -EINVAL;
>
> - /* Write 0x00 to the status register to disable write protection */
> - ret = spi_nor_write_sr_and_check(nor, 0);
> + ret = spi_nor_write_sr1(nor, &sr);
> if (ret)
> - dev_dbg(nor->dev, "unable to clear BP bits, WP# asserted?\n");
> + return ret;
>
> - return ret;
> + ret = spi_nor_read_sr1(nor, &sr);
> + if (ret)
> + return ret;
> +
> + if (sr) {
> + dev_dbg(nor->dev, "unable to clear BP bits, WP# asserted?\n");
> + return -EIO;
> + }
> +
> + return 0;
> }
>
> static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, u64 len)
> @@ -50,6 +60,7 @@ static const struct spi_nor_locking_ops at25fs_nor_locking_ops = {
>
> static int at25fs_nor_late_init(struct spi_nor *nor)
> {
> + nor->params->opcodes.write_sr1 = SPINOR_OP_WRSR;
> nor->params->locking_ops = &at25fs_nor_locking_ops;
>
> return 0;
> @@ -69,6 +80,7 @@ static const struct spi_nor_fixups at25fs_nor_fixups = {
> * Return: 0 on success, -error otherwise.
> */
> static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
> +
> u64 len, bool is_protect)
> {
> int ret;
> @@ -78,19 +90,24 @@ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
> if (ofs || len != nor->params->size)
> return -EINVAL;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1(nor, &sr);
> if (ret)
> return ret;
>
> - sr = nor->bouncebuf[0];
> -
> /* SRWD bit needs to be cleared, otherwise the protection doesn't change */
> if (sr & SR_SRWD) {
> sr &= ~SR_SRWD;
> - ret = spi_nor_write_sr_and_check(nor, sr);
> - if (ret) {
> - dev_dbg(nor->dev, "unable to clear SRWD bit, WP# asserted?\n");
> + ret = spi_nor_write_sr1(nor, &sr);
> + if (ret)
> return ret;
> +
> + ret = spi_nor_read_sr1(nor, &sr);
> + if (ret)
> + return ret;
> +
> + if (sr & SR_SRWD) {
> + dev_dbg(nor->dev, "unable to clear SRWD bit, WP# asserted?\n");
> + return -EIO;
> }
> }
>
> @@ -108,14 +125,7 @@ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
> sr &= ~ATMEL_SR_GLOBAL_PROTECT_MASK;
> }
>
> - nor->bouncebuf[0] = sr;
> -
> - /*
> - * We cannot use the spi_nor_write_sr_and_check() because this command
> - * isn't really setting any bits, instead it is an pseudo command for
> - * "Global Unprotect" or "Global Protect"
> - */
> - return spi_nor_write_sr(nor, nor->bouncebuf, 1);
> + return spi_nor_write_sr1(nor, &sr);
> }
>
> static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs, u64 len)
> @@ -131,16 +141,17 @@ static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs, u64 len)
> static int atmel_nor_is_global_protected(struct spi_nor *nor, loff_t ofs,
> u64 len)
> {
> + u8 sr;
> int ret;
>
> if (ofs >= nor->params->size || (ofs + len) > nor->params->size)
> return -EINVAL;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1(nor, &sr);
> if (ret)
> return ret;
>
> - return ((nor->bouncebuf[0] & ATMEL_SR_GLOBAL_PROTECT_MASK) == ATMEL_SR_GLOBAL_PROTECT_MASK);
> + return ((sr & ATMEL_SR_GLOBAL_PROTECT_MASK) == ATMEL_SR_GLOBAL_PROTECT_MASK);
> }
>
> static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = {
> @@ -151,6 +162,7 @@ static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = {
>
> static int atmel_nor_global_protection_late_init(struct spi_nor *nor)
> {
> + nor->params->opcodes.write_sr1 = SPINOR_OP_WRSR;
> nor->params->locking_ops = &atmel_nor_global_protection_ops;
>
> return 0;
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index 29b8fe3d1c65..ac7812562047 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -443,75 +443,6 @@ int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
> return ret;
> }
>
> -/**
> - * spi_nor_read_sr() - Read the Status Register.
> - * @nor: pointer to 'struct spi_nor'.
> - * @sr: pointer to a DMA-able buffer where the value of the
> - * Status Register will be written. Should be at least 2 bytes.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
> -{
> - int ret;
> -
> - if (nor->spimem) {
> - struct spi_mem_op op = SPI_NOR_RDSR_OP(sr);
> -
> - if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
> - op.addr.nbytes = nor->params->rdsr_addr_nbytes;
> - op.dummy.nbytes = nor->params->rdsr_dummy;
> - /*
> - * We don't want to read only one byte in DTR mode. So,
> - * read 2 and then discard the second byte.
> - */
> - op.data.nbytes = 2;
> - }
> -
> - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
> -
> - ret = spi_mem_exec_op(nor->spimem, &op);
> - } else {
> - ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,
> - 1);
> - }
> -
> - if (ret)
> - dev_dbg(nor->dev, "error %d reading SR\n", ret);
> -
> - return ret;
> -}
> -
> -/**
> - * spi_nor_read_cr() - Read the Configuration Register using the
> - * SPINOR_OP_RDCR (35h) command.
> - * @nor: pointer to 'struct spi_nor'
> - * @cr: pointer to a DMA-able buffer where the value of the
> - * Configuration Register will be written.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
> -{
> - int ret;
> -
> - if (nor->spimem) {
> - struct spi_mem_op op = SPI_NOR_RDCR_OP(cr);
> -
> - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
> -
> - ret = spi_mem_exec_op(nor->spimem, &op);
> - } else {
> - ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr,
> - 1);
> - }
> -
> - if (ret)
> - dev_dbg(nor->dev, "error %d reading CR\n", ret);
> -
> - return ret;
> -}
> -
> /**
> * spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode
> * using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by
> @@ -617,12 +548,13 @@ int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable)
> int spi_nor_sr_ready(struct spi_nor *nor)
> {
> int ret;
> + u8 sr;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1(nor, &sr);
> if (ret)
> return ret;
>
> - return !(nor->bouncebuf[0] & SR_WIP);
> + return !(sr & SR_WIP);
> }
>
> /**
> @@ -784,345 +716,297 @@ int spi_nor_global_block_unlock(struct spi_nor *nor)
> }
>
> /**
> - * spi_nor_write_sr() - Write the Status Register.
> + * spi_nor_read_sr_ll() - Low-level Status Registers read.
> * @nor: pointer to 'struct spi_nor'.
> - * @sr: pointer to DMA-able buffer to write to the Status Register.
> - * @len: number of bytes to write to the Status Register.
> + * @opcode: opcode for the status register read operation.
> + * @sr: pointer to buffer for storing the content of the status registers.
> + * @len: number of status registers to read (1 or 2).
> *
> * Return: 0 on success, -errno otherwise.
> */
> -int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
> +static int spi_nor_read_sr_ll(struct spi_nor *nor, u8 opcode, u8 *sr,
> + unsigned int len)
> {
> - int ret;
> + int ret, i;
>
> - ret = spi_nor_write_enable(nor);
> - if (ret)
> - return ret;
> + if (len > 2)
> + return -EINVAL;
> +
> + for (i = 0; i < len; i++)
> + nor->bouncebuf[i] = 0;
>
> if (nor->spimem) {
> - struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len);
> + struct spi_mem_op op = SPI_NOR_RDSR_OP(opcode, nor->bouncebuf, len);
> +
> + if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
> + op.addr.nbytes = nor->params->rdsr_addr_nbytes;
> + op.dummy.nbytes = nor->params->rdsr_dummy;
> + /*
> + * We don't want to read only one byte in DTR mode. So,
> + * read 2 and then discard the second byte.
> + */
> + op.data.nbytes = 2;
> + }
>
> spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
>
> ret = spi_mem_exec_op(nor->spimem, &op);
> } else {
> - ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr,
> - len);
> + ret = spi_nor_controller_ops_read_reg(nor, opcode, nor->bouncebuf, len);
> }
>
> - if (ret) {
> - dev_dbg(nor->dev, "error %d writing SR\n", ret);
> - return ret;
> - }
> -
> - return spi_nor_wait_till_ready(nor);
> -}
> -
> -/**
> - * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
> - * ensure that the byte written match the received value.
> - * @nor: pointer to a 'struct spi_nor'.
> - * @sr1: byte value to be written to the Status Register.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
> -{
> - int ret;
> -
> - nor->bouncebuf[0] = sr1;
> -
> - ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
> - if (ret)
> - return ret;
> -
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> - if (ret)
> - return ret;
> -
> - if (nor->bouncebuf[0] != sr1) {
> - dev_dbg(nor->dev, "SR1: read back test failed\n");
> - return -EIO;
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
> - * Status Register 2 in one shot. Ensure that the byte written in the Status
> - * Register 1 match the received value, and that the 16-bit Write did not
> - * affect what was already in the Status Register 2.
> - * @nor: pointer to a 'struct spi_nor'.
> - * @sr1: byte value to be written to the Status Register 1.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
> -{
> - int ret;
> - u8 *sr_cr = nor->bouncebuf;
> - u8 cr_written;
> -
> - /* Make sure we don't overwrite the contents of Status Register 2. */
> - if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> - ret = spi_nor_read_cr(nor, &sr_cr[1]);
> - if (ret)
> - return ret;
> - } else if ((spi_nor_get_protocol_width(nor->read_proto) == 4 ||
> - spi_nor_get_protocol_width(nor->write_proto) == 4) &&
> - nor->params->quad_enable) {
> - /*
> - * If the Status Register 2 Read command (35h) is not
> - * supported, we should at least be sure we don't
> - * change the value of the SR2 Quad Enable bit.
> - *
> - * When the Quad Enable method is set and the buswidth is 4, we
> - * can safely assume that the value of the QE bit is one, as a
> - * consequence of the nor->params->quad_enable() call.
> - *
> - * According to the JESD216 revB standard, BFPT DWORDS[15],
> - * bits 22:20, the 16-bit Write Status (01h) command is
> - * available just for the cases in which the QE bit is
> - * described in SR2 at BIT(1).
> - */
> - sr_cr[1] = SR2_QUAD_EN_BIT1;
> - } else {
> - sr_cr[1] = 0;
> - }
> -
> - sr_cr[0] = sr1;
> -
> - ret = spi_nor_write_sr(nor, sr_cr, 2);
> - if (ret)
> - return ret;
> -
> - ret = spi_nor_read_sr(nor, sr_cr);
> - if (ret)
> - return ret;
> -
> - if (sr1 != sr_cr[0]) {
> - dev_dbg(nor->dev, "SR: Read back test failed\n");
> - return -EIO;
> - }
> -
> - if (nor->flags & SNOR_F_NO_READ_CR)
> - return 0;
> -
> - cr_written = sr_cr[1];
> -
> - ret = spi_nor_read_cr(nor, &sr_cr[1]);
> - if (ret)
> - return ret;
> -
> - if (cr_written != sr_cr[1]) {
> - dev_dbg(nor->dev, "CR: read back test failed\n");
> - return -EIO;
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
> - * Configuration Register in one shot. Ensure that the byte written in the
> - * Configuration Register match the received value, and that the 16-bit Write
> - * did not affect what was already in the Status Register 1.
> - * @nor: pointer to a 'struct spi_nor'.
> - * @cr: byte value to be written to the Configuration Register.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
> -{
> - int ret;
> - u8 *sr_cr = nor->bouncebuf;
> - u8 sr_written;
> -
> - /* Keep the current value of the Status Register 1. */
> - ret = spi_nor_read_sr(nor, sr_cr);
> - if (ret)
> - return ret;
> -
> - sr_cr[1] = cr;
> -
> - ret = spi_nor_write_sr(nor, sr_cr, 2);
> - if (ret)
> - return ret;
> -
> - sr_written = sr_cr[0];
> -
> - ret = spi_nor_read_sr(nor, sr_cr);
> - if (ret)
> - return ret;
> -
> - if (sr_written != sr_cr[0]) {
> - dev_dbg(nor->dev, "SR: Read back test failed\n");
> - return -EIO;
> - }
> -
> - if (nor->flags & SNOR_F_NO_READ_CR)
> - return 0;
> -
> - ret = spi_nor_read_cr(nor, &sr_cr[1]);
> - if (ret)
> - return ret;
> -
> - if (cr != sr_cr[1]) {
> - dev_dbg(nor->dev, "CR: read back test failed\n");
> - return -EIO;
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * spi_nor_write_16bit_sr_cr_and_check() - Write the Status Register 1 and the
> - * Configuration Register in one shot. Ensure that the bytes written in both
> - * registers match the received value.
> - * @nor: pointer to a 'struct spi_nor'.
> - * @regs: two-byte array with values to be written to the status and
> - * configuration registers.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spi_nor_write_16bit_sr_cr_and_check(struct spi_nor *nor, const u8 *regs)
> -{
> - u8 written_regs[2];
> - int ret;
> -
> - written_regs[0] = regs[0];
> - written_regs[1] = regs[1];
> - nor->bouncebuf[0] = regs[0];
> - nor->bouncebuf[1] = regs[1];
> -
> - ret = spi_nor_write_sr(nor, nor->bouncebuf, 2);
> - if (ret)
> - return ret;
> -
> - ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
> - if (ret)
> - return ret;
> -
> - if (written_regs[0] != nor->bouncebuf[0]) {
> - dev_dbg(nor->dev, "SR: Read back test failed\n");
> - return -EIO;
> - }
> -
> - if (nor->flags & SNOR_F_NO_READ_CR)
> - return 0;
> -
> - ret = spi_nor_read_cr(nor, &nor->bouncebuf[1]);
> - if (ret)
> - return ret;
> -
> - if (written_regs[1] != nor->bouncebuf[1]) {
> - dev_dbg(nor->dev, "CR: read back test failed\n");
> - return -EIO;
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
> - * the byte written match the received value without affecting other bits in the
> - * Status Register 1 and 2.
> - * @nor: pointer to a 'struct spi_nor'.
> - * @sr1: byte value to be written to the Status Register.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
> -{
> - if (nor->flags & SNOR_F_HAS_16BIT_SR)
> - return spi_nor_write_16bit_sr_and_check(nor, sr1);
> -
> - return spi_nor_write_sr1_and_check(nor, sr1);
> -}
> -
> -/**
> - * spi_nor_write_sr_cr_and_check() - Write the Status Register 1 and ensure that
> - * the byte written match the received value. Same for the Control Register if
> - * available.
> - * @nor: pointer to a 'struct spi_nor'.
> - * @regs: byte array to be written to the registers.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs)
> -{
> - if (nor->flags & SNOR_F_HAS_16BIT_SR)
> - return spi_nor_write_16bit_sr_cr_and_check(nor, regs);
> -
> - return spi_nor_write_sr1_and_check(nor, regs[0]);
> -}
> -
> -/**
> - * spi_nor_write_sr2() - Write the Status Register 2 using the
> - * SPINOR_OP_WRSR2 (3eh) command.
> - * @nor: pointer to 'struct spi_nor'.
> - * @sr2: pointer to DMA-able buffer to write to the Status Register 2.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
> -{
> - int ret;
> -
> - ret = spi_nor_write_enable(nor);
> - if (ret)
> - return ret;
> -
> - if (nor->spimem) {
> - struct spi_mem_op op = SPI_NOR_WRSR2_OP(sr2);
> -
> - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
> -
> - ret = spi_mem_exec_op(nor->spimem, &op);
> - } else {
> - ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2,
> - sr2, 1);
> - }
> -
> - if (ret) {
> - dev_dbg(nor->dev, "error %d writing SR2\n", ret);
> - return ret;
> - }
> -
> - return spi_nor_wait_till_ready(nor);
> -}
> -
> -/**
> - * spi_nor_read_sr2() - Read the Status Register 2 using the
> - * SPINOR_OP_RDSR2 (3fh) command.
> - * @nor: pointer to 'struct spi_nor'.
> - * @sr2: pointer to DMA-able buffer where the value of the
> - * Status Register 2 will be written.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
> -{
> - int ret;
> -
> - if (nor->spimem) {
> - struct spi_mem_op op = SPI_NOR_RDSR2_OP(sr2);
> -
> - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
> -
> - ret = spi_mem_exec_op(nor->spimem, &op);
> - } else {
> - ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2,
> - 1);
> - }
> + memcpy(sr, nor->bouncebuf, len);
>
> if (ret)
> - dev_dbg(nor->dev, "error %d reading SR2\n", ret);
> + dev_dbg(nor->dev, "Error %d reading Status Registers\n", ret);
>
> return ret;
> }
>
> +/**
> + * spi_nor_write_sr_ll() - Low-level Status Registers write.
> + * @nor: pointer to 'struct spi_nor'.
> + * @opcode: opcode for the status register write operation.
> + * @sr: pointer to status registers buffer to write.
> + * @len: number of status registers to write.
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +static int spi_nor_write_sr_ll(struct spi_nor *nor, u8 opcode, const u8 *sr,
> + unsigned int len)
> +{
> + int ret, i;
> +
> + if (len > 2)
> + return -EINVAL;
> +
> + ret = spi_nor_write_enable(nor);
> + if (ret)
> + return ret;
> +
> + for (i = 0; i < len; i++)
> + nor->bouncebuf[i] = sr[i];
> +
> + if (nor->spimem) {
> + struct spi_mem_op op = SPI_NOR_WRSR_OP(opcode,
> + nor->bouncebuf, len);
> +
> + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
> +
> + ret = spi_mem_exec_op(nor->spimem, &op);
> + } else {
> + ret = spi_nor_controller_ops_write_reg(nor, opcode,
> + nor->bouncebuf, len);
> + }
> +
> + if (ret) {
> + dev_dbg(nor->dev, "Error %d writing Status Registers\n", ret);
> + return ret;
> + }
> +
> + return spi_nor_wait_till_ready(nor);
> +}
> +
> +/**
> + * spi_nor_read_sr1() - Read SR1 only
> + * Useful for:
> + * - The core to offer a generic "read SR1 and SR2" capability
> + * - Manufacturer drivers (since they know the chip SR layout)
> + * - Polling the BUSY bit in the core
> + *
> + * @nor: the spi_nor structure
> + * @sr1: pointer to a valid SR1 buffer
> + *
> + * Return 0 or errno.
> + */
> +int spi_nor_read_sr1(struct spi_nor *nor, u8 *sr1)
> +{
> + return spi_nor_read_sr_ll(nor, nor->params->opcodes.read_sr1, sr1, 1);
> +}
> +
> +/**
> + * spi_nor_read_sr2() - Read SR2 only
> + * Useful for:
> + * - The core to offer a generic "read SR1 and SR2" capability
> + * - Manufacturer drivers (since they know the chip SR layout)
> + * - SR2 based OTP configuration
> + *
> + * @nor: the spi_nor structure
> + * @sr2: pointer to a valid SR2 buffer
> + *
> + * Return 0 or errno.
> + */
> +int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
> +{
> + struct spi_nor_flash_parameter *params = nor->params;
> + int ret;
> +
> + if (params->opcodes.read_sr2) {
> + ret = spi_nor_read_sr_ll(nor, params->opcodes.read_sr2, sr2, 1);
> + if (ret)
> + return ret;
> + } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
> + spi_nor_get_protocol_width(nor->write_proto) == 4) {
> + /* Make sure the QE bit is persistently kept */
> + *sr2 = params->qe_mask[1];
Mh. So before there was at least a check if a quad_enable cb is set.
Is this now implicit? because qe_mask[1] is zero if there is no
quad_enable? That should at *least* get some comment.
I tried to actually get the original use case, but all I've found
is Tudors commit 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit
on lock()/unlock()"). There wasn't much of a discussion on the ML,
and I couldn't find where Boris was suggesting it.
So before we cannot get rid of it anymore, we should just handle it
in the one caller which actually uses it: spi_nor_sr_{un,}lock().
I've checked the current spi_nor_write_sr_and_check() and the only
actual user is the swp.c. atmel.c is doing global write protection
on/off, which IIRC only uses SR1.
So let's move that weird handling there. Then chances are, we can
get rid of it as we know what flashes do locking because that is not
discoverable at runtime. It's just tedious work to check all the
datasheets. But as soon as we now put that into a more generic path,
we can't do anything about it anymore.
> + } else {
> + *sr2 = 0;
I'd expect an -EINVAL or -EIO here.
-michael
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * spi_nor_read_sr1_and_sr2() - Read SR1 then SR2
> + * General purpose helper, always safe to call.
> + *
> + * @nor: the spi_nor structure
> + * @sr: pointer to a valid 2-byte array
> + *
> + * Return 0 or errno.
> + */
> +int spi_nor_read_sr1_and_sr2(struct spi_nor *nor, u8 *sr)
> +{
> + int ret;
> +
> + ret = spi_nor_read_sr1(nor, &sr[0]);
> + if (ret)
> + return ret;
> +
> + return spi_nor_read_sr2(nor, &sr[1]);
> +}
> +
> +/**
> + * spi_nor_write_sr1() - Write SR1 only
> + * Useful for:
> + * - Manufacturer drivers (since they know the chip SR layout)
> + *
> + * @nor: the spi_nor structure
> + * @sr1: pointer to a valid SR1 buffer
> + *
> + * Return 0 or errno.
> + */
> +int spi_nor_write_sr1(struct spi_nor *nor, const u8 *sr1)
> +{
> + if (WARN_ONCE(!nor->params->opcodes.write_sr1,
> + "Restricted helper use, write SR1 not supported"))
> + return -EIO;
> +
> + return spi_nor_write_sr_ll(nor, nor->params->opcodes.write_sr1, sr1, 1);
> +}
> +
> +/**
> + * spi_nor_write_sr2() - Write SR2 only
> + * Useful for:
> + * - Manufacturer drivers (since they know the chip SR layout)
> + * - SR2 based OTP configuration
> + *
> + * @nor: the spi_nor structure
> + * @sr2: pointer to a valid SR2 buffer
> + *
> + * Return 0 or errno.
> + */
> +int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
> +{
> + if (WARN_ONCE(!nor->params->opcodes.write_sr2,
> + "Restricted helper use, write SR2 not supported"))
> + return -EIO;
> +
> + return spi_nor_write_sr_ll(nor, nor->params->opcodes.write_sr2, sr2, 1);
> +}
> +
> +/**
> + * spi_nor_write_sr1_and_sr2() - Write SR1 then SR2
> + * General purpose helper, always safe to call. Will expectedly ignore
> + * SR2 on certain chips.
> + *
> + * @nor: the spi_nor structure
> + * @sr: pointer to a valid 2-byte array
> + *
> + * Return 0 or errno.
> + */
> +static int spi_nor_write_sr1_and_sr2(struct spi_nor *nor, const u8 *sr)
> +{
> + struct spi_nor_flash_parameter *params = nor->params;
> + int ret;
> +
> + if (params->opcodes.write_sr1_and_sr2)
> + return spi_nor_write_sr_ll(nor,
> + params->opcodes.write_sr1_and_sr2,
> + sr, 2);
> +
> + ret = spi_nor_write_sr1(nor, &sr[0]);
> + if (ret)
> + return ret;
> +
> + if (params->opcodes.write_sr2)
> + return spi_nor_write_sr2(nor, &sr[1]);
> +
> + return 0;
> +}
> +
> +/**
> + * spi_nor_write_sr1_and_sr2_and_check() - Write SR1 then SR2, then read
> + * them back and verifies
> + * General purpose helper, always safe to call. Will expectedly ignore
> + * SR2 on certain chips.
> + *
> + * @nor: the spi_nor structure
> + * @sr: pointer to a valid 2-byte array
> + *
> + * Return 0 or errno.
> + */
> +int spi_nor_write_sr1_and_sr2_and_check(struct spi_nor *nor, const u8 *sr)
> +{
> + u8 tmp[2];
> + int ret;
> +
> + ret = spi_nor_write_sr1_and_sr2(nor, sr);
> + if (ret)
> + return ret;
> +
> + ret = spi_nor_read_sr1_and_sr2(nor, tmp);
> + if (ret)
> + return ret;
> +
> + if (sr[0] != tmp[0] || sr[1] != tmp[1])
> + return -EIO;
> +
> + return 0;
> +}
> +
> +/**
> + * spi_nor_generic_quad_enable() - Read the status registers,
> + * apply the QE bit mask,
> + * write the status registers,
> + * read them back and check the content.
> + *
> + * @nor: pointer to 'struct spi_nor'
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +static int spi_nor_generic_quad_enable(struct spi_nor *nor)
> +{
> + u8 *qe_mask = nor->params->qe_mask;
> + u8 sr[2] = {};
> + int ret;
> +
> + if (!qe_mask[0] && !qe_mask[1])
> + return 0;
> +
> + ret = spi_nor_read_sr1_and_sr2(nor, sr);
> + if (ret)
> + return ret;
> +
> + if (sr[0] & qe_mask[0] || sr[1] & qe_mask[1])
> + return 0;
> +
> + sr[0] |= qe_mask[0];
> + sr[1] |= qe_mask[1];
> +
> + return spi_nor_write_sr1_and_sr2_and_check(nor, sr);
> +}
> +
> /**
> * spi_nor_erase_die() - Erase the entire die.
> * @nor: pointer to 'struct spi_nor'.
> @@ -1904,106 +1788,6 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
> return ret;
> }
>
> -/**
> - * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
> - * Register 1.
> - * @nor: pointer to a 'struct spi_nor'
> - *
> - * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
> -{
> - int ret;
> -
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> - if (ret)
> - return ret;
> -
> - if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
> - return 0;
> -
> - nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
> -
> - return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
> -}
> -
> -/**
> - * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
> - * Register 2.
> - * @nor: pointer to a 'struct spi_nor'.
> - *
> - * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
> -{
> - int ret;
> -
> - if (nor->flags & SNOR_F_NO_READ_CR)
> - return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
> -
> - ret = spi_nor_read_cr(nor, nor->bouncebuf);
> - if (ret)
> - return ret;
> -
> - if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
> - return 0;
> -
> - nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
> -
> - return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
> -}
> -
> -/**
> - * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
> - * @nor: pointer to a 'struct spi_nor'
> - *
> - * Set the Quad Enable (QE) bit in the Status Register 2.
> - *
> - * This is one of the procedures to set the QE bit described in the SFDP
> - * (JESD216 rev B) specification but no manufacturer using this procedure has
> - * been identified yet, hence the name of the function.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
> -{
> - u8 *sr2 = nor->bouncebuf;
> - int ret;
> - u8 sr2_written;
> -
> - /* Check current Quad Enable bit value. */
> - ret = spi_nor_read_sr2(nor, sr2);
> - if (ret)
> - return ret;
> - if (*sr2 & SR2_QUAD_EN_BIT7)
> - return 0;
> -
> - /* Update the Quad Enable bit. */
> - *sr2 |= SR2_QUAD_EN_BIT7;
> -
> - ret = spi_nor_write_sr2(nor, sr2);
> - if (ret)
> - return ret;
> -
> - sr2_written = *sr2;
> -
> - /* Read back and check it. */
> - ret = spi_nor_read_sr2(nor, sr2);
> - if (ret)
> - return ret;
> -
> - if (*sr2 != sr2_written) {
> - dev_dbg(nor->dev, "SR2: Read back test failed\n");
> - return -EIO;
> - }
> -
> - return 0;
> -}
> -
> static const struct spi_nor_manufacturer *manufacturers[] = {
> &spi_nor_atmel,
> &spi_nor_eon,
> @@ -2494,6 +2278,7 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
> {
> struct spi_nor_flash_parameter *params = nor->params;
> unsigned int cap;
> + u8 opcode;
>
> /* X-X-X modes are not supported yet, mask them all. */
> *hwcaps &= ~SNOR_HWCAPS_X_X_X;
> @@ -2525,14 +2310,14 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
> *hwcaps &= ~BIT(cap);
> }
>
> - /* Some SPI controllers might not support CR read opcode. */
> - if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> - struct spi_mem_op op = SPI_NOR_RDCR_OP(nor->bouncebuf);
> -
> + /* Some SPI controllers might not support reading SR2 */
> + opcode = nor->params->opcodes.read_sr2;
> + if (opcode) {
> + struct spi_mem_op op = SPI_NOR_RDSR_OP(opcode, nor->bouncebuf, 1);
> spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
>
> if (!spi_mem_supports_op(nor->spimem, &op))
> - nor->flags |= SNOR_F_NO_READ_CR;
> + nor->params->opcodes.read_sr2 = 0;
> }
> }
>
> @@ -3107,11 +2892,14 @@ static void spi_nor_init_default_params(struct spi_nor *nor)
> const struct flash_info *info = nor->info;
> struct device_node *np = spi_nor_get_flash_node(nor);
>
> - params->quad_enable = spi_nor_sr2_bit1_quad_enable;
> - params->otp.org = info->otp;
> + /* Default to 16-bit Read/Write Status commands */
> + params->opcodes.read_sr1 = SPINOR_OP_RDSR;
> + params->opcodes.read_sr2 = SPINOR_OP_RDCR;
> + params->opcodes.write_sr1_and_sr2 = SPINOR_OP_WRSR;
> + params->quad_enable = spi_nor_generic_quad_enable;
> + params->qe_mask[1] = BIT(1);
>
> - /* Default to 16-bit Write Status (01h) Command */
> - nor->flags |= SNOR_F_HAS_16BIT_SR;
> + params->otp.org = info->otp;
>
> /* Set SPI NOR sizes. */
> params->writesize = 1;
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 2cc0c80da3fa..7d43d3ba47ee 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -37,36 +37,18 @@
> SPI_MEM_OP_NO_DUMMY, \
> SPI_MEM_OP_NO_DATA)
>
> -#define SPI_NOR_RDSR_OP(buf) \
> - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), \
> +#define SPI_NOR_RDSR_OP(opcode, buf, len) \
> + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
> SPI_MEM_OP_NO_ADDR, \
> SPI_MEM_OP_NO_DUMMY, \
> - SPI_MEM_OP_DATA_IN(1, buf, 0))
> + SPI_MEM_OP_DATA_IN(len, buf, 0))
>
> -#define SPI_NOR_WRSR_OP(buf, len) \
> - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), \
> +#define SPI_NOR_WRSR_OP(opcode, buf, len) \
> + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
> SPI_MEM_OP_NO_ADDR, \
> SPI_MEM_OP_NO_DUMMY, \
> SPI_MEM_OP_DATA_OUT(len, buf, 0))
>
> -#define SPI_NOR_RDSR2_OP(buf) \
> - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), \
> - SPI_MEM_OP_NO_ADDR, \
> - SPI_MEM_OP_NO_DUMMY, \
> - SPI_MEM_OP_DATA_OUT(1, buf, 0))
> -
> -#define SPI_NOR_WRSR2_OP(buf) \
> - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), \
> - SPI_MEM_OP_NO_ADDR, \
> - SPI_MEM_OP_NO_DUMMY, \
> - SPI_MEM_OP_DATA_OUT(1, buf, 0))
> -
> -#define SPI_NOR_RDCR_OP(buf) \
> - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), \
> - SPI_MEM_OP_NO_ADDR, \
> - SPI_MEM_OP_NO_DUMMY, \
> - SPI_MEM_OP_DATA_IN(1, buf, 0))
> -
> #define SPI_NOR_EN4B_EX4B_OP(enable) \
> SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B, 0), \
> SPI_MEM_OP_NO_ADDR, \
> @@ -129,8 +111,6 @@ enum spi_nor_option_flags {
> SNOR_F_4B_OPCODES = BIT(3),
> SNOR_F_HAS_4BAIT = BIT(4),
> SNOR_F_HAS_LOCK = BIT(5),
> - SNOR_F_HAS_16BIT_SR = BIT(6),
> - SNOR_F_NO_READ_CR = BIT(7),
> SNOR_F_HAS_SR_TB_BIT6 = BIT(8),
> SNOR_F_HAS_4BIT_BP = BIT(9),
> SNOR_F_HAS_SR_BP3_BIT6 = BIT(10),
> @@ -345,9 +325,19 @@ struct spi_nor_otp {
> * List of variable opcodes used by the chip.
> *
> * @die_erase: opcode for erasing a die, defaults to SPINOR_OP_CHIP_ERASE
> + * @read_sr1: opcode for reading SR1 alone
> + * @read_sr2: opcode for reading SR2 alone
> + * @write_sr1: opcode for writing SR1 alone
> + * @write_sr2: opcode for writing SR2 alone
> + * @write_sr1_and_sr2: opcode for writing SR1 then SR2 in one operation
> */
> struct spi_nor_opcodes {
> u8 die_erase;
> + u8 read_sr1;
> + u8 read_sr2;
> + u8 write_sr1;
> + u8 write_sr2;
> + u8 write_sr1_and_sr2;
> };
>
> /**
> @@ -384,6 +374,7 @@ struct spi_nor_opcodes {
> * @otp: SPI NOR OTP info.
> * @set_octal_dtr: enables or disables SPI NOR octal DTR mode.
> * @quad_enable: enables SPI NOR quad mode.
> + * @qe_mask: two bytes mask used to set/clear the QE bit
> * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
> * @ready: (optional) flashes might use a different mechanism
> * than reading the status register to indicate they
> @@ -413,6 +404,7 @@ struct spi_nor_flash_parameter {
>
> int (*set_octal_dtr)(struct spi_nor *nor, bool enable);
> int (*quad_enable)(struct spi_nor *nor);
> + u8 qe_mask[2];
> int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
> int (*ready)(struct spi_nor *nor);
>
> @@ -641,18 +633,15 @@ int spi_nor_wait_till_ready(struct spi_nor *nor);
> int spi_nor_global_block_unlock(struct spi_nor *nor);
> int spi_nor_prep_and_lock(struct spi_nor *nor);
> void spi_nor_unlock_and_unprep(struct spi_nor *nor);
> -int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
> -int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
> -int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
> int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
> enum spi_nor_protocol reg_proto);
> -int spi_nor_read_sr(struct spi_nor *nor, u8 *sr);
> int spi_nor_sr_ready(struct spi_nor *nor);
> -int spi_nor_read_cr(struct spi_nor *nor, u8 *cr);
> -int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len);
> -int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1);
> -int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr);
> -int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs);
> +int spi_nor_read_sr1(struct spi_nor *nor, u8 *sr1);
> +int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2);
> +int spi_nor_read_sr1_and_sr2(struct spi_nor *nor, u8 *sr);
> +int spi_nor_write_sr1(struct spi_nor *nor, const u8 *sr1);
> +int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2);
> +int spi_nor_write_sr1_and_sr2_and_check(struct spi_nor *nor, const u8 *sr);
>
> ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
> u8 *buf);
> diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
> index ef6f0ffcd6bb..512825c3fc85 100644
> --- a/drivers/mtd/spi-nor/debugfs.c
> +++ b/drivers/mtd/spi-nor/debugfs.c
> @@ -19,8 +19,6 @@ static const char *const snor_f_names[] = {
> SNOR_F_NAME(4B_OPCODES),
> SNOR_F_NAME(HAS_4BAIT),
> SNOR_F_NAME(HAS_LOCK),
> - SNOR_F_NAME(HAS_16BIT_SR),
> - SNOR_F_NAME(NO_READ_CR),
> SNOR_F_NAME(HAS_SR_TB_BIT6),
> SNOR_F_NAME(HAS_4BIT_BP),
> SNOR_F_NAME(HAS_SR_BP3_BIT6),
> diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
> index ef1edd0add70..4070a692e968 100644
> --- a/drivers/mtd/spi-nor/gigadevice.c
> +++ b/drivers/mtd/spi-nor/gigadevice.c
> @@ -23,8 +23,10 @@ gd25q256_post_bfpt(struct spi_nor *nor,
> * GD25Q256E | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR
> */
> if (bfpt_header->major == SFDP_JESD216_MAJOR &&
> - bfpt_header->minor == SFDP_JESD216_MINOR)
> - nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> + bfpt_header->minor == SFDP_JESD216_MINOR) {
> + nor->params->qe_mask[0] = BIT(6);
> + nor->params->qe_mask[1] = 0;
> + }
>
> return 0;
> }
> diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
> index 18d9a00aa22e..04db42b5141e 100644
> --- a/drivers/mtd/spi-nor/issi.c
> +++ b/drivers/mtd/spi-nor/issi.c
> @@ -131,7 +131,8 @@ static const struct flash_info issi_nor_parts[] = {
>
> static void issi_nor_default_init(struct spi_nor *nor)
> {
> - nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> + nor->params->qe_mask[0] = BIT(6);
> + nor->params->qe_mask[1] = 0;
> }
>
> static const struct spi_nor_fixups issi_fixups = {
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index e97f5cbd9aad..55612237c1ef 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -65,11 +65,12 @@ mx25l3255e_late_init_fixups(struct spi_nor *nor)
>
> /*
> * SFDP of MX25L3255E is JESD216, which does not include the Quad
> - * Enable bit Requirement in BFPT. As a result, during BFPT parsing,
> - * the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.
> - * Therefore, it is necessary to correct this setting by late_init.
> + * Enable bit Requirement in BFPT. As a result, during BFPT parsing
> + * the quad_enable mask is reset. Therefore, it is necessary to
> + * correct this setting by late_init.
> */
> - params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> + params->qe_mask[0] = BIT(6);
> + params->qe_mask[1] = 0;
>
> /*
> * In addition, MX25L3255E also supports 1-4-4 page program in 3-byte
> @@ -314,7 +315,8 @@ static int macronix_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
>
> static void macronix_nor_default_init(struct spi_nor *nor)
> {
> - nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> + nor->params->qe_mask[0] = BIT(6);
> + nor->params->qe_mask[1] = 0;
> }
>
> static int macronix_nor_late_init(struct spi_nor *nor)
> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
> index 031cf887318c..344539d2a36a 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -229,7 +229,7 @@ static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor,
> const struct sfdp_parameter_header *bfpt_header,
> const struct sfdp_bfpt *bfpt)
> {
> - nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> + nor->params->opcodes.write_sr1 = 0;
> return 0;
> }
>
> @@ -633,7 +633,7 @@ static int micron_st_nor_ready(struct spi_nor *nor)
> static void micron_st_nor_default_init(struct spi_nor *nor)
> {
> nor->flags |= SNOR_F_HAS_LOCK;
> - nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> + nor->params->opcodes.write_sr1 = 0;
> nor->params->quad_enable = NULL;
> }
>
> diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
> index 7d0b145d78d8..1eeb33a20091 100644
> --- a/drivers/mtd/spi-nor/otp.c
> +++ b/drivers/mtd/spi-nor/otp.c
> @@ -175,24 +175,24 @@ static int spi_nor_otp_lock_bit_cr(unsigned int region)
> */
> int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigned int region)
> {
> - u8 *cr = nor->bouncebuf;
> int ret, lock_bit;
> + u8 sr[2];
>
> lock_bit = spi_nor_otp_lock_bit_cr(region);
> if (lock_bit < 0)
> return lock_bit;
>
> - ret = spi_nor_read_cr(nor, cr);
> + ret = spi_nor_read_sr1_and_sr2(nor, sr);
> if (ret)
> return ret;
>
> /* no need to write the register if region is already locked */
> - if (cr[0] & lock_bit)
> + if (sr[1] & lock_bit)
> return 0;
>
> - cr[0] |= lock_bit;
> + sr[1] |= lock_bit;
>
> - return spi_nor_write_16bit_cr_and_check(nor, cr[0]);
> + return spi_nor_write_sr1_and_sr2_and_check(nor, sr);
> }
>
> /**
> @@ -207,18 +207,18 @@ int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigned int region)
> */
> int spi_nor_otp_is_locked_sr2(struct spi_nor *nor, unsigned int region)
> {
> - u8 *cr = nor->bouncebuf;
> int ret, lock_bit;
> + u8 sr2;
>
> lock_bit = spi_nor_otp_lock_bit_cr(region);
> if (lock_bit < 0)
> return lock_bit;
>
> - ret = spi_nor_read_cr(nor, cr);
> + ret = spi_nor_read_sr2(nor, &sr2);
> if (ret)
> return ret;
>
> - return cr[0] & lock_bit;
> + return sr2 & lock_bit;
> }
>
> static loff_t spi_nor_otp_region_start(const struct spi_nor *nor, unsigned int region)
> diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
> index 526763c79f55..1d799f02b8e5 100644
> --- a/drivers/mtd/spi-nor/sfdp.c
> +++ b/drivers/mtd/spi-nor/sfdp.c
> @@ -561,10 +561,21 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> val >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
> params->page_size = 1U << val;
>
> + /*
> + * The standard declares various read and write status methods, some of
> + * them will be overloaded based on the QER field.
> + */
> + params->opcodes.read_sr1 = SPINOR_OP_RDSR;
> + params->opcodes.read_sr2 = SPINOR_OP_RDCR;
> + params->opcodes.write_sr1 = SPINOR_OP_WRSR;
> + params->opcodes.write_sr1_and_sr2 = SPINOR_OP_WRSR;
> +
> + params->qe_mask[0] = 0;
> + params->qe_mask[1] = 0;
> +
> /* Quad Enable Requirements. */
> switch (bfpt.dwords[SFDP_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
> case BFPT_DWORD15_QER_NONE:
> - params->quad_enable = NULL;
> break;
>
> case BFPT_DWORD15_QER_SR2_BIT1_NO_1B_WR:
> @@ -572,23 +583,28 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> * Writing only one byte to the Status Register has the
> * side-effect of clearing Status Register 2.
> */
> + fallthrough;
> case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
> /*
> * Read Configuration Register (35h) instruction is not
> - * supported.
> + * supported. 16-bit writes expected.
> */
> - nor->flags |= SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR;
> - params->quad_enable = spi_nor_sr2_bit1_quad_enable;
> + params->opcodes.read_sr2 = 0;
> + params->opcodes.write_sr1 = 0;
> + params->qe_mask[1] = BIT(1);
> break;
>
> case BFPT_DWORD15_QER_SR1_BIT6:
> - nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> - params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> + params->opcodes.read_sr2 = 0;
> + params->opcodes.write_sr1_and_sr2 = 0;
> + params->qe_mask[0] = BIT(6);
> break;
>
> case BFPT_DWORD15_QER_SR2_BIT7:
> - nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> - params->quad_enable = spi_nor_sr2_bit7_quad_enable;
> + params->opcodes.read_sr2 = SPINOR_OP_RDSR2;
> + params->opcodes.write_sr1_and_sr2 = 0;
> + params->opcodes.write_sr2 = SPINOR_OP_WRSR2;
> + params->qe_mask[1] = BIT(7);
> break;
>
> case BFPT_DWORD15_QER_SR2_BIT1:
> @@ -598,9 +614,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> * Register 2, so let's be cautious and keep the default
> * assumption of a 16-bit Write Status (01h) command.
> */
> - nor->flags |= SNOR_F_HAS_16BIT_SR;
> -
> - params->quad_enable = spi_nor_sr2_bit1_quad_enable;
> + params->opcodes.write_sr1 = 0;
> + params->qe_mask[1] = BIT(1);
> break;
>
> default:
> @@ -608,6 +623,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> break;
> }
>
> + /* opcodes sanity check */
> + WARN_ON(!params->opcodes.read_sr1 ||
> + (!params->opcodes.write_sr1 && !params->opcodes.write_sr1_and_sr2));
> +
> dword = bfpt.dwords[SFDP_DWORD(16)] & BFPT_DWORD16_4B_ADDR_MODE_MASK;
> if (SFDP_MASK_CHECK(dword, BFPT_DWORD16_4B_ADDR_MODE_BRWR))
> params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr;
> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
> index 2a8238c707e1..ca2703a5a338 100644
> --- a/drivers/mtd/spi-nor/spansion.c
> +++ b/drivers/mtd/spi-nor/spansion.c
> @@ -399,8 +399,9 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
> nor->bouncebuf);
> bool is3byte, is4byte;
> int ret;
> + u8 sr;
>
> - ret = spi_nor_read_sr(nor, &nor->bouncebuf[1]);
> + ret = spi_nor_read_sr1(nor, &sr);
> if (ret)
> return ret;
>
> @@ -408,7 +409,7 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
> if (ret)
> return ret;
>
> - is3byte = (nor->bouncebuf[0] == nor->bouncebuf[1]);
> + is3byte = (nor->bouncebuf[0] == sr);
>
> op = (struct spi_mem_op)
> CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0,
> @@ -417,7 +418,7 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
> if (ret)
> return ret;
>
> - is4byte = (nor->bouncebuf[0] == nor->bouncebuf[1]);
> + is4byte = (nor->bouncebuf[0] == sr);
>
> if (is3byte == is4byte)
> return -EIO;
> @@ -1103,13 +1104,14 @@ static const struct flash_info spansion_nor_parts[] = {
> static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
> {
> int ret;
> + u8 sr;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1(nor, &sr);
> if (ret)
> return ret;
>
> - if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
> - if (nor->bouncebuf[0] & SR_E_ERR)
> + if (sr & (SR_E_ERR | SR_P_ERR)) {
> + if (sr & SR_E_ERR)
> dev_err(nor->dev, "Erase Error occurred\n");
> else
> dev_err(nor->dev, "Programming Error occurred\n");
> @@ -1129,7 +1131,7 @@ static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
> return -EIO;
> }
>
> - return !(nor->bouncebuf[0] & SR_WIP);
> + return !(sr & SR_WIP);
> }
>
> static int spansion_nor_late_init(struct spi_nor *nor)
> diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
> index db02c14ba16f..77a0bc41d4e5 100644
> --- a/drivers/mtd/spi-nor/sst.c
> +++ b/drivers/mtd/spi-nor/sst.c
> @@ -21,16 +21,17 @@ static int sst26vf_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len)
> static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
> {
> int ret;
> + u8 cr;
>
> /* We only support unlocking the entire flash array. */
> if (ofs != 0 || len != nor->params->size)
> return -EINVAL;
>
> - ret = spi_nor_read_cr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr2(nor, &cr);
> if (ret)
> return ret;
>
> - if (!(nor->bouncebuf[0] & SST26VF_CR_BPNV)) {
> + if (!(cr & SST26VF_CR_BPNV)) {
> dev_dbg(nor->dev, "Any block has been permanently locked\n");
> return -EINVAL;
> }
> diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c
> index 235070b215d1..b7b291e15917 100644
> --- a/drivers/mtd/spi-nor/swp.c
> +++ b/drivers/mtd/spi-nor/swp.c
> @@ -36,7 +36,7 @@ static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor)
>
> static u8 spi_nor_get_sr_cmp_mask(struct spi_nor *nor)
> {
> - if (!(nor->flags & SNOR_F_NO_READ_CR) &&
> + if (nor->params->opcodes.read_sr2 &&
> nor->flags & SNOR_F_HAS_SR2_CMP_BIT6)
> return SR2_CMP_BIT6;
> else
> @@ -207,17 +207,9 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u8 *sr)
>
>
> if (!sr) {
> - if (spi_nor_read_sr(nor, nor->bouncebuf))
> + if (spi_nor_read_sr1_and_sr2(nor, sr_cr))
> return;
>
> - sr_cr[0] = nor->bouncebuf[0];
> -
> - if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> - if (spi_nor_read_cr(nor, nor->bouncebuf))
> - return;
> - }
> -
> - sr_cr[1] = nor->bouncebuf[0];
> sr = sr_cr;
> }
>
> @@ -273,20 +265,10 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)
> int ret;
> u8 pow;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1_and_sr2(nor, status_old);
> if (ret)
> return ret;
>
> - status_old[0] = nor->bouncebuf[0];
> -
> - if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> - ret = spi_nor_read_cr(nor, nor->bouncebuf);
> - if (ret)
> - return ret;
> -
> - status_old[1] = nor->bouncebuf[0];
> - }
> -
> /* If nothing in our range is unlocked, we don't need to do anything */
> if (spi_nor_is_locked_sr(nor, ofs, len, status_old))
> return 0;
> @@ -378,10 +360,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)
> (ofs_old < ofs_new || (ofs_new + len_new) < (ofs_old + len_old)))
> return -EINVAL;
>
> - if (nor->flags & SNOR_F_NO_READ_CR)
> - ret = spi_nor_write_sr_and_check(nor, best_status_new[0]);
> - else
> - ret = spi_nor_write_sr_cr_and_check(nor, best_status_new);
> + ret = spi_nor_write_sr1_and_sr2_and_check(nor, best_status_new);
> if (ret)
> return ret;
>
> @@ -409,20 +388,10 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
> int ret;
> u8 pow;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1_and_sr2(nor, status_old);
> if (ret)
> return ret;
>
> - status_old[0] = nor->bouncebuf[0];
> -
> - if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> - ret = spi_nor_read_cr(nor, nor->bouncebuf);
> - if (ret)
> - return ret;
> -
> - status_old[1] = nor->bouncebuf[0];
> - }
> -
> /* If nothing in our range is locked, we don't need to do anything */
> if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old))
> return 0;
> @@ -512,10 +481,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
> (ofs_new < ofs_old || (ofs_old + len_old) < (ofs_new + len_new)))
> return -EINVAL;
>
> - if (nor->flags & SNOR_F_NO_READ_CR)
> - ret = spi_nor_write_sr_and_check(nor, best_status_new[0]);
> - else
> - ret = spi_nor_write_sr_cr_and_check(nor, best_status_new);
> + ret = spi_nor_write_sr1_and_sr2_and_check(nor, best_status_new);
> if (ret)
> return ret;
>
> @@ -536,20 +502,10 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, u64 len)
> u8 sr_cr[2] = {};
> int ret;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1_and_sr2(nor, sr_cr);
> if (ret)
> return ret;
>
> - sr_cr[0] = nor->bouncebuf[0];
> -
> - if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> - ret = spi_nor_read_cr(nor, nor->bouncebuf);
> - if (ret)
> - return ret;
> -
> - sr_cr[1] = nor->bouncebuf[0];
> - }
> -
> return spi_nor_is_locked_sr(nor, ofs, len, sr_cr);
> }
>
> diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
> index 593429bd6cdf..01a693033448 100644
> --- a/drivers/mtd/spi-nor/winbond.c
> +++ b/drivers/mtd/spi-nor/winbond.c
> @@ -520,12 +520,12 @@ static int winbond_nor_late_init(struct spi_nor *nor)
> * been to declare CR reads as unsupported, whereas the Jedec
> * specification doesn't clearly state that. In practice, all these
> * chips do support reading back the CR, which is needed for SWP support,
> - * so make sure that capability remains enabled (needed for SWP).
> + * so make sure that capability remains enabled.
> * In practice, only exclude the old W25X family (JEDEC ID: EF 30 xx)
> * which actually does not support this feature.
> */
> if (nor->id[1] > 0x30)
> - nor->flags &= ~SNOR_F_NO_READ_CR;
> + params->opcodes.read_sr2 = SPINOR_OP_RDCR;
>
> /*
> * Winbond has reused many IDs, up to four times at this
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 4b92494827b1..f0b5a1989881 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -113,20 +113,16 @@
> #define SR_E_ERR BIT(5)
> #define SR_P_ERR BIT(6)
>
> -#define SR1_QUAD_EN_BIT6 BIT(6)
> -
> #define SR_BP_SHIFT 2
>
> /* Enhanced Volatile Configuration Register bits */
> #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
>
> /* Status Register 2 bits. */
> -#define SR2_QUAD_EN_BIT1 BIT(1)
> #define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */
> #define SR2_LB2 BIT(4) /* Security Register Lock Bit 2 */
> #define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */
> #define SR2_CMP_BIT6 BIT(6)
> -#define SR2_QUAD_EN_BIT7 BIT(7)
>
> /* Supported SPI protocols */
> #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 03/23] mtd: spi-nor: Refactor Read Status/Write Status support
@ 2026-08-14 12:25 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 12:25 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 61787 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> SPI NOR has a lot of history. Additions over additions, the subtleties
> of the JESD216 specification, their implementations by the manufacturers
> and the hardware mistakes have generated a gigantic maze, let's try to
> understand what is really needed.
>
> The specification explains the QE (Quad Enable) bitfield as describing
> where the bit to enable the Quad capability is, but also how to set
> it. Unfortunately, the specification is not precise about what opcodes
> are supported exactly in all the cases. There is an introduction that
> basically states:
> - Opcode 0x05 reads SR1
> - Opcode 0x35 reads SR2
> - Opcode 0x01 writes SR1, and then SR2 if another byte is written
>
> Then the bitfield, among indicating the location of the QE bit, may
> indicate:
> - Reading SR1 and SR2 in one operation is not possible (loops over the
> content of SR1)
> - Reading SR2 directly is possible
> - Only writing SR1 zeroes SR2.
>
> One problem with the current implementation, is that it only focuses on
> the QE bit. A quad_enable function was created for each case, even
> though in practice, the logic was always the same: read, modify, write,
> read back and verify. One problem comes when other features need to play
> with the status registers, like software block protection or OTP: you
> never know how to properly handle the QE bit, nor where it is, nor how
> to read/write the Status registers. This lead to
> approximations/guessing (in swp.c, otp.c and obviously in legacy
> controller drivers like atmel.c) but also to the implementation of a
> gazillon of helpers for reading/writing/checking the status registers.
>
> In addition, I believe some design decisions had a negative impact over
> the years.
>
> - All possible situations had to be flagged by the core. This is likely
> wrong, because we no longer know why we need specific quirks. It was
> ineherent to the state of the SPI NOR core before the great cleanup
> that had happened the past few years. I believe this creates confusion
> in the core today, and we should push this to vendor fixups
> instead. As an example, in 2023 Hsin-Yi was facing an issue because
> his chip was setting the wrong QER value, leading to RDCR being
> prevented, thus falling into a condition blindly setting a random QE
> bit (I strongy believe it is done like that for wrong reasons). His
> chip actually had RDCR support! The correct fix should have been to
> mark the capability in a device fixup instead of handling this in the
> core.
>
> Link: https://lore.kernel.org/lkml/CAJMQK-hR0eaO0b4Vd0U8_KAndLyZapqdHjVLAoe42rWi9rdLkA@mail.gmail.com/
>
> - SFDP parsing is over cautious. I believe
> BFPT_DWORD15_QER_SR2_BIT1_NO_RD is abusive (nothing states that RDCR is
> not supported), and BFPT_DWORD15_QER_SR2_BIT1 is also out of
> specification when forcing 16-bit Status writes.
>
> - SNOR_F_HAS_16BIT_SR is only imposing 16bit Status writes, whereas
> reads can still be 8-bit wide.
>
> - The usage of helpers verifying the writes was also spread for IMHO no
> really good reason. Why shouldn't we trust spi operations when it
> comes to Status Registers? We do not read back our page reads, so why
> status registers should be treated with so much care, if it's not
> because we are unsure of what is being done? My proposal includes a
> check when it comes to the QE bit (done once) but we don't need these
> checks otherwise. If the QE bit was written properly, there are high
> chances that the other register accesses will just be fine, no?
>
> Asde from my main quest, I also observed no good reason to ask the
> read/write status register callers to use nor->bouncebuf while the
> low-level helpers could do it themselves (we are talking about one or
> two bytes being copied).
>
> So after these observations, my proposal is the following:
> - Create private low level helpers that just read or write a status
> register. They are flexible, we can give the opcode (which varies
> based on the SFDP QER field) and the length (1 or 2).
> - Create public generic accessors which will be used to read/write sr1
> and/or sr2. This is where all the cleverness shall be. The helpers use
> the available opcodes for a given chip in order to fullfill the
> request.
> - Provide a single generic ->quad_enable() hook which generically does
> all the steps mentioned above (read, modify, write, read back and
> verify).
> - Create a list of opcodes for all 6 possible situations:
> {read, write} {sr1, sr2, sr1 and sr2}. These opcodes are
> filled/cleared based on the QER field. An opcode set to 0 indicates
> the absence of support (there is no 0x00 opcode in SPI NOR).
>
> I tried my best to analyze the current behavior and to mimic it as much
> as possible, but this is a risky cleanup. However, if we go for this, it
> will be *much* easier in the future to handle all kind of chip
> variations. We won't be limited to a couple of flags anymore, but rather
> we'll be able to just disable a read or write capability using a single
> line.
>
> Known deviations:
> - The Atmel manufacturer driver drives non SFDP chips which by default
> were receiving the HAS_16B_WR flag, forcing SR2 writes all the times,
> but it was deliberately making single bytes writes to SR1 for its
> locking operations. The flag is likely wrong for them, so I removed
> it.
> - I am proposing on purpose a single quad_enable helper. It should match
> all the cases, with 1 identified difference which I believe is
> harmless: in the SR2_BIT7 case, the helper would make an extra SR1
> read/write which was not done before. This entry explicitly supports
> reading and writing the two registers. Note: no manufacturer has been
> identified to actually use that entry yet.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> This is a really hard to review patch, it is big, full of changes
> everywhere, but I cannot really split it further. The commit log is
> really important, it tries to explain the steps I went through when
> trying to refactor the whole QE/SR handling for which I received
> feedback from Michael, Tudor and Sashiko.
>
> Ideally we could expect test coverage of each case:
> - BFPT_DWORD15_QER_NONE: Probably not needed
> - BFPT_DWORD15_QER_SR2_BIT1_BUGGY: Expected from Hsin-Yi (flag is being
> renamed _NO_1B_WR)
> - BFPT_DWORD15_QER_SR2_BIT1_NO_RD: Tested with a chip re-enabling RDCR
> in a fixup
> - BFPT_DWORD15_QER_SR1_BIT6: TBD
> - BFPT_DWORD15_QER_SR2_BIT7: TBD
> - BFPT_DWORD15_QER_SR2_BIT1: TBD
> - BFPT_DWORD15_QER_SR2_BIT1_1B: Done.
> There will probably be breakages on older chips. These cannot be
> guessed because they are not properly listed in manufacturer
> fixups (yet). If we want a cleanup/simplification, we will have to cope
> with this risk.
>
> I hope the diff stats will motivate people to have a look and report
> their testing.
>
> I will also eagerly monitor Sashiko's output which will probably be
> very useful to catch niche weird cases where these changes might break.
Honestly, I'm still not sold at the sr1 and sr2 split. But since
spi-nor is know for it's code churn. I could just rework that later
:)
Still I had some questions in the old thread:
I don't get why there should be any endianess problems?
Just the low level read and write would have to figure out how to
read and write the status registers.
> ---
> Documentation/driver-api/mtd/spi-nor.rst | 2 +-
> drivers/mtd/spi-nor/atmel.c | 52 +-
> drivers/mtd/spi-nor/core.c | 784 +++++++++++--------------------
> drivers/mtd/spi-nor/core.h | 57 +--
> drivers/mtd/spi-nor/debugfs.c | 2 -
> drivers/mtd/spi-nor/gigadevice.c | 6 +-
> drivers/mtd/spi-nor/issi.c | 3 +-
> drivers/mtd/spi-nor/macronix.c | 12 +-
> drivers/mtd/spi-nor/micron-st.c | 4 +-
> drivers/mtd/spi-nor/otp.c | 16 +-
> drivers/mtd/spi-nor/sfdp.c | 41 +-
> drivers/mtd/spi-nor/spansion.c | 16 +-
> drivers/mtd/spi-nor/sst.c | 5 +-
> drivers/mtd/spi-nor/swp.c | 58 +--
> drivers/mtd/spi-nor/winbond.c | 4 +-
> include/linux/mtd/spi-nor.h | 4 -
> 16 files changed, 416 insertions(+), 650 deletions(-)
>
> diff --git a/Documentation/driver-api/mtd/spi-nor.rst b/Documentation/driver-api/mtd/spi-nor.rst
> index 747a326fb6c0..5441fa7d4f04 100644
> --- a/Documentation/driver-api/mtd/spi-nor.rst
> +++ b/Documentation/driver-api/mtd/spi-nor.rst
> @@ -118,7 +118,7 @@ section, after the ``---`` marker.
> write size 1
> page size 256
> address nbytes 3
> - flags HAS_LOCK | HAS_16BIT_SR | SOFT_RESET | SWP_IS_VOLATILE
> + flags HAS_LOCK | SOFT_RESET | SWP_IS_VOLATILE
>
> opcodes
> read 0xeb
> diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
> index 82c592f0a1e1..8741c0bda497 100644
> --- a/drivers/mtd/spi-nor/atmel.c
> +++ b/drivers/mtd/spi-nor/atmel.c
> @@ -23,18 +23,28 @@ static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len)
>
> static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
> {
> + /* Write 0x00 to the status register to disable write protection */
> + u8 sr = 0;
> int ret;
>
> /* We only support unlocking the whole flash array */
> if (ofs || len != nor->params->size)
> return -EINVAL;
>
> - /* Write 0x00 to the status register to disable write protection */
> - ret = spi_nor_write_sr_and_check(nor, 0);
> + ret = spi_nor_write_sr1(nor, &sr);
> if (ret)
> - dev_dbg(nor->dev, "unable to clear BP bits, WP# asserted?\n");
> + return ret;
>
> - return ret;
> + ret = spi_nor_read_sr1(nor, &sr);
> + if (ret)
> + return ret;
> +
> + if (sr) {
> + dev_dbg(nor->dev, "unable to clear BP bits, WP# asserted?\n");
> + return -EIO;
> + }
> +
> + return 0;
> }
>
> static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, u64 len)
> @@ -50,6 +60,7 @@ static const struct spi_nor_locking_ops at25fs_nor_locking_ops = {
>
> static int at25fs_nor_late_init(struct spi_nor *nor)
> {
> + nor->params->opcodes.write_sr1 = SPINOR_OP_WRSR;
> nor->params->locking_ops = &at25fs_nor_locking_ops;
>
> return 0;
> @@ -69,6 +80,7 @@ static const struct spi_nor_fixups at25fs_nor_fixups = {
> * Return: 0 on success, -error otherwise.
> */
> static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
> +
> u64 len, bool is_protect)
> {
> int ret;
> @@ -78,19 +90,24 @@ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
> if (ofs || len != nor->params->size)
> return -EINVAL;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1(nor, &sr);
> if (ret)
> return ret;
>
> - sr = nor->bouncebuf[0];
> -
> /* SRWD bit needs to be cleared, otherwise the protection doesn't change */
> if (sr & SR_SRWD) {
> sr &= ~SR_SRWD;
> - ret = spi_nor_write_sr_and_check(nor, sr);
> - if (ret) {
> - dev_dbg(nor->dev, "unable to clear SRWD bit, WP# asserted?\n");
> + ret = spi_nor_write_sr1(nor, &sr);
> + if (ret)
> return ret;
> +
> + ret = spi_nor_read_sr1(nor, &sr);
> + if (ret)
> + return ret;
> +
> + if (sr & SR_SRWD) {
> + dev_dbg(nor->dev, "unable to clear SRWD bit, WP# asserted?\n");
> + return -EIO;
> }
> }
>
> @@ -108,14 +125,7 @@ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs,
> sr &= ~ATMEL_SR_GLOBAL_PROTECT_MASK;
> }
>
> - nor->bouncebuf[0] = sr;
> -
> - /*
> - * We cannot use the spi_nor_write_sr_and_check() because this command
> - * isn't really setting any bits, instead it is an pseudo command for
> - * "Global Unprotect" or "Global Protect"
> - */
> - return spi_nor_write_sr(nor, nor->bouncebuf, 1);
> + return spi_nor_write_sr1(nor, &sr);
> }
>
> static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs, u64 len)
> @@ -131,16 +141,17 @@ static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs, u64 len)
> static int atmel_nor_is_global_protected(struct spi_nor *nor, loff_t ofs,
> u64 len)
> {
> + u8 sr;
> int ret;
>
> if (ofs >= nor->params->size || (ofs + len) > nor->params->size)
> return -EINVAL;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1(nor, &sr);
> if (ret)
> return ret;
>
> - return ((nor->bouncebuf[0] & ATMEL_SR_GLOBAL_PROTECT_MASK) == ATMEL_SR_GLOBAL_PROTECT_MASK);
> + return ((sr & ATMEL_SR_GLOBAL_PROTECT_MASK) == ATMEL_SR_GLOBAL_PROTECT_MASK);
> }
>
> static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = {
> @@ -151,6 +162,7 @@ static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = {
>
> static int atmel_nor_global_protection_late_init(struct spi_nor *nor)
> {
> + nor->params->opcodes.write_sr1 = SPINOR_OP_WRSR;
> nor->params->locking_ops = &atmel_nor_global_protection_ops;
>
> return 0;
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index 29b8fe3d1c65..ac7812562047 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -443,75 +443,6 @@ int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
> return ret;
> }
>
> -/**
> - * spi_nor_read_sr() - Read the Status Register.
> - * @nor: pointer to 'struct spi_nor'.
> - * @sr: pointer to a DMA-able buffer where the value of the
> - * Status Register will be written. Should be at least 2 bytes.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
> -{
> - int ret;
> -
> - if (nor->spimem) {
> - struct spi_mem_op op = SPI_NOR_RDSR_OP(sr);
> -
> - if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
> - op.addr.nbytes = nor->params->rdsr_addr_nbytes;
> - op.dummy.nbytes = nor->params->rdsr_dummy;
> - /*
> - * We don't want to read only one byte in DTR mode. So,
> - * read 2 and then discard the second byte.
> - */
> - op.data.nbytes = 2;
> - }
> -
> - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
> -
> - ret = spi_mem_exec_op(nor->spimem, &op);
> - } else {
> - ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,
> - 1);
> - }
> -
> - if (ret)
> - dev_dbg(nor->dev, "error %d reading SR\n", ret);
> -
> - return ret;
> -}
> -
> -/**
> - * spi_nor_read_cr() - Read the Configuration Register using the
> - * SPINOR_OP_RDCR (35h) command.
> - * @nor: pointer to 'struct spi_nor'
> - * @cr: pointer to a DMA-able buffer where the value of the
> - * Configuration Register will be written.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
> -{
> - int ret;
> -
> - if (nor->spimem) {
> - struct spi_mem_op op = SPI_NOR_RDCR_OP(cr);
> -
> - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
> -
> - ret = spi_mem_exec_op(nor->spimem, &op);
> - } else {
> - ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr,
> - 1);
> - }
> -
> - if (ret)
> - dev_dbg(nor->dev, "error %d reading CR\n", ret);
> -
> - return ret;
> -}
> -
> /**
> * spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode
> * using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by
> @@ -617,12 +548,13 @@ int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable)
> int spi_nor_sr_ready(struct spi_nor *nor)
> {
> int ret;
> + u8 sr;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1(nor, &sr);
> if (ret)
> return ret;
>
> - return !(nor->bouncebuf[0] & SR_WIP);
> + return !(sr & SR_WIP);
> }
>
> /**
> @@ -784,345 +716,297 @@ int spi_nor_global_block_unlock(struct spi_nor *nor)
> }
>
> /**
> - * spi_nor_write_sr() - Write the Status Register.
> + * spi_nor_read_sr_ll() - Low-level Status Registers read.
> * @nor: pointer to 'struct spi_nor'.
> - * @sr: pointer to DMA-able buffer to write to the Status Register.
> - * @len: number of bytes to write to the Status Register.
> + * @opcode: opcode for the status register read operation.
> + * @sr: pointer to buffer for storing the content of the status registers.
> + * @len: number of status registers to read (1 or 2).
> *
> * Return: 0 on success, -errno otherwise.
> */
> -int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
> +static int spi_nor_read_sr_ll(struct spi_nor *nor, u8 opcode, u8 *sr,
> + unsigned int len)
> {
> - int ret;
> + int ret, i;
>
> - ret = spi_nor_write_enable(nor);
> - if (ret)
> - return ret;
> + if (len > 2)
> + return -EINVAL;
> +
> + for (i = 0; i < len; i++)
> + nor->bouncebuf[i] = 0;
>
> if (nor->spimem) {
> - struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len);
> + struct spi_mem_op op = SPI_NOR_RDSR_OP(opcode, nor->bouncebuf, len);
> +
> + if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
> + op.addr.nbytes = nor->params->rdsr_addr_nbytes;
> + op.dummy.nbytes = nor->params->rdsr_dummy;
> + /*
> + * We don't want to read only one byte in DTR mode. So,
> + * read 2 and then discard the second byte.
> + */
> + op.data.nbytes = 2;
> + }
>
> spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
>
> ret = spi_mem_exec_op(nor->spimem, &op);
> } else {
> - ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr,
> - len);
> + ret = spi_nor_controller_ops_read_reg(nor, opcode, nor->bouncebuf, len);
> }
>
> - if (ret) {
> - dev_dbg(nor->dev, "error %d writing SR\n", ret);
> - return ret;
> - }
> -
> - return spi_nor_wait_till_ready(nor);
> -}
> -
> -/**
> - * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
> - * ensure that the byte written match the received value.
> - * @nor: pointer to a 'struct spi_nor'.
> - * @sr1: byte value to be written to the Status Register.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
> -{
> - int ret;
> -
> - nor->bouncebuf[0] = sr1;
> -
> - ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
> - if (ret)
> - return ret;
> -
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> - if (ret)
> - return ret;
> -
> - if (nor->bouncebuf[0] != sr1) {
> - dev_dbg(nor->dev, "SR1: read back test failed\n");
> - return -EIO;
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
> - * Status Register 2 in one shot. Ensure that the byte written in the Status
> - * Register 1 match the received value, and that the 16-bit Write did not
> - * affect what was already in the Status Register 2.
> - * @nor: pointer to a 'struct spi_nor'.
> - * @sr1: byte value to be written to the Status Register 1.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
> -{
> - int ret;
> - u8 *sr_cr = nor->bouncebuf;
> - u8 cr_written;
> -
> - /* Make sure we don't overwrite the contents of Status Register 2. */
> - if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> - ret = spi_nor_read_cr(nor, &sr_cr[1]);
> - if (ret)
> - return ret;
> - } else if ((spi_nor_get_protocol_width(nor->read_proto) == 4 ||
> - spi_nor_get_protocol_width(nor->write_proto) == 4) &&
> - nor->params->quad_enable) {
> - /*
> - * If the Status Register 2 Read command (35h) is not
> - * supported, we should at least be sure we don't
> - * change the value of the SR2 Quad Enable bit.
> - *
> - * When the Quad Enable method is set and the buswidth is 4, we
> - * can safely assume that the value of the QE bit is one, as a
> - * consequence of the nor->params->quad_enable() call.
> - *
> - * According to the JESD216 revB standard, BFPT DWORDS[15],
> - * bits 22:20, the 16-bit Write Status (01h) command is
> - * available just for the cases in which the QE bit is
> - * described in SR2 at BIT(1).
> - */
> - sr_cr[1] = SR2_QUAD_EN_BIT1;
> - } else {
> - sr_cr[1] = 0;
> - }
> -
> - sr_cr[0] = sr1;
> -
> - ret = spi_nor_write_sr(nor, sr_cr, 2);
> - if (ret)
> - return ret;
> -
> - ret = spi_nor_read_sr(nor, sr_cr);
> - if (ret)
> - return ret;
> -
> - if (sr1 != sr_cr[0]) {
> - dev_dbg(nor->dev, "SR: Read back test failed\n");
> - return -EIO;
> - }
> -
> - if (nor->flags & SNOR_F_NO_READ_CR)
> - return 0;
> -
> - cr_written = sr_cr[1];
> -
> - ret = spi_nor_read_cr(nor, &sr_cr[1]);
> - if (ret)
> - return ret;
> -
> - if (cr_written != sr_cr[1]) {
> - dev_dbg(nor->dev, "CR: read back test failed\n");
> - return -EIO;
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
> - * Configuration Register in one shot. Ensure that the byte written in the
> - * Configuration Register match the received value, and that the 16-bit Write
> - * did not affect what was already in the Status Register 1.
> - * @nor: pointer to a 'struct spi_nor'.
> - * @cr: byte value to be written to the Configuration Register.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
> -{
> - int ret;
> - u8 *sr_cr = nor->bouncebuf;
> - u8 sr_written;
> -
> - /* Keep the current value of the Status Register 1. */
> - ret = spi_nor_read_sr(nor, sr_cr);
> - if (ret)
> - return ret;
> -
> - sr_cr[1] = cr;
> -
> - ret = spi_nor_write_sr(nor, sr_cr, 2);
> - if (ret)
> - return ret;
> -
> - sr_written = sr_cr[0];
> -
> - ret = spi_nor_read_sr(nor, sr_cr);
> - if (ret)
> - return ret;
> -
> - if (sr_written != sr_cr[0]) {
> - dev_dbg(nor->dev, "SR: Read back test failed\n");
> - return -EIO;
> - }
> -
> - if (nor->flags & SNOR_F_NO_READ_CR)
> - return 0;
> -
> - ret = spi_nor_read_cr(nor, &sr_cr[1]);
> - if (ret)
> - return ret;
> -
> - if (cr != sr_cr[1]) {
> - dev_dbg(nor->dev, "CR: read back test failed\n");
> - return -EIO;
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * spi_nor_write_16bit_sr_cr_and_check() - Write the Status Register 1 and the
> - * Configuration Register in one shot. Ensure that the bytes written in both
> - * registers match the received value.
> - * @nor: pointer to a 'struct spi_nor'.
> - * @regs: two-byte array with values to be written to the status and
> - * configuration registers.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spi_nor_write_16bit_sr_cr_and_check(struct spi_nor *nor, const u8 *regs)
> -{
> - u8 written_regs[2];
> - int ret;
> -
> - written_regs[0] = regs[0];
> - written_regs[1] = regs[1];
> - nor->bouncebuf[0] = regs[0];
> - nor->bouncebuf[1] = regs[1];
> -
> - ret = spi_nor_write_sr(nor, nor->bouncebuf, 2);
> - if (ret)
> - return ret;
> -
> - ret = spi_nor_read_sr(nor, &nor->bouncebuf[0]);
> - if (ret)
> - return ret;
> -
> - if (written_regs[0] != nor->bouncebuf[0]) {
> - dev_dbg(nor->dev, "SR: Read back test failed\n");
> - return -EIO;
> - }
> -
> - if (nor->flags & SNOR_F_NO_READ_CR)
> - return 0;
> -
> - ret = spi_nor_read_cr(nor, &nor->bouncebuf[1]);
> - if (ret)
> - return ret;
> -
> - if (written_regs[1] != nor->bouncebuf[1]) {
> - dev_dbg(nor->dev, "CR: read back test failed\n");
> - return -EIO;
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
> - * the byte written match the received value without affecting other bits in the
> - * Status Register 1 and 2.
> - * @nor: pointer to a 'struct spi_nor'.
> - * @sr1: byte value to be written to the Status Register.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
> -{
> - if (nor->flags & SNOR_F_HAS_16BIT_SR)
> - return spi_nor_write_16bit_sr_and_check(nor, sr1);
> -
> - return spi_nor_write_sr1_and_check(nor, sr1);
> -}
> -
> -/**
> - * spi_nor_write_sr_cr_and_check() - Write the Status Register 1 and ensure that
> - * the byte written match the received value. Same for the Control Register if
> - * available.
> - * @nor: pointer to a 'struct spi_nor'.
> - * @regs: byte array to be written to the registers.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs)
> -{
> - if (nor->flags & SNOR_F_HAS_16BIT_SR)
> - return spi_nor_write_16bit_sr_cr_and_check(nor, regs);
> -
> - return spi_nor_write_sr1_and_check(nor, regs[0]);
> -}
> -
> -/**
> - * spi_nor_write_sr2() - Write the Status Register 2 using the
> - * SPINOR_OP_WRSR2 (3eh) command.
> - * @nor: pointer to 'struct spi_nor'.
> - * @sr2: pointer to DMA-able buffer to write to the Status Register 2.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
> -{
> - int ret;
> -
> - ret = spi_nor_write_enable(nor);
> - if (ret)
> - return ret;
> -
> - if (nor->spimem) {
> - struct spi_mem_op op = SPI_NOR_WRSR2_OP(sr2);
> -
> - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
> -
> - ret = spi_mem_exec_op(nor->spimem, &op);
> - } else {
> - ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2,
> - sr2, 1);
> - }
> -
> - if (ret) {
> - dev_dbg(nor->dev, "error %d writing SR2\n", ret);
> - return ret;
> - }
> -
> - return spi_nor_wait_till_ready(nor);
> -}
> -
> -/**
> - * spi_nor_read_sr2() - Read the Status Register 2 using the
> - * SPINOR_OP_RDSR2 (3fh) command.
> - * @nor: pointer to 'struct spi_nor'.
> - * @sr2: pointer to DMA-able buffer where the value of the
> - * Status Register 2 will be written.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
> -{
> - int ret;
> -
> - if (nor->spimem) {
> - struct spi_mem_op op = SPI_NOR_RDSR2_OP(sr2);
> -
> - spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
> -
> - ret = spi_mem_exec_op(nor->spimem, &op);
> - } else {
> - ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2,
> - 1);
> - }
> + memcpy(sr, nor->bouncebuf, len);
>
> if (ret)
> - dev_dbg(nor->dev, "error %d reading SR2\n", ret);
> + dev_dbg(nor->dev, "Error %d reading Status Registers\n", ret);
>
> return ret;
> }
>
> +/**
> + * spi_nor_write_sr_ll() - Low-level Status Registers write.
> + * @nor: pointer to 'struct spi_nor'.
> + * @opcode: opcode for the status register write operation.
> + * @sr: pointer to status registers buffer to write.
> + * @len: number of status registers to write.
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +static int spi_nor_write_sr_ll(struct spi_nor *nor, u8 opcode, const u8 *sr,
> + unsigned int len)
> +{
> + int ret, i;
> +
> + if (len > 2)
> + return -EINVAL;
> +
> + ret = spi_nor_write_enable(nor);
> + if (ret)
> + return ret;
> +
> + for (i = 0; i < len; i++)
> + nor->bouncebuf[i] = sr[i];
> +
> + if (nor->spimem) {
> + struct spi_mem_op op = SPI_NOR_WRSR_OP(opcode,
> + nor->bouncebuf, len);
> +
> + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
> +
> + ret = spi_mem_exec_op(nor->spimem, &op);
> + } else {
> + ret = spi_nor_controller_ops_write_reg(nor, opcode,
> + nor->bouncebuf, len);
> + }
> +
> + if (ret) {
> + dev_dbg(nor->dev, "Error %d writing Status Registers\n", ret);
> + return ret;
> + }
> +
> + return spi_nor_wait_till_ready(nor);
> +}
> +
> +/**
> + * spi_nor_read_sr1() - Read SR1 only
> + * Useful for:
> + * - The core to offer a generic "read SR1 and SR2" capability
> + * - Manufacturer drivers (since they know the chip SR layout)
> + * - Polling the BUSY bit in the core
> + *
> + * @nor: the spi_nor structure
> + * @sr1: pointer to a valid SR1 buffer
> + *
> + * Return 0 or errno.
> + */
> +int spi_nor_read_sr1(struct spi_nor *nor, u8 *sr1)
> +{
> + return spi_nor_read_sr_ll(nor, nor->params->opcodes.read_sr1, sr1, 1);
> +}
> +
> +/**
> + * spi_nor_read_sr2() - Read SR2 only
> + * Useful for:
> + * - The core to offer a generic "read SR1 and SR2" capability
> + * - Manufacturer drivers (since they know the chip SR layout)
> + * - SR2 based OTP configuration
> + *
> + * @nor: the spi_nor structure
> + * @sr2: pointer to a valid SR2 buffer
> + *
> + * Return 0 or errno.
> + */
> +int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
> +{
> + struct spi_nor_flash_parameter *params = nor->params;
> + int ret;
> +
> + if (params->opcodes.read_sr2) {
> + ret = spi_nor_read_sr_ll(nor, params->opcodes.read_sr2, sr2, 1);
> + if (ret)
> + return ret;
> + } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
> + spi_nor_get_protocol_width(nor->write_proto) == 4) {
> + /* Make sure the QE bit is persistently kept */
> + *sr2 = params->qe_mask[1];
Mh. So before there was at least a check if a quad_enable cb is set.
Is this now implicit? because qe_mask[1] is zero if there is no
quad_enable? That should at *least* get some comment.
I tried to actually get the original use case, but all I've found
is Tudors commit 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit
on lock()/unlock()"). There wasn't much of a discussion on the ML,
and I couldn't find where Boris was suggesting it.
So before we cannot get rid of it anymore, we should just handle it
in the one caller which actually uses it: spi_nor_sr_{un,}lock().
I've checked the current spi_nor_write_sr_and_check() and the only
actual user is the swp.c. atmel.c is doing global write protection
on/off, which IIRC only uses SR1.
So let's move that weird handling there. Then chances are, we can
get rid of it as we know what flashes do locking because that is not
discoverable at runtime. It's just tedious work to check all the
datasheets. But as soon as we now put that into a more generic path,
we can't do anything about it anymore.
> + } else {
> + *sr2 = 0;
I'd expect an -EINVAL or -EIO here.
-michael
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * spi_nor_read_sr1_and_sr2() - Read SR1 then SR2
> + * General purpose helper, always safe to call.
> + *
> + * @nor: the spi_nor structure
> + * @sr: pointer to a valid 2-byte array
> + *
> + * Return 0 or errno.
> + */
> +int spi_nor_read_sr1_and_sr2(struct spi_nor *nor, u8 *sr)
> +{
> + int ret;
> +
> + ret = spi_nor_read_sr1(nor, &sr[0]);
> + if (ret)
> + return ret;
> +
> + return spi_nor_read_sr2(nor, &sr[1]);
> +}
> +
> +/**
> + * spi_nor_write_sr1() - Write SR1 only
> + * Useful for:
> + * - Manufacturer drivers (since they know the chip SR layout)
> + *
> + * @nor: the spi_nor structure
> + * @sr1: pointer to a valid SR1 buffer
> + *
> + * Return 0 or errno.
> + */
> +int spi_nor_write_sr1(struct spi_nor *nor, const u8 *sr1)
> +{
> + if (WARN_ONCE(!nor->params->opcodes.write_sr1,
> + "Restricted helper use, write SR1 not supported"))
> + return -EIO;
> +
> + return spi_nor_write_sr_ll(nor, nor->params->opcodes.write_sr1, sr1, 1);
> +}
> +
> +/**
> + * spi_nor_write_sr2() - Write SR2 only
> + * Useful for:
> + * - Manufacturer drivers (since they know the chip SR layout)
> + * - SR2 based OTP configuration
> + *
> + * @nor: the spi_nor structure
> + * @sr2: pointer to a valid SR2 buffer
> + *
> + * Return 0 or errno.
> + */
> +int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
> +{
> + if (WARN_ONCE(!nor->params->opcodes.write_sr2,
> + "Restricted helper use, write SR2 not supported"))
> + return -EIO;
> +
> + return spi_nor_write_sr_ll(nor, nor->params->opcodes.write_sr2, sr2, 1);
> +}
> +
> +/**
> + * spi_nor_write_sr1_and_sr2() - Write SR1 then SR2
> + * General purpose helper, always safe to call. Will expectedly ignore
> + * SR2 on certain chips.
> + *
> + * @nor: the spi_nor structure
> + * @sr: pointer to a valid 2-byte array
> + *
> + * Return 0 or errno.
> + */
> +static int spi_nor_write_sr1_and_sr2(struct spi_nor *nor, const u8 *sr)
> +{
> + struct spi_nor_flash_parameter *params = nor->params;
> + int ret;
> +
> + if (params->opcodes.write_sr1_and_sr2)
> + return spi_nor_write_sr_ll(nor,
> + params->opcodes.write_sr1_and_sr2,
> + sr, 2);
> +
> + ret = spi_nor_write_sr1(nor, &sr[0]);
> + if (ret)
> + return ret;
> +
> + if (params->opcodes.write_sr2)
> + return spi_nor_write_sr2(nor, &sr[1]);
> +
> + return 0;
> +}
> +
> +/**
> + * spi_nor_write_sr1_and_sr2_and_check() - Write SR1 then SR2, then read
> + * them back and verifies
> + * General purpose helper, always safe to call. Will expectedly ignore
> + * SR2 on certain chips.
> + *
> + * @nor: the spi_nor structure
> + * @sr: pointer to a valid 2-byte array
> + *
> + * Return 0 or errno.
> + */
> +int spi_nor_write_sr1_and_sr2_and_check(struct spi_nor *nor, const u8 *sr)
> +{
> + u8 tmp[2];
> + int ret;
> +
> + ret = spi_nor_write_sr1_and_sr2(nor, sr);
> + if (ret)
> + return ret;
> +
> + ret = spi_nor_read_sr1_and_sr2(nor, tmp);
> + if (ret)
> + return ret;
> +
> + if (sr[0] != tmp[0] || sr[1] != tmp[1])
> + return -EIO;
> +
> + return 0;
> +}
> +
> +/**
> + * spi_nor_generic_quad_enable() - Read the status registers,
> + * apply the QE bit mask,
> + * write the status registers,
> + * read them back and check the content.
> + *
> + * @nor: pointer to 'struct spi_nor'
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +static int spi_nor_generic_quad_enable(struct spi_nor *nor)
> +{
> + u8 *qe_mask = nor->params->qe_mask;
> + u8 sr[2] = {};
> + int ret;
> +
> + if (!qe_mask[0] && !qe_mask[1])
> + return 0;
> +
> + ret = spi_nor_read_sr1_and_sr2(nor, sr);
> + if (ret)
> + return ret;
> +
> + if (sr[0] & qe_mask[0] || sr[1] & qe_mask[1])
> + return 0;
> +
> + sr[0] |= qe_mask[0];
> + sr[1] |= qe_mask[1];
> +
> + return spi_nor_write_sr1_and_sr2_and_check(nor, sr);
> +}
> +
> /**
> * spi_nor_erase_die() - Erase the entire die.
> * @nor: pointer to 'struct spi_nor'.
> @@ -1904,106 +1788,6 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
> return ret;
> }
>
> -/**
> - * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
> - * Register 1.
> - * @nor: pointer to a 'struct spi_nor'
> - *
> - * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
> -{
> - int ret;
> -
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> - if (ret)
> - return ret;
> -
> - if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
> - return 0;
> -
> - nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
> -
> - return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
> -}
> -
> -/**
> - * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
> - * Register 2.
> - * @nor: pointer to a 'struct spi_nor'.
> - *
> - * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
> -{
> - int ret;
> -
> - if (nor->flags & SNOR_F_NO_READ_CR)
> - return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
> -
> - ret = spi_nor_read_cr(nor, nor->bouncebuf);
> - if (ret)
> - return ret;
> -
> - if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
> - return 0;
> -
> - nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
> -
> - return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
> -}
> -
> -/**
> - * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
> - * @nor: pointer to a 'struct spi_nor'
> - *
> - * Set the Quad Enable (QE) bit in the Status Register 2.
> - *
> - * This is one of the procedures to set the QE bit described in the SFDP
> - * (JESD216 rev B) specification but no manufacturer using this procedure has
> - * been identified yet, hence the name of the function.
> - *
> - * Return: 0 on success, -errno otherwise.
> - */
> -int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
> -{
> - u8 *sr2 = nor->bouncebuf;
> - int ret;
> - u8 sr2_written;
> -
> - /* Check current Quad Enable bit value. */
> - ret = spi_nor_read_sr2(nor, sr2);
> - if (ret)
> - return ret;
> - if (*sr2 & SR2_QUAD_EN_BIT7)
> - return 0;
> -
> - /* Update the Quad Enable bit. */
> - *sr2 |= SR2_QUAD_EN_BIT7;
> -
> - ret = spi_nor_write_sr2(nor, sr2);
> - if (ret)
> - return ret;
> -
> - sr2_written = *sr2;
> -
> - /* Read back and check it. */
> - ret = spi_nor_read_sr2(nor, sr2);
> - if (ret)
> - return ret;
> -
> - if (*sr2 != sr2_written) {
> - dev_dbg(nor->dev, "SR2: Read back test failed\n");
> - return -EIO;
> - }
> -
> - return 0;
> -}
> -
> static const struct spi_nor_manufacturer *manufacturers[] = {
> &spi_nor_atmel,
> &spi_nor_eon,
> @@ -2494,6 +2278,7 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
> {
> struct spi_nor_flash_parameter *params = nor->params;
> unsigned int cap;
> + u8 opcode;
>
> /* X-X-X modes are not supported yet, mask them all. */
> *hwcaps &= ~SNOR_HWCAPS_X_X_X;
> @@ -2525,14 +2310,14 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
> *hwcaps &= ~BIT(cap);
> }
>
> - /* Some SPI controllers might not support CR read opcode. */
> - if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> - struct spi_mem_op op = SPI_NOR_RDCR_OP(nor->bouncebuf);
> -
> + /* Some SPI controllers might not support reading SR2 */
> + opcode = nor->params->opcodes.read_sr2;
> + if (opcode) {
> + struct spi_mem_op op = SPI_NOR_RDSR_OP(opcode, nor->bouncebuf, 1);
> spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
>
> if (!spi_mem_supports_op(nor->spimem, &op))
> - nor->flags |= SNOR_F_NO_READ_CR;
> + nor->params->opcodes.read_sr2 = 0;
> }
> }
>
> @@ -3107,11 +2892,14 @@ static void spi_nor_init_default_params(struct spi_nor *nor)
> const struct flash_info *info = nor->info;
> struct device_node *np = spi_nor_get_flash_node(nor);
>
> - params->quad_enable = spi_nor_sr2_bit1_quad_enable;
> - params->otp.org = info->otp;
> + /* Default to 16-bit Read/Write Status commands */
> + params->opcodes.read_sr1 = SPINOR_OP_RDSR;
> + params->opcodes.read_sr2 = SPINOR_OP_RDCR;
> + params->opcodes.write_sr1_and_sr2 = SPINOR_OP_WRSR;
> + params->quad_enable = spi_nor_generic_quad_enable;
> + params->qe_mask[1] = BIT(1);
>
> - /* Default to 16-bit Write Status (01h) Command */
> - nor->flags |= SNOR_F_HAS_16BIT_SR;
> + params->otp.org = info->otp;
>
> /* Set SPI NOR sizes. */
> params->writesize = 1;
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 2cc0c80da3fa..7d43d3ba47ee 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -37,36 +37,18 @@
> SPI_MEM_OP_NO_DUMMY, \
> SPI_MEM_OP_NO_DATA)
>
> -#define SPI_NOR_RDSR_OP(buf) \
> - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), \
> +#define SPI_NOR_RDSR_OP(opcode, buf, len) \
> + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
> SPI_MEM_OP_NO_ADDR, \
> SPI_MEM_OP_NO_DUMMY, \
> - SPI_MEM_OP_DATA_IN(1, buf, 0))
> + SPI_MEM_OP_DATA_IN(len, buf, 0))
>
> -#define SPI_NOR_WRSR_OP(buf, len) \
> - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), \
> +#define SPI_NOR_WRSR_OP(opcode, buf, len) \
> + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
> SPI_MEM_OP_NO_ADDR, \
> SPI_MEM_OP_NO_DUMMY, \
> SPI_MEM_OP_DATA_OUT(len, buf, 0))
>
> -#define SPI_NOR_RDSR2_OP(buf) \
> - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), \
> - SPI_MEM_OP_NO_ADDR, \
> - SPI_MEM_OP_NO_DUMMY, \
> - SPI_MEM_OP_DATA_OUT(1, buf, 0))
> -
> -#define SPI_NOR_WRSR2_OP(buf) \
> - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), \
> - SPI_MEM_OP_NO_ADDR, \
> - SPI_MEM_OP_NO_DUMMY, \
> - SPI_MEM_OP_DATA_OUT(1, buf, 0))
> -
> -#define SPI_NOR_RDCR_OP(buf) \
> - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), \
> - SPI_MEM_OP_NO_ADDR, \
> - SPI_MEM_OP_NO_DUMMY, \
> - SPI_MEM_OP_DATA_IN(1, buf, 0))
> -
> #define SPI_NOR_EN4B_EX4B_OP(enable) \
> SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B, 0), \
> SPI_MEM_OP_NO_ADDR, \
> @@ -129,8 +111,6 @@ enum spi_nor_option_flags {
> SNOR_F_4B_OPCODES = BIT(3),
> SNOR_F_HAS_4BAIT = BIT(4),
> SNOR_F_HAS_LOCK = BIT(5),
> - SNOR_F_HAS_16BIT_SR = BIT(6),
> - SNOR_F_NO_READ_CR = BIT(7),
> SNOR_F_HAS_SR_TB_BIT6 = BIT(8),
> SNOR_F_HAS_4BIT_BP = BIT(9),
> SNOR_F_HAS_SR_BP3_BIT6 = BIT(10),
> @@ -345,9 +325,19 @@ struct spi_nor_otp {
> * List of variable opcodes used by the chip.
> *
> * @die_erase: opcode for erasing a die, defaults to SPINOR_OP_CHIP_ERASE
> + * @read_sr1: opcode for reading SR1 alone
> + * @read_sr2: opcode for reading SR2 alone
> + * @write_sr1: opcode for writing SR1 alone
> + * @write_sr2: opcode for writing SR2 alone
> + * @write_sr1_and_sr2: opcode for writing SR1 then SR2 in one operation
> */
> struct spi_nor_opcodes {
> u8 die_erase;
> + u8 read_sr1;
> + u8 read_sr2;
> + u8 write_sr1;
> + u8 write_sr2;
> + u8 write_sr1_and_sr2;
> };
>
> /**
> @@ -384,6 +374,7 @@ struct spi_nor_opcodes {
> * @otp: SPI NOR OTP info.
> * @set_octal_dtr: enables or disables SPI NOR octal DTR mode.
> * @quad_enable: enables SPI NOR quad mode.
> + * @qe_mask: two bytes mask used to set/clear the QE bit
> * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
> * @ready: (optional) flashes might use a different mechanism
> * than reading the status register to indicate they
> @@ -413,6 +404,7 @@ struct spi_nor_flash_parameter {
>
> int (*set_octal_dtr)(struct spi_nor *nor, bool enable);
> int (*quad_enable)(struct spi_nor *nor);
> + u8 qe_mask[2];
> int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
> int (*ready)(struct spi_nor *nor);
>
> @@ -641,18 +633,15 @@ int spi_nor_wait_till_ready(struct spi_nor *nor);
> int spi_nor_global_block_unlock(struct spi_nor *nor);
> int spi_nor_prep_and_lock(struct spi_nor *nor);
> void spi_nor_unlock_and_unprep(struct spi_nor *nor);
> -int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor);
> -int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor);
> -int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor);
> int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
> enum spi_nor_protocol reg_proto);
> -int spi_nor_read_sr(struct spi_nor *nor, u8 *sr);
> int spi_nor_sr_ready(struct spi_nor *nor);
> -int spi_nor_read_cr(struct spi_nor *nor, u8 *cr);
> -int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len);
> -int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1);
> -int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr);
> -int spi_nor_write_sr_cr_and_check(struct spi_nor *nor, const u8 *regs);
> +int spi_nor_read_sr1(struct spi_nor *nor, u8 *sr1);
> +int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2);
> +int spi_nor_read_sr1_and_sr2(struct spi_nor *nor, u8 *sr);
> +int spi_nor_write_sr1(struct spi_nor *nor, const u8 *sr1);
> +int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2);
> +int spi_nor_write_sr1_and_sr2_and_check(struct spi_nor *nor, const u8 *sr);
>
> ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
> u8 *buf);
> diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
> index ef6f0ffcd6bb..512825c3fc85 100644
> --- a/drivers/mtd/spi-nor/debugfs.c
> +++ b/drivers/mtd/spi-nor/debugfs.c
> @@ -19,8 +19,6 @@ static const char *const snor_f_names[] = {
> SNOR_F_NAME(4B_OPCODES),
> SNOR_F_NAME(HAS_4BAIT),
> SNOR_F_NAME(HAS_LOCK),
> - SNOR_F_NAME(HAS_16BIT_SR),
> - SNOR_F_NAME(NO_READ_CR),
> SNOR_F_NAME(HAS_SR_TB_BIT6),
> SNOR_F_NAME(HAS_4BIT_BP),
> SNOR_F_NAME(HAS_SR_BP3_BIT6),
> diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
> index ef1edd0add70..4070a692e968 100644
> --- a/drivers/mtd/spi-nor/gigadevice.c
> +++ b/drivers/mtd/spi-nor/gigadevice.c
> @@ -23,8 +23,10 @@ gd25q256_post_bfpt(struct spi_nor *nor,
> * GD25Q256E | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR
> */
> if (bfpt_header->major == SFDP_JESD216_MAJOR &&
> - bfpt_header->minor == SFDP_JESD216_MINOR)
> - nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> + bfpt_header->minor == SFDP_JESD216_MINOR) {
> + nor->params->qe_mask[0] = BIT(6);
> + nor->params->qe_mask[1] = 0;
> + }
>
> return 0;
> }
> diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
> index 18d9a00aa22e..04db42b5141e 100644
> --- a/drivers/mtd/spi-nor/issi.c
> +++ b/drivers/mtd/spi-nor/issi.c
> @@ -131,7 +131,8 @@ static const struct flash_info issi_nor_parts[] = {
>
> static void issi_nor_default_init(struct spi_nor *nor)
> {
> - nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> + nor->params->qe_mask[0] = BIT(6);
> + nor->params->qe_mask[1] = 0;
> }
>
> static const struct spi_nor_fixups issi_fixups = {
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index e97f5cbd9aad..55612237c1ef 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -65,11 +65,12 @@ mx25l3255e_late_init_fixups(struct spi_nor *nor)
>
> /*
> * SFDP of MX25L3255E is JESD216, which does not include the Quad
> - * Enable bit Requirement in BFPT. As a result, during BFPT parsing,
> - * the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.
> - * Therefore, it is necessary to correct this setting by late_init.
> + * Enable bit Requirement in BFPT. As a result, during BFPT parsing
> + * the quad_enable mask is reset. Therefore, it is necessary to
> + * correct this setting by late_init.
> */
> - params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> + params->qe_mask[0] = BIT(6);
> + params->qe_mask[1] = 0;
>
> /*
> * In addition, MX25L3255E also supports 1-4-4 page program in 3-byte
> @@ -314,7 +315,8 @@ static int macronix_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
>
> static void macronix_nor_default_init(struct spi_nor *nor)
> {
> - nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> + nor->params->qe_mask[0] = BIT(6);
> + nor->params->qe_mask[1] = 0;
> }
>
> static int macronix_nor_late_init(struct spi_nor *nor)
> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
> index 031cf887318c..344539d2a36a 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -229,7 +229,7 @@ static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor,
> const struct sfdp_parameter_header *bfpt_header,
> const struct sfdp_bfpt *bfpt)
> {
> - nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> + nor->params->opcodes.write_sr1 = 0;
> return 0;
> }
>
> @@ -633,7 +633,7 @@ static int micron_st_nor_ready(struct spi_nor *nor)
> static void micron_st_nor_default_init(struct spi_nor *nor)
> {
> nor->flags |= SNOR_F_HAS_LOCK;
> - nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> + nor->params->opcodes.write_sr1 = 0;
> nor->params->quad_enable = NULL;
> }
>
> diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
> index 7d0b145d78d8..1eeb33a20091 100644
> --- a/drivers/mtd/spi-nor/otp.c
> +++ b/drivers/mtd/spi-nor/otp.c
> @@ -175,24 +175,24 @@ static int spi_nor_otp_lock_bit_cr(unsigned int region)
> */
> int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigned int region)
> {
> - u8 *cr = nor->bouncebuf;
> int ret, lock_bit;
> + u8 sr[2];
>
> lock_bit = spi_nor_otp_lock_bit_cr(region);
> if (lock_bit < 0)
> return lock_bit;
>
> - ret = spi_nor_read_cr(nor, cr);
> + ret = spi_nor_read_sr1_and_sr2(nor, sr);
> if (ret)
> return ret;
>
> /* no need to write the register if region is already locked */
> - if (cr[0] & lock_bit)
> + if (sr[1] & lock_bit)
> return 0;
>
> - cr[0] |= lock_bit;
> + sr[1] |= lock_bit;
>
> - return spi_nor_write_16bit_cr_and_check(nor, cr[0]);
> + return spi_nor_write_sr1_and_sr2_and_check(nor, sr);
> }
>
> /**
> @@ -207,18 +207,18 @@ int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigned int region)
> */
> int spi_nor_otp_is_locked_sr2(struct spi_nor *nor, unsigned int region)
> {
> - u8 *cr = nor->bouncebuf;
> int ret, lock_bit;
> + u8 sr2;
>
> lock_bit = spi_nor_otp_lock_bit_cr(region);
> if (lock_bit < 0)
> return lock_bit;
>
> - ret = spi_nor_read_cr(nor, cr);
> + ret = spi_nor_read_sr2(nor, &sr2);
> if (ret)
> return ret;
>
> - return cr[0] & lock_bit;
> + return sr2 & lock_bit;
> }
>
> static loff_t spi_nor_otp_region_start(const struct spi_nor *nor, unsigned int region)
> diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
> index 526763c79f55..1d799f02b8e5 100644
> --- a/drivers/mtd/spi-nor/sfdp.c
> +++ b/drivers/mtd/spi-nor/sfdp.c
> @@ -561,10 +561,21 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> val >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
> params->page_size = 1U << val;
>
> + /*
> + * The standard declares various read and write status methods, some of
> + * them will be overloaded based on the QER field.
> + */
> + params->opcodes.read_sr1 = SPINOR_OP_RDSR;
> + params->opcodes.read_sr2 = SPINOR_OP_RDCR;
> + params->opcodes.write_sr1 = SPINOR_OP_WRSR;
> + params->opcodes.write_sr1_and_sr2 = SPINOR_OP_WRSR;
> +
> + params->qe_mask[0] = 0;
> + params->qe_mask[1] = 0;
> +
> /* Quad Enable Requirements. */
> switch (bfpt.dwords[SFDP_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
> case BFPT_DWORD15_QER_NONE:
> - params->quad_enable = NULL;
> break;
>
> case BFPT_DWORD15_QER_SR2_BIT1_NO_1B_WR:
> @@ -572,23 +583,28 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> * Writing only one byte to the Status Register has the
> * side-effect of clearing Status Register 2.
> */
> + fallthrough;
> case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
> /*
> * Read Configuration Register (35h) instruction is not
> - * supported.
> + * supported. 16-bit writes expected.
> */
> - nor->flags |= SNOR_F_HAS_16BIT_SR | SNOR_F_NO_READ_CR;
> - params->quad_enable = spi_nor_sr2_bit1_quad_enable;
> + params->opcodes.read_sr2 = 0;
> + params->opcodes.write_sr1 = 0;
> + params->qe_mask[1] = BIT(1);
> break;
>
> case BFPT_DWORD15_QER_SR1_BIT6:
> - nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> - params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> + params->opcodes.read_sr2 = 0;
> + params->opcodes.write_sr1_and_sr2 = 0;
> + params->qe_mask[0] = BIT(6);
> break;
>
> case BFPT_DWORD15_QER_SR2_BIT7:
> - nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> - params->quad_enable = spi_nor_sr2_bit7_quad_enable;
> + params->opcodes.read_sr2 = SPINOR_OP_RDSR2;
> + params->opcodes.write_sr1_and_sr2 = 0;
> + params->opcodes.write_sr2 = SPINOR_OP_WRSR2;
> + params->qe_mask[1] = BIT(7);
> break;
>
> case BFPT_DWORD15_QER_SR2_BIT1:
> @@ -598,9 +614,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> * Register 2, so let's be cautious and keep the default
> * assumption of a 16-bit Write Status (01h) command.
> */
> - nor->flags |= SNOR_F_HAS_16BIT_SR;
> -
> - params->quad_enable = spi_nor_sr2_bit1_quad_enable;
> + params->opcodes.write_sr1 = 0;
> + params->qe_mask[1] = BIT(1);
> break;
>
> default:
> @@ -608,6 +623,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> break;
> }
>
> + /* opcodes sanity check */
> + WARN_ON(!params->opcodes.read_sr1 ||
> + (!params->opcodes.write_sr1 && !params->opcodes.write_sr1_and_sr2));
> +
> dword = bfpt.dwords[SFDP_DWORD(16)] & BFPT_DWORD16_4B_ADDR_MODE_MASK;
> if (SFDP_MASK_CHECK(dword, BFPT_DWORD16_4B_ADDR_MODE_BRWR))
> params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr;
> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
> index 2a8238c707e1..ca2703a5a338 100644
> --- a/drivers/mtd/spi-nor/spansion.c
> +++ b/drivers/mtd/spi-nor/spansion.c
> @@ -399,8 +399,9 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
> nor->bouncebuf);
> bool is3byte, is4byte;
> int ret;
> + u8 sr;
>
> - ret = spi_nor_read_sr(nor, &nor->bouncebuf[1]);
> + ret = spi_nor_read_sr1(nor, &sr);
> if (ret)
> return ret;
>
> @@ -408,7 +409,7 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
> if (ret)
> return ret;
>
> - is3byte = (nor->bouncebuf[0] == nor->bouncebuf[1]);
> + is3byte = (nor->bouncebuf[0] == sr);
>
> op = (struct spi_mem_op)
> CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0,
> @@ -417,7 +418,7 @@ static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
> if (ret)
> return ret;
>
> - is4byte = (nor->bouncebuf[0] == nor->bouncebuf[1]);
> + is4byte = (nor->bouncebuf[0] == sr);
>
> if (is3byte == is4byte)
> return -EIO;
> @@ -1103,13 +1104,14 @@ static const struct flash_info spansion_nor_parts[] = {
> static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
> {
> int ret;
> + u8 sr;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1(nor, &sr);
> if (ret)
> return ret;
>
> - if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
> - if (nor->bouncebuf[0] & SR_E_ERR)
> + if (sr & (SR_E_ERR | SR_P_ERR)) {
> + if (sr & SR_E_ERR)
> dev_err(nor->dev, "Erase Error occurred\n");
> else
> dev_err(nor->dev, "Programming Error occurred\n");
> @@ -1129,7 +1131,7 @@ static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
> return -EIO;
> }
>
> - return !(nor->bouncebuf[0] & SR_WIP);
> + return !(sr & SR_WIP);
> }
>
> static int spansion_nor_late_init(struct spi_nor *nor)
> diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
> index db02c14ba16f..77a0bc41d4e5 100644
> --- a/drivers/mtd/spi-nor/sst.c
> +++ b/drivers/mtd/spi-nor/sst.c
> @@ -21,16 +21,17 @@ static int sst26vf_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len)
> static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
> {
> int ret;
> + u8 cr;
>
> /* We only support unlocking the entire flash array. */
> if (ofs != 0 || len != nor->params->size)
> return -EINVAL;
>
> - ret = spi_nor_read_cr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr2(nor, &cr);
> if (ret)
> return ret;
>
> - if (!(nor->bouncebuf[0] & SST26VF_CR_BPNV)) {
> + if (!(cr & SST26VF_CR_BPNV)) {
> dev_dbg(nor->dev, "Any block has been permanently locked\n");
> return -EINVAL;
> }
> diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c
> index 235070b215d1..b7b291e15917 100644
> --- a/drivers/mtd/spi-nor/swp.c
> +++ b/drivers/mtd/spi-nor/swp.c
> @@ -36,7 +36,7 @@ static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor)
>
> static u8 spi_nor_get_sr_cmp_mask(struct spi_nor *nor)
> {
> - if (!(nor->flags & SNOR_F_NO_READ_CR) &&
> + if (nor->params->opcodes.read_sr2 &&
> nor->flags & SNOR_F_HAS_SR2_CMP_BIT6)
> return SR2_CMP_BIT6;
> else
> @@ -207,17 +207,9 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u8 *sr)
>
>
> if (!sr) {
> - if (spi_nor_read_sr(nor, nor->bouncebuf))
> + if (spi_nor_read_sr1_and_sr2(nor, sr_cr))
> return;
>
> - sr_cr[0] = nor->bouncebuf[0];
> -
> - if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> - if (spi_nor_read_cr(nor, nor->bouncebuf))
> - return;
> - }
> -
> - sr_cr[1] = nor->bouncebuf[0];
> sr = sr_cr;
> }
>
> @@ -273,20 +265,10 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)
> int ret;
> u8 pow;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1_and_sr2(nor, status_old);
> if (ret)
> return ret;
>
> - status_old[0] = nor->bouncebuf[0];
> -
> - if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> - ret = spi_nor_read_cr(nor, nor->bouncebuf);
> - if (ret)
> - return ret;
> -
> - status_old[1] = nor->bouncebuf[0];
> - }
> -
> /* If nothing in our range is unlocked, we don't need to do anything */
> if (spi_nor_is_locked_sr(nor, ofs, len, status_old))
> return 0;
> @@ -378,10 +360,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)
> (ofs_old < ofs_new || (ofs_new + len_new) < (ofs_old + len_old)))
> return -EINVAL;
>
> - if (nor->flags & SNOR_F_NO_READ_CR)
> - ret = spi_nor_write_sr_and_check(nor, best_status_new[0]);
> - else
> - ret = spi_nor_write_sr_cr_and_check(nor, best_status_new);
> + ret = spi_nor_write_sr1_and_sr2_and_check(nor, best_status_new);
> if (ret)
> return ret;
>
> @@ -409,20 +388,10 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
> int ret;
> u8 pow;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1_and_sr2(nor, status_old);
> if (ret)
> return ret;
>
> - status_old[0] = nor->bouncebuf[0];
> -
> - if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> - ret = spi_nor_read_cr(nor, nor->bouncebuf);
> - if (ret)
> - return ret;
> -
> - status_old[1] = nor->bouncebuf[0];
> - }
> -
> /* If nothing in our range is locked, we don't need to do anything */
> if (spi_nor_is_unlocked_sr(nor, ofs, len, status_old))
> return 0;
> @@ -512,10 +481,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)
> (ofs_new < ofs_old || (ofs_old + len_old) < (ofs_new + len_new)))
> return -EINVAL;
>
> - if (nor->flags & SNOR_F_NO_READ_CR)
> - ret = spi_nor_write_sr_and_check(nor, best_status_new[0]);
> - else
> - ret = spi_nor_write_sr_cr_and_check(nor, best_status_new);
> + ret = spi_nor_write_sr1_and_sr2_and_check(nor, best_status_new);
> if (ret)
> return ret;
>
> @@ -536,20 +502,10 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, u64 len)
> u8 sr_cr[2] = {};
> int ret;
>
> - ret = spi_nor_read_sr(nor, nor->bouncebuf);
> + ret = spi_nor_read_sr1_and_sr2(nor, sr_cr);
> if (ret)
> return ret;
>
> - sr_cr[0] = nor->bouncebuf[0];
> -
> - if (!(nor->flags & SNOR_F_NO_READ_CR)) {
> - ret = spi_nor_read_cr(nor, nor->bouncebuf);
> - if (ret)
> - return ret;
> -
> - sr_cr[1] = nor->bouncebuf[0];
> - }
> -
> return spi_nor_is_locked_sr(nor, ofs, len, sr_cr);
> }
>
> diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c
> index 593429bd6cdf..01a693033448 100644
> --- a/drivers/mtd/spi-nor/winbond.c
> +++ b/drivers/mtd/spi-nor/winbond.c
> @@ -520,12 +520,12 @@ static int winbond_nor_late_init(struct spi_nor *nor)
> * been to declare CR reads as unsupported, whereas the Jedec
> * specification doesn't clearly state that. In practice, all these
> * chips do support reading back the CR, which is needed for SWP support,
> - * so make sure that capability remains enabled (needed for SWP).
> + * so make sure that capability remains enabled.
> * In practice, only exclude the old W25X family (JEDEC ID: EF 30 xx)
> * which actually does not support this feature.
> */
> if (nor->id[1] > 0x30)
> - nor->flags &= ~SNOR_F_NO_READ_CR;
> + params->opcodes.read_sr2 = SPINOR_OP_RDCR;
>
> /*
> * Winbond has reused many IDs, up to four times at this
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 4b92494827b1..f0b5a1989881 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -113,20 +113,16 @@
> #define SR_E_ERR BIT(5)
> #define SR_P_ERR BIT(6)
>
> -#define SR1_QUAD_EN_BIT6 BIT(6)
> -
> #define SR_BP_SHIFT 2
>
> /* Enhanced Volatile Configuration Register bits */
> #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
>
> /* Status Register 2 bits. */
> -#define SR2_QUAD_EN_BIT1 BIT(1)
> #define SR2_LB1 BIT(3) /* Security Register Lock Bit 1 */
> #define SR2_LB2 BIT(4) /* Security Register Lock Bit 2 */
> #define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */
> #define SR2_CMP_BIT6 BIT(6)
> -#define SR2_QUAD_EN_BIT7 BIT(7)
>
> /* Supported SPI protocols */
> #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
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______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 04/23] mtd: spi-nor: Add support for the new JESD216 rev F QER field
2026-08-13 15:19 ` Miquel Raynal
@ 2026-08-14 12:26 ` Michael Walle
-1 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 12:26 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1: Type: text/plain, Size: 667 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> Revision F of the JEDEC JESD216 standard includes yet another
> supported setting in the QER 3-bit bitfield: 110b.
>
> This setting implies that the QE bit is bit 1 of SR2 (which is an
> already supported case) but this time it makes it very clear that both
> reading and writing to SR2 is supported, but not with the usual
> opcodes. The write operation uses an alternate WRSR2 opcode:
> 0x31 (instead of 0x3E) and both the reads and writes manipulate a single
> register at a time.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
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^ permalink raw reply [flat|nested] 92+ messages in thread
* Re: [PATCH v3 04/23] mtd: spi-nor: Add support for the new JESD216 rev F QER field
@ 2026-08-14 12:26 ` Michael Walle
0 siblings, 0 replies; 92+ messages in thread
From: Michael Walle @ 2026-08-14 12:26 UTC (permalink / raw)
To: Miquel Raynal, Pratyush Yadav, Takahiro Kuwano,
Richard Weinberger, Vignesh Raghavendra, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Jonathan Corbet, Shuah Khan
Cc: Steam Lin, Hsin-Yi Wang, Thomas Petazzoni, linux-mtd,
linux-arm-kernel, linux-kernel, linux-doc
[-- Attachment #1.1: Type: text/plain, Size: 667 bytes --]
On Thu Aug 13, 2026 at 5:19 PM CEST, Miquel Raynal wrote:
> Revision F of the JEDEC JESD216 standard includes yet another
> supported setting in the QER 3-bit bitfield: 110b.
>
> This setting implies that the QE bit is bit 1 of SR2 (which is an
> already supported case) but this time it makes it very clear that both
> reading and writing to SR2 is supported, but not with the usual
> opcodes. The write operation uses an alternate WRSR2 opcode:
> 0x31 (instead of 0x3E) and both the reads and writes manipulate a single
> register at a time.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Michael Walle <mwalle@kernel.org>
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______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 92+ messages in thread
end of thread, other threads:[~2026-08-14 12:26 UTC | newest]
Thread overview: 92+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-13 15:19 [PATCH v3 00/23] mtd: spi-nor: QE handling cleanup + fixup reworks + Winbond RV chips addition Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-13 15:19 ` [PATCH v3 01/23] mtd: spi-nor: Rename BFPT_DWORD15_QER_SR2_BIT1_BUGGY Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 7:30 ` Michael Walle
2026-08-14 7:30 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 02/23] mtd: spi-nor: Create a structure containing the flash opcodes Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 7:31 ` Michael Walle
2026-08-14 7:31 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 03/23] mtd: spi-nor: Refactor Read Status/Write Status support Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 12:25 ` Michael Walle
2026-08-14 12:25 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 04/23] mtd: spi-nor: Add support for the new JESD216 rev F QER field Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 12:26 ` Michael Walle
2026-08-14 12:26 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 05/23] mtd: spi-nor: Create the concept of fixup table with match function Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:40 ` Michael Walle
2026-08-14 9:40 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 06/23] mtd: spi-nor: Create an indirection on the part name Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:41 ` Michael Walle
2026-08-14 9:41 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 07/23] mtd: spi-nor: Move the SFDP header structure to a C header Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:41 ` Michael Walle
2026-08-14 9:41 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 08/23] mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-Q/N parts Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:46 ` Michael Walle
2026-08-14 9:46 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 09/23] mtd: spi-nor: winbond: Add support for W25Q32RV-Q/N Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:46 ` Michael Walle
2026-08-14 9:46 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 10/23] mtd: spi-nor: winbond: Add support for W25Q64RV-Q/N Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:46 ` Michael Walle
2026-08-14 9:46 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 11/23] mtd: spi-nor: winbond: Add support for W25Q12RV-Q/N Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:47 ` Michael Walle
2026-08-14 9:47 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 12/23] mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:47 ` Michael Walle
2026-08-14 9:47 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 13/23] mtd: spi-nor: winbond: Add support for W25Q01RV-Q/N Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:47 ` Michael Walle
2026-08-14 9:47 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 14/23] mtd: spi-nor: winbond: Add support for W25Q02RV-Q/N Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:48 ` Michael Walle
2026-08-14 9:48 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 15/23] mtd: spi-nor: winbond: Prepare introduction of W25QxxRV-M parts Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:50 ` Michael Walle
2026-08-14 9:50 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 16/23] mtd: spi-nor: winbond: Add support for W25Q32RV-M Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:50 ` Michael Walle
2026-08-14 9:50 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 17/23] mtd: spi-nor: winbond: Add support for W25Q64RV-M Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:51 ` Michael Walle
2026-08-14 9:51 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 18/23] mtd: spi-nor: winbond: Add support for W25Q12RV-M Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:51 ` Michael Walle
2026-08-14 9:51 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 19/23] mtd: spi-nor: winbond: Add support for W25Q51RV-M Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:52 ` Michael Walle
2026-08-14 9:52 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 20/23] mtd: spi-nor: winbond: Add support for W25Q01RV-M Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:52 ` Michael Walle
2026-08-14 9:52 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 21/23] mtd: spi-nor: winbond: Add support for W25Q02RV-M Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:52 ` Michael Walle
2026-08-14 9:52 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 22/23] mtd: spi-nor: winbond: Add support for W25Q51RV-Q/N/M Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
2026-08-14 9:53 ` Michael Walle
2026-08-14 9:53 ` Michael Walle
2026-08-13 15:19 ` [PATCH v3 23/23] mtd: spi-nor: debugfs: Expose SR opcodes and QE mask Miquel Raynal
2026-08-13 15:19 ` Miquel Raynal
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