[PATCH v4 0/4] drm/tyr: GPU reset infrastructure

[PATCH v4 0/4] drm/tyr: GPU reset infrastructure

[Onur Özkan]

Add support for scheduling GPU resets on a dedicated workqueue. Track
the reset state to avoid queueing another reset while one is already
pending or in progress.

Use an SRCU based gate with mutex-protected reader admission to block
hardware accesses while reset work runs and wait for current users
before resetting.

Stop new reset requests during teardown and drain any queued or running
reset work before releasing the device resources.

This is the initial reset infrastructure only. It is not wired to a reset
source yet as those will follow in separate work.

Based on 'commit 53441a9cae3c ("drm/tyr: program CSF global interface")'
from tyr-for-upstream with the following patch series on the ML:
  - rust: workqueue: add cancel_sync support [1]
  - rust: add SRCU abstraction [2]
  - rust: workqueue: add ScopedQueue for lifetime bound items [3]
  - Creation of workqueues in Rust [4]

TODOs:
  - On reset failure, we don't do anything for now. We should unplug
	  the GPU (that's what Panthor does) but we don't have the infrastructure
    for that yet [5].
  - In schedule(), similar to panthor_device_schedule_reset(), we should
  	have a PM check but similar to the note above, we don't have the
    infrastructure for that yet.

Changes since v4:
  - Moved iomem behind the HwGate.
  - Renamed the guard names in hw_gate (after the iomem patch, I realized
    the old names were confusing).

Changes since v3:
  - Dropped Resettable, ActiveHwState, pre/post-reset hooks and typestate.
  - Removed ResetState::Enqueueing and teardown spinning.
  - Replaced fail-fast try_access() and epoch tracking with a blocking
    hardware-access gate.
  - Used b4 for the prerequisites.

Changes since v2:
  - Replaced Work::disable_sync with Work::cancel_sync.
  - Used type state pattern for reset stages.
  - Using ScopedQueue with device lifetime instead of a static workqueue.
  - Removed SRCU patch from this series.

Changes since v1:
  - Removed OrderedQueue and using Alice's workqueue implementation [1]
    instead.
  - Added Resettable trait with pre_reset and post_reset hooks to be
    implemented by reset-managed hardwares.
  - Added SRCU abstraction and used it to synchronize the reset work and
    hardware access.

v1: https://lore.kernel.org/rust-for-linux/20260313091646.16938-1-work@onurozkan.dev
v2: https://lore.kernel.org/rust-for-linux/20260416171728.205141-1-work@onurozkan.dev
v3: https://lore.kernel.org/all/20260708114358.957305-1-work@onurozkan.dev
v4: https://lore.kernel.org/all/20260813-tyr-reset-impl-v4-0-b36fcd0805b2@onurozkan.dev

Link: https://lore.kernel.org/all/20260617131731.145337-1-work@onurozkan.dev [1]
Link: https://lore.kernel.org/all/20260613065348.96750-1-work@onurozkan.dev [2]
Link: https://lore.kernel.org/all/20260617144645.253444-1-work@onurozkan.dev [3]
Link: https://lore.kernel.org/all/20260312-create-workqueue-v4-0-ea39c351c38f@google.com [4]
Link: https://gitlab.freedesktop.org/panfrost/linux/-/work_items/29#note_3391826 [5]
Link: https://gitlab.freedesktop.org/panfrost/linux/-/issues/28
Signed-off-by: Onur Özkan <work@onurozkan.dev>
---
Onur Özkan (4):
      rust: workqueue: impl Send and Sync for OwnedQueue
      drm/tyr: clear stale IRQ state before soft reset
      drm/tyr: add GPU reset infrastructure
      drm/tyr: put iomem behind the hardware gate

 drivers/gpu/drm/tyr/driver.rs            |  61 +++-----
 drivers/gpu/drm/tyr/fw.rs                |  16 +-
 drivers/gpu/drm/tyr/mmu.rs               |   9 +-
 drivers/gpu/drm/tyr/mmu/address_space.rs |  49 +++---
 drivers/gpu/drm/tyr/reset.rs             | 252 +++++++++++++++++++++++++++++++
 drivers/gpu/drm/tyr/reset/hw_gate.rs     | 102 +++++++++++++
 drivers/gpu/drm/tyr/tyr.rs               |   1 +
 rust/kernel/workqueue/mod.rs             |   8 +
 8 files changed, 421 insertions(+), 77 deletions(-)
---
base-commit: 53441a9cae3c4be552fa8aefa6e61b0f1bceb8a5
change-id: 20260813-tyr-reset-impl-93e951f996b4
prerequisite-message-id: <20260312-create-workqueue-v4-0-ea39c351c38f@google.com>
prerequisite-patch-id: f5e24f7b3717f2ab0445b5395c7f12b554861d78
prerequisite-patch-id: 0bf6ae4abcef7090d0e48921d6ec627a59dc6a7a
prerequisite-patch-id: f2bd17b7ba9f4626ddec56fec8e108872ddc6af1
prerequisite-message-id: <20260617144645.253444-1-work@onurozkan.dev>
prerequisite-patch-id: 5b966d09cfd455dd09fb0911d174b123efa02a16
prerequisite-message-id: <20260613065348.96750-1-work@onurozkan.dev>
prerequisite-patch-id: 9e1efee190d212ba1b01cd0acb5a4357e0b4da42
prerequisite-patch-id: 26aba035f4d1e212fa6ea7078095febefff5c5ba
prerequisite-patch-id: ffa25d5aadec4c04589af2bdd59a9c022f0fc9b0
prerequisite-patch-id: c2e05a4ac9d665d331952b291a622df6be673e41
prerequisite-patch-id: c14a4bd8a68b045356d61f7fa94690bd037ad08b
prerequisite-message-id: <20260617131731.145337-1-work@onurozkan.dev>
prerequisite-patch-id: b40e7a218c4e0467933e83c45b09eb78c7ebace2

[PATCH v4 1/4] rust: workqueue: impl Send and Sync for OwnedQueue

[Onur Özkan]

Allows OwnedQueue to be used across thread boundaries which is needed
from the tyr reset implementation.

Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Signed-off-by: Onur Özkan <work@onurozkan.dev>
---
 rust/kernel/workqueue/mod.rs | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/rust/kernel/workqueue/mod.rs b/rust/kernel/workqueue/mod.rs
index 933032fc4a85..d766cd9b9175 100644
--- a/rust/kernel/workqueue/mod.rs
+++ b/rust/kernel/workqueue/mod.rs
@@ -383,6 +383,14 @@ pub struct OwnedQueue {
     queue: NonNull<Queue>,
 }
 
+// SAFETY: `OwnedQueue` has exclusive ownership of the workqueue and accesses to workqueues
+// are thread safe as documented by the `Send` implementation for `Queue`.
+unsafe impl Send for OwnedQueue {}
+
+// SAFETY: Shared access to an `OwnedQueue` only provides shared access to its `Queue` which
+// is thread safe as documented by the `Sync` implementation for `Queue`.
+unsafe impl Sync for OwnedQueue {}
+
 impl Deref for OwnedQueue {
     type Target = Queue;
     fn deref(&self) -> &Queue {

-- 
2.51.2

[PATCH v4 2/4] drm/tyr: clear stale IRQ state before soft reset

[Onur Özkan]

Previous reset may leave the reset completed IRQ set which can make the
poll return too early.

Clear the IRQ first so the driver waits for the current reset to
complete.

Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Onur Özkan <work@onurozkan.dev>
---
 drivers/gpu/drm/tyr/driver.rs | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver.rs
index c5063b2be94d..90d6cd988cd2 100644
--- a/drivers/gpu/drm/tyr/driver.rs
+++ b/drivers/gpu/drm/tyr/driver.rs
@@ -86,6 +86,9 @@ pub(crate) struct TyrDrmRegistrationData<'bound> {
 }
 
 fn issue_soft_reset(dev: &Device, iomem: &IoMem<'_>) -> Result {
+    // Clear any stale reset IRQ state before issuing a new soft reset.
+    iomem.write_reg(GPU_IRQ_CLEAR::zeroed().with_reset_completed(true));
+
     iomem.write_reg(GPU_COMMAND::reset(ResetMode::SoftReset));
 
     poll::read_poll_timeout(

-- 
2.51.2

[PATCH v4 3/4] drm/tyr: add GPU reset infrastructure

[Onur Özkan]

Add support for scheduling GPU resets on a dedicated workqueue. Track
the reset state to avoid queueing another reset while one is already
pending or in progress.

Use an SRCU based gate with mutex-protected reader admission to block
hardware accesses while reset work runs and wait for current users
before resetting.

Stop new reset requests during teardown and drain any queued or running
reset work before releasing the device resources.

This is the initial reset infrastructure only. It is not wired to a reset
source yet as those will follow in separate work.

Link: https://gitlab.freedesktop.org/panfrost/linux/-/work_items/28
Signed-off-by: Onur Özkan <work@onurozkan.dev>
---
 drivers/gpu/drm/tyr/driver.rs        |  42 ++----
 drivers/gpu/drm/tyr/reset.rs         | 260 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/tyr/reset/hw_gate.rs |  80 +++++++++++
 drivers/gpu/drm/tyr/tyr.rs           |   1 +
 4 files changed, 355 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver.rs
index 90d6cd988cd2..bd613ab7e05c 100644
--- a/drivers/gpu/drm/tyr/driver.rs
+++ b/drivers/gpu/drm/tyr/driver.rs
@@ -8,7 +8,6 @@
     device::{
         Bound,
         Core,
-        Device,
         DeviceContext, //
     },
     dma::{
@@ -17,13 +16,9 @@
     },
     drm,
     drm::ioctl,
-    io::{
-        poll,
-        Io, //
-    },
     new_mutex,
     of,
-    platform,
+    platform, //
     prelude::*,
     regulator,
     regulator::Regulator,
@@ -33,7 +28,6 @@
         Arc,
         Mutex, //
     },
-    time,
     types::ForLt, //
 };
 
@@ -41,10 +35,10 @@
     file::TyrDrmFileData,
     fw::Firmware,
     gem::BoData,
-    gpu,
     gpu::GpuInfo,
     mmu::Mmu,
-    regs::gpu_control::*, //
+    regs::gpu_control::*,
+    reset, //
 };
 
 pub(crate) type IoMem<'a> = kernel::io::mem::IoMem<'a, SZ_2M>;
@@ -67,6 +61,11 @@ pub(crate) struct TyrDrmRegistrationData<'bound> {
     /// Parent platform device.
     pub(crate) pdev: &'bound platform::Device<Bound>,
 
+    // `ResetHandle::drop()` drains queued/running works and this must happen
+    // before clocks/regulators are dropped. So keep this field before them to
+    // ensure the correct drop order.
+    pub(crate) reset: reset::ResetHandle<'bound>,
+
     /// Firmware sections.
     pub(crate) fw: Arc<Firmware<'bound>>,
 
@@ -85,23 +84,6 @@ pub(crate) struct TyrDrmRegistrationData<'bound> {
     pub(crate) gpu_info: GpuInfo,
 }
 
-fn issue_soft_reset(dev: &Device, iomem: &IoMem<'_>) -> Result {
-    // Clear any stale reset IRQ state before issuing a new soft reset.
-    iomem.write_reg(GPU_IRQ_CLEAR::zeroed().with_reset_completed(true));
-
-    iomem.write_reg(GPU_COMMAND::reset(ResetMode::SoftReset));
-
-    poll::read_poll_timeout(
-        || Ok(iomem.read(GPU_IRQ_RAWSTAT)),
-        |status| status.reset_completed(),
-        time::Delta::from_millis(1),
-        time::Delta::from_millis(100),
-    )
-    .inspect_err(|_| dev_err!(dev, "GPU reset failed."))?;
-
-    Ok(())
-}
-
 kernel::of_device_table!(
     OF_TABLE,
     MODULE_OF_TABLE,
@@ -136,8 +118,7 @@ fn probe<'bound>(
 
         let iomem = Arc::new(request.iomap_sized::<SZ_2M>()?, GFP_KERNEL)?;
 
-        issue_soft_reset(pdev.as_ref(), &iomem)?;
-        gpu::l2_power_on(pdev.as_ref(), &iomem)?;
+        reset::run_reset(pdev.as_ref(), &iomem)?;
 
         let gpu_info = GpuInfo::new(&iomem);
         gpu_info.log(pdev.as_ref());
@@ -152,6 +133,10 @@ fn probe<'bound>(
 
         let unreg_dev = drm::UnregisteredDevice::<TyrDrmDriver>::new(pdev, Ok(()))?;
 
+        // SAFETY: `ResetHandle` is stored in registration data created with `new_with_lt`
+        // and is dropped before the borrowed device and MMIO references expire.
+        let reset = unsafe { reset::ResetHandle::new(pdev, iomem.as_arc_borrow())? };
+
         let mmu = Mmu::new(iomem.as_arc_borrow(), &gpu_info)?;
 
         let firmware = Firmware::new(
@@ -167,6 +152,7 @@ fn probe<'bound>(
 
         let reg_data = try_pin_init!(TyrDrmRegistrationData {
                 pdev,
+                reset,
                 fw: firmware,
                 clks <- new_mutex!(Clocks {
                     core: core_clk,
diff --git a/drivers/gpu/drm/tyr/reset.rs b/drivers/gpu/drm/tyr/reset.rs
new file mode 100644
index 000000000000..a0eabf8ac6d0
--- /dev/null
+++ b/drivers/gpu/drm/tyr/reset.rs
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+
+//! Provides asynchronous reset handling for the Tyr DRM driver via [`ResetHandle`].
+//!
+//! [`ResetHandle::schedule`] runs reset work on a dedicated ordered
+//! [`ScopedQueue`] and avoids duplicate pending reset requests.
+//!
+//! # High-level Execution Flow
+//!
+//! ```text
+//! +------+  schedule()  +---------+  reset_work()  +------------+
+//! | Idle |------------->| Pending |--------------->| InProgress |
+//! +------+              +---------+                +------------+
+//!    ^                                             |
+//!    |               work complete                 |
+//!    +---------------------------------------------+
+//!
+//! Teardown transitions any state to ShuttingDown, then drains pending and
+//! running work.
+//! ```
+
+mod hw_gate;
+
+use hw_gate::HwGate;
+
+use kernel::{
+    device::{
+        Bound,
+        Device, //
+    },
+    io::{
+        poll,
+        Io, //
+    },
+    platform,
+    prelude::*,
+    sync::{
+        atomic::{
+            Atomic,
+            AtomicType,
+            Full,
+            Release, //
+        },
+        Arc,
+        ArcBorrow, //
+    },
+    time,
+    workqueue::{
+        self,
+        ScopedQueue,
+        Work, //
+    },
+};
+
+use crate::{
+    driver::IoMem,
+    gpu,
+    regs::gpu_control::*, //
+};
+
+/// Lifecycle state of the reset worker.
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(i32)]
+enum ResetState {
+    /// Hardware is available and no reset request exists.
+    Idle = 0,
+    /// Reset work item is queued and waiting to be claimed by the worker.
+    Pending = 1,
+    /// Worker has claimed the request and is resetting hardware.
+    InProgress = 2,
+    /// Teardown has started and no new reset request may start.
+    ShuttingDown = 3,
+}
+
+// SAFETY: `ResetState` and `i32` have the same size and alignment, and are
+// round-trip transmutable.
+unsafe impl AtomicType for ResetState {
+    type Repr = i32;
+}
+
+/// Internal reset orchestrator that owns the state, [`HwGate`], and work item.
+#[pin_data]
+struct Controller<'bound> {
+    /// Parent platform device.
+    pdev: &'bound platform::Device<Bound>,
+    /// Mapped register space needed for reset operations.
+    iomem: Arc<IoMem<'bound>>,
+    /// State shared by reset schedulers and the worker.
+    state: Atomic<ResetState>,
+    /// Drains reset-sensitive hardware accesses before a reset.
+    #[pin]
+    hw: HwGate,
+    /// Work item backing async reset processing.
+    #[pin]
+    work: Work<Controller<'bound>>,
+}
+
+kernel::impl_has_work! {
+    impl{'bound} HasWork<Controller<'bound>> for Controller<'bound> { self.work }
+}
+
+impl<'bound> workqueue::WorkItem for Controller<'bound> {
+    type Pointer = Arc<Self>;
+
+    fn run(this: Arc<Self>) {
+        this.reset_work();
+    }
+}
+
+impl<'bound> Controller<'bound> {
+    /// Creates an [`Arc<Controller>`] ready for use.
+    fn new(
+        pdev: &'bound platform::Device<Bound>,
+        iomem: ArcBorrow<'_, IoMem<'bound>>,
+    ) -> Result<Arc<Self>> {
+        Arc::pin_init(
+            try_pin_init!(Self {
+                pdev,
+                iomem: iomem.into(),
+                state: Atomic::new(ResetState::Idle),
+                hw <- HwGate::new(),
+                work <- kernel::new_work!("tyr::reset"),
+            }),
+            GFP_KERNEL,
+        )
+    }
+
+    /// Attempts to transition the reset state from `from` to `to`.
+    #[inline]
+    fn try_transition(&self, from: ResetState, to: ResetState) -> bool {
+        self.state.cmpxchg(from, to, Full).is_ok()
+    }
+
+    /// Processes one scheduled reset request.
+    ///
+    /// If the pending reset cannot be claimed, the worker returns immediately.
+    ///
+    /// It first claims [`ResetState::Pending`], then waits for earlier hardware
+    /// accesses to complete before issuing the reset and returning the worker
+    /// state to [`ResetState::Idle`].
+    ///
+    /// Panthor reference:
+    /// - drivers/gpu/drm/panthor/panthor_device.c::panthor_device_reset_work()
+    fn reset_work(self: &Arc<Self>) {
+        if !self.try_transition(ResetState::Pending, ResetState::InProgress) {
+            return;
+        }
+
+        dev_info!(self.pdev, "Starting GPU reset.\n");
+
+        // Wait for current hardware accesses to finish before resetting.
+        let reset_guard = self.hw.close();
+        let reset_result = run_reset(self.pdev.as_ref(), &self.iomem);
+        drop(reset_guard);
+
+        if let Err(e) = reset_result {
+            dev_err!(self.pdev, "GPU reset failed: {:?}\n", e);
+
+            // TODO: Unplug the GPU.
+            // There is no API for unplugging the GPU and this is unreachable
+            // for now since there are no hardware users for reset API.
+        } else {
+            dev_info!(self.pdev, "GPU reset completed.\n");
+        }
+
+        let _ = self.try_transition(ResetState::InProgress, ResetState::Idle);
+    }
+}
+
+/// User-facing handle for scheduling resets.
+///
+/// Dropping the handle drains any queued or in-flight reset work before the
+/// [`ScopedQueue`] and the clock and regulator resources are released.
+pub(crate) struct ResetHandle<'bound> {
+    controller: Arc<Controller<'bound>>,
+    wq: ScopedQueue<'bound>,
+}
+
+impl<'bound> ResetHandle<'bound> {
+    /// Creates [`ResetHandle`].
+    ///
+    /// # Safety
+    ///
+    /// The returned handle must not be leaked or otherwise prevented from
+    /// running [`Drop`], since it owns work that may borrow from `'bound`.
+    pub(crate) unsafe fn new(
+        pdev: &'bound platform::Device<Bound>,
+        iomem: ArcBorrow<'_, IoMem<'bound>>,
+    ) -> Result<Self> {
+        Ok(Self {
+            controller: Controller::new(pdev, iomem)?,
+            // SAFETY: The caller guarantees the handle is dropped.
+            wq: unsafe { ScopedQueue::new(c"tyr-reset-wq")? },
+        })
+    }
+
+    /// Schedules a GPU reset on the dedicated workqueue.
+    ///
+    /// If a reset is already pending or in progress the call is a no-op.
+    #[expect(dead_code)]
+    pub(crate) fn schedule(&self) {
+        // TODO: Similar to `panthor_device_schedule_reset()` in Panthor, add a
+        // power management check once Tyr supports it.
+
+        if self
+            .controller
+            .try_transition(ResetState::Idle, ResetState::Pending)
+        {
+            let _ = self.wq.enqueue(self.controller.clone());
+        }
+    }
+}
+
+impl<'bound> Drop for ResetHandle<'bound> {
+    fn drop(&mut self) {
+        // Stop new reset requests before draining queued/running work.
+        self.controller
+            .state
+            .store(ResetState::ShuttingDown, Release);
+
+        // Not required for safety because `wq` will drain on drop, but keep
+        // cancellation of `controller.work` explicit before fields are dropped.
+        let _ = self.controller.work.cancel_sync();
+    }
+}
+
+/// Issues a soft reset command and waits for reset-complete IRQ status.
+fn issue_soft_reset<'bound>(dev: &'bound Device<Bound>, io: &IoMem<'bound>) -> Result {
+    // Clear any stale reset-complete IRQ state before issuing a new soft reset.
+    io.write_reg(GPU_IRQ_CLEAR::zeroed().with_reset_completed(true));
+
+    io.write_reg(GPU_COMMAND::reset(ResetMode::SoftReset));
+
+    poll::read_poll_timeout(
+        || Ok(io.read(GPU_IRQ_RAWSTAT)),
+        |status| status.reset_completed(),
+        time::Delta::from_millis(1),
+        time::Delta::from_millis(100),
+    )
+    .inspect_err(|_| dev_err!(dev, "GPU reset timed out."))?;
+
+    Ok(())
+}
+
+/// Runs one synchronous GPU reset pass.
+///
+/// Its visibility is `pub(super)` only so the probe path can run an
+/// initial reset; it is not part of this module's public API.
+///
+/// On success, the GPU is left in a state suitable for reinitialization.
+///
+/// The sequence is as follows:
+///   - Trigger a GPU soft reset.
+///   - Wait for the reset-complete IRQ status.
+///   - Power L2 back on.
+pub(super) fn run_reset<'bound>(dev: &'bound Device<Bound>, iomem: &IoMem<'bound>) -> Result {
+    issue_soft_reset(dev, iomem)?;
+    gpu::l2_power_on(dev, iomem)?;
+    Ok(())
+}
diff --git a/drivers/gpu/drm/tyr/reset/hw_gate.rs b/drivers/gpu/drm/tyr/reset/hw_gate.rs
new file mode 100644
index 000000000000..54754f9fc05f
--- /dev/null
+++ b/drivers/gpu/drm/tyr/reset/hw_gate.rs
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+
+//! Hardware-access gate for the GPU reset cycle.
+//!
+//! [`HwGate`] uses a mutex and [`Srcu`] to coordinate reset-sensitive hardware
+//! access with reset. Readers hold the mutex while entering SRCU, then release
+//! it before accessing hardware. The reset worker holds the mutex while waiting
+//! for admitted readers and resetting hardware.
+
+use kernel::{
+    prelude::*,
+    sync::{
+        new_mutex,
+        srcu,
+        Mutex,
+        MutexGuard,
+        Srcu, //
+    },
+};
+
+/// Synchronizes GPU hardware access with reset.
+#[pin_data]
+pub(super) struct HwGate {
+    /// Admits readers and is held exclusively while the reset worker owns the
+    /// hardware.
+    #[pin]
+    gate_lock: Mutex<()>,
+    /// Drains readers that entered before the reset worker acquired `gate_lock`.
+    #[pin]
+    srcu: Srcu,
+}
+
+impl HwGate {
+    /// Creates an open hardware-access gate.
+    pub(super) fn new() -> impl PinInit<Self, Error> {
+        try_pin_init!(Self {
+            gate_lock <- new_mutex!(()),
+            srcu <- kernel::new_srcu!(),
+        })
+    }
+
+    /// Enters a reset-sensitive hardware-access section.
+    #[expect(dead_code)]
+    fn access(&self) -> HwAccessGuard<'_> {
+        let gate_lock = self.gate_lock.lock();
+        let srcu = self.srcu.read_lock();
+        drop(gate_lock);
+
+        HwAccessGuard { _srcu: srcu }
+    }
+
+    /// Stops new readers and drains admitted readers for the reset worker.
+    ///
+    /// Callers must serialize write-side access. The reset controller's state
+    /// machine provides that serialization.
+    pub(super) fn close(&self) -> HwClosedGuard<'_> {
+        let gate_lock = self.gate_lock.lock();
+
+        // Holding `gate_lock` prevents new readers from entering SRCU. Readers
+        // admitted before us are enrolled, so wait for their read-side work.
+        self.srcu.synchronize();
+
+        HwClosedGuard {
+            _gate_lock: gate_lock,
+        }
+    }
+}
+
+/// Shared hardware access that blocks reset until dropped.
+#[must_use = "the gate is released when the guard is dropped"]
+struct HwAccessGuard<'a> {
+    _srcu: srcu::Guard<'a>,
+}
+
+/// Exclusive hardware access for the reset worker that blocks new hardware
+/// accesses until dropped.
+#[must_use = "the gate stays closed until the guard is dropped"]
+pub(super) struct HwClosedGuard<'a> {
+    _gate_lock: MutexGuard<'a, ()>,
+}
diff --git a/drivers/gpu/drm/tyr/tyr.rs b/drivers/gpu/drm/tyr/tyr.rs
index 3f6fe5fbeb0f..63873628c843 100644
--- a/drivers/gpu/drm/tyr/tyr.rs
+++ b/drivers/gpu/drm/tyr/tyr.rs
@@ -14,6 +14,7 @@
 mod gpu;
 mod mmu;
 mod regs;
+mod reset;
 mod slot;
 mod vm;
 mod wait;

-- 
2.51.2

[PATCH v4 4/4] drm/tyr: put iomem behind the hardware gate

[Onur Özkan]

Move iomem mapping into HwGate and pass Arc<HwGate> to components that
access hardware. Callers obtain HwAccessGuard before accessing the iomem
so the reset worker waits for ongoing accesses.

Suggested-by: Daniel Almeida <daniel.almeida@collabora.com>
Signed-off-by: Onur Özkan <work@onurozkan.dev>
---
 drivers/gpu/drm/tyr/driver.rs            | 26 +++++++----------
 drivers/gpu/drm/tyr/fw.rs                | 16 ++++++-----
 drivers/gpu/drm/tyr/mmu.rs               |  9 ++----
 drivers/gpu/drm/tyr/mmu/address_space.rs | 49 ++++++++++++++++----------------
 drivers/gpu/drm/tyr/reset.rs             | 34 +++++++++-------------
 drivers/gpu/drm/tyr/reset/hw_gate.rs     | 40 ++++++++++++++++++++------
 6 files changed, 90 insertions(+), 84 deletions(-)

diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver.rs
index bd613ab7e05c..936624340edd 100644
--- a/drivers/gpu/drm/tyr/driver.rs
+++ b/drivers/gpu/drm/tyr/driver.rs
@@ -75,9 +75,6 @@ pub(crate) struct TyrDrmRegistrationData<'bound> {
     #[pin]
     regulators: Mutex<Regulators>,
 
-    /// GPU MMIO register mapping.
-    pub(crate) iomem: Arc<IoMem<'bound>>,
-
     /// Some information on the GPU.
     ///
     /// This is mainly queried by userspace, i.e.: Mesa.
@@ -116,11 +113,15 @@ fn probe<'bound>(
 
         let request = pdev.io_request_by_index(0).ok_or(ENODEV)?;
 
-        let iomem = Arc::new(request.iomap_sized::<SZ_2M>()?, GFP_KERNEL)?;
+        let hw = Arc::pin_init(
+            reset::HwGate::new(request.iomap_sized::<SZ_2M>()?),
+            GFP_KERNEL,
+        )?;
 
-        reset::run_reset(pdev.as_ref(), &iomem)?;
+        reset::run_reset(pdev.as_ref(), &hw)?;
 
-        let gpu_info = GpuInfo::new(&iomem);
+        let hw_guard = hw.access();
+        let gpu_info = GpuInfo::new(hw_guard.iomem());
         gpu_info.log(pdev.as_ref());
 
         let pa_bits = MMU_FEATURES::from_raw(gpu_info.mmu_features)
@@ -135,17 +136,11 @@ fn probe<'bound>(
 
         // SAFETY: `ResetHandle` is stored in registration data created with `new_with_lt`
         // and is dropped before the borrowed device and MMIO references expire.
-        let reset = unsafe { reset::ResetHandle::new(pdev, iomem.as_arc_borrow())? };
+        let reset = unsafe { reset::ResetHandle::new(pdev, hw.clone())? };
 
-        let mmu = Mmu::new(iomem.as_arc_borrow(), &gpu_info)?;
+        let mmu = Mmu::new(hw.clone(), &gpu_info)?;
 
-        let firmware = Firmware::new(
-            pdev,
-            iomem.clone(),
-            &unreg_dev,
-            mmu.as_arc_borrow(),
-            &gpu_info,
-        )?;
+        let firmware = Firmware::new(pdev, hw.clone(), &unreg_dev, mmu.as_arc_borrow(), &gpu_info)?;
 
         firmware.boot()?;
         firmware.enable_global_interface(&gpu_info, &core_clk)?;
@@ -163,7 +158,6 @@ fn probe<'bound>(
                     _mali: mali_regulator,
                     _sram: sram_regulator,
                 }),
-                iomem,
                 gpu_info,
         });
 
diff --git a/drivers/gpu/drm/tyr/fw.rs b/drivers/gpu/drm/tyr/fw.rs
index 651bbe77f10b..e1522ab14e8d 100644
--- a/drivers/gpu/drm/tyr/fw.rs
+++ b/drivers/gpu/drm/tyr/fw.rs
@@ -41,7 +41,6 @@
 
 use crate::{
     driver::{
-        IoMem,
         TyrDrmDevice, //
     },
     fw::{
@@ -65,6 +64,7 @@
         MCU_CONTROL,
         MCU_STATUS, //
     },
+    reset::HwGate,
     vm::Vm, //
 };
 
@@ -148,8 +148,8 @@ pub(crate) struct Firmware<'bound> {
     /// Platform device reference (needed to access the MCU JOB_IRQ registers).
     _pdev: ARef<platform::Device>,
 
-    /// Iomem need to access registers.
-    iomem: Arc<IoMem<'bound>>,
+    /// Shared gate that coordinates hardware access with GPU reset.
+    hw: Arc<HwGate<'bound>>,
 
     /// MCU VM.
     vm: Arc<Vm<'bound>>,
@@ -221,7 +221,7 @@ fn load(
     /// Load firmware and map sections into MCU VM.
     pub(crate) fn new(
         pdev: &'bound platform::Device<Bound>,
-        iomem: Arc<IoMem<'bound>>,
+        hw: Arc<HwGate<'bound>>,
         ddev: &TyrDrmDevice<Uninit>,
         mmu: ArcBorrow<'_, Mmu<'bound>>,
         gpu_info: &GpuInfo,
@@ -262,7 +262,7 @@ pub(crate) fn new(
         let firmware = Arc::pin_init(
             try_pin_init!(Firmware {
                 _pdev: pdev.into(),
-                iomem,
+                hw,
                 vm,
                 sections,
                 global_iface <- new_mutex!(GlobalInterface::new()?),
@@ -288,7 +288,8 @@ pub(crate) fn shared_section<'a>(&'a self) -> Result<&'a Section<'bound>> {
     }
 
     pub(crate) fn boot(&self) -> Result {
-        let io = &self.iomem;
+        let hw_guard = self.hw.access();
+        let io = hw_guard.iomem();
         io.write_reg(MCU_CONTROL::zeroed().with_req(McuControlMode::Auto));
 
         if let Err(e) = poll::read_poll_timeout(
@@ -307,8 +308,9 @@ pub(crate) fn boot(&self) -> Result {
     /// Enable the global interface.
     pub(crate) fn enable_global_interface(&self, gpu_info: &GpuInfo, core_clk: &Clk) -> Result {
         let shared_section = self.shared_section()?;
+        let hw_guard = self.hw.access();
         self.global_iface
             .lock()
-            .enable(&self.iomem, shared_section, gpu_info, core_clk)
+            .enable(hw_guard.iomem(), shared_section, gpu_info, core_clk)
     }
 }
diff --git a/drivers/gpu/drm/tyr/mmu.rs b/drivers/gpu/drm/tyr/mmu.rs
index cb5908c80e3d..8df6d2ef3c74 100644
--- a/drivers/gpu/drm/tyr/mmu.rs
+++ b/drivers/gpu/drm/tyr/mmu.rs
@@ -26,7 +26,6 @@
 };
 
 use crate::{
-    driver::IoMem,
     gpu::GpuInfo,
     mmu::address_space::{
         AddressSpaceManager,
@@ -36,6 +35,7 @@
         gpu_control::AS_PRESENT,
         MAX_AS, //
     },
+    reset::HwGate,
     slot::SlotManager, //
 };
 
@@ -67,14 +67,11 @@ pub(crate) struct Mmu<'bound> {
 
 impl<'bound> Mmu<'bound> {
     /// Create an MMU component for this device.
-    pub(crate) fn new(
-        iomem: ArcBorrow<'_, IoMem<'bound>>,
-        gpu_info: &GpuInfo,
-    ) -> Result<Arc<Mmu<'bound>>> {
+    pub(crate) fn new(hw: Arc<HwGate<'bound>>, gpu_info: &GpuInfo) -> Result<Arc<Mmu<'bound>>> {
         let present = AS_PRESENT::from_raw(gpu_info.as_present).present().get();
         let slot_count = present.count_ones().try_into()?;
 
-        let as_manager = AddressSpaceManager::new(iomem, present)?;
+        let as_manager = AddressSpaceManager::new(hw, present)?;
         let mmu_init = try_pin_init!(Self{
             as_manager <- new_mutex!(SlotManager::new(as_manager, slot_count)?),
         });
diff --git a/drivers/gpu/drm/tyr/mmu/address_space.rs b/drivers/gpu/drm/tyr/mmu/address_space.rs
index d5274220eb3c..7ce2902e6300 100644
--- a/drivers/gpu/drm/tyr/mmu/address_space.rs
+++ b/drivers/gpu/drm/tyr/mmu/address_space.rs
@@ -42,7 +42,6 @@
 };
 
 use crate::{
-    driver::IoMem,
     mmu::{
         AsSlotManager,
         Mmu, //
@@ -52,6 +51,7 @@
         mmu_control::mmu_as_control::*,
         MAX_AS, //
     },
+    reset::HwGate,
     slot::{
         Seat,
         SlotOperations, //
@@ -201,8 +201,8 @@ fn as_config(&self) -> Result<AddressSpaceConfig> {
 ///
 /// [`SlotOperations`]: crate::slot::SlotOperations
 pub(crate) struct AddressSpaceManager<'bound> {
-    /// Memory-mapped I/O region for GPU register access.
-    iomem: Arc<IoMem<'bound>>,
+    /// Shared gate that coordinates hardware access with GPU reset.
+    hw: Arc<HwGate<'bound>>,
 
     /// Bitmask of available address space slots from GPU_AS_PRESENT register.
     as_present: u32,
@@ -229,16 +229,13 @@ fn evict(&mut self, slot_idx: usize, _slot_data: &Self::SlotData) -> Result {
 impl<'bound> AddressSpaceManager<'bound> {
     /// Creates a new address space manager.
     ///
-    /// Initializes the manager with references to the platform device and
-    /// I/O memory region, along with the bitmask of available AS slots.
+    /// Initializes the manager with the hardware-access gate and the bitmask
+    /// of available AS slots.
     pub(super) fn new(
-        iomem: ArcBorrow<'_, IoMem<'bound>>,
+        hw: Arc<HwGate<'bound>>,
         as_present: u32,
     ) -> Result<AddressSpaceManager<'bound>> {
-        Ok(Self {
-            iomem: iomem.into(),
-            as_present,
-        })
+        Ok(Self { hw, as_present })
     }
 
     /// Validates that an AS slot number is within range and present in hardware.
@@ -269,7 +266,8 @@ fn validate_as_slot(&self, as_nr: usize) -> Result {
     ///
     /// Returns an error if polling times out after 10ms or if register access fails.
     fn as_wait_ready(&self, as_nr: usize) -> Result {
-        let io = &*self.iomem;
+        let hw_guard = self.hw.access();
+        let io = hw_guard.iomem();
         let op = || {
             let status_reg = STATUS::try_at(as_nr).ok_or(EINVAL)?;
             Ok(io.read(status_reg))
@@ -283,9 +281,10 @@ fn as_wait_ready(&self, as_nr: usize) -> Result {
     /// Sends a command to an AS slot.
     ///
     /// Returns an error if waiting for ready times out or if register write fails.
-    fn as_send_cmd(&mut self, as_nr: usize, cmd: MmuCommand) -> Result {
+    fn as_send_cmd(&self, as_nr: usize, cmd: MmuCommand) -> Result {
         self.as_wait_ready(as_nr)?;
-        let io = &*self.iomem;
+        let hw_guard = self.hw.access();
+        let io = hw_guard.iomem();
         let command_reg = COMMAND::try_at(as_nr).ok_or(EINVAL)?;
         io.write(command_reg, COMMAND::zeroed().with_command(cmd));
         Ok(())
@@ -294,7 +293,7 @@ fn as_send_cmd(&mut self, as_nr: usize, cmd: MmuCommand) -> Result {
     /// Sends a command to an AS slot and waits for completion.
     ///
     /// Returns an error if sending the command fails or if waiting for completion times out.
-    fn as_send_cmd_and_wait(&mut self, as_nr: usize, cmd: MmuCommand) -> Result {
+    fn as_send_cmd_and_wait(&self, as_nr: usize, cmd: MmuCommand) -> Result {
         self.as_send_cmd(as_nr, cmd)?;
         self.as_wait_ready(as_nr)?;
         Ok(())
@@ -303,10 +302,10 @@ fn as_send_cmd_and_wait(&mut self, as_nr: usize, cmd: MmuCommand) -> Result {
     /// Enables an AS slot with the provided configuration.
     ///
     /// Returns an error if the slot is invalid or if register writes/commands fail.
-    fn as_enable(&mut self, as_nr: usize, as_config: &AddressSpaceConfig) -> Result {
+    fn as_enable(&self, as_nr: usize, as_config: &AddressSpaceConfig) -> Result {
         self.validate_as_slot(as_nr)?;
-
-        let io = &*self.iomem;
+        let hw_guard = self.hw.access();
+        let io = hw_guard.iomem();
 
         let transtab = as_config.transtab;
         io.write(
@@ -346,14 +345,14 @@ fn as_enable(&mut self, as_nr: usize, as_config: &AddressSpaceConfig) -> Result
     /// Disables an AS slot and clears its configuration.
     ///
     /// Returns an error if the slot is invalid or if register writes/commands fail.
-    fn as_disable(&mut self, as_nr: usize) -> Result {
+    fn as_disable(&self, as_nr: usize) -> Result {
         self.validate_as_slot(as_nr)?;
+        let hw_guard = self.hw.access();
+        let io = hw_guard.iomem();
 
         // Flush AS before disabling
         self.as_send_cmd_and_wait(as_nr, MmuCommand::FlushMem)?;
 
-        let io = &*self.iomem;
-
         io.write(
             TRANSTAB_LO::try_at(as_nr).ok_or(EINVAL)?,
             TRANSTAB_LO::from_raw(0),
@@ -397,8 +396,10 @@ fn as_disable(&mut self, as_nr: usize) -> Result {
     /// power-of-two region aligned to its size.
     ///
     /// Returns an error if the slot is invalid or if register writes/commands fail.
-    fn as_start_update(&mut self, as_nr: usize, region: &Range<u64>) -> Result {
+    fn as_start_update(&self, as_nr: usize, region: &Range<u64>) -> Result {
         self.validate_as_slot(as_nr)?;
+        let hw_guard = self.hw.access();
+        let io = hw_guard.iomem();
 
         // The lock operates on full 64-byte cache lines of translation table entries.
         // Since each translation table entry (TTE) is 8 bytes, a cache line has 8 TTEs.
@@ -436,8 +437,6 @@ fn as_start_update(&mut self, as_nr: usize, region: &Range<u64>) -> Result {
         // because log2(32 KiB) = 15.
         let lockaddr_size = lock_region_log2 - 1;
 
-        let io = &*self.iomem;
-
         let lockaddr_val = LOCKADDR::zeroed()
             .try_with_size(lockaddr_size)?
             .try_with_base(lockaddr_base)?
@@ -458,7 +457,7 @@ fn as_start_update(&mut self, as_nr: usize, region: &Range<u64>) -> Result {
     /// Completes an atomic translation table update.
     ///
     /// Returns an error if the slot is invalid or if the flush command fails.
-    fn as_end_update(&mut self, as_nr: usize) -> Result {
+    fn as_end_update(&self, as_nr: usize) -> Result {
         self.validate_as_slot(as_nr)?;
         self.as_send_cmd_and_wait(as_nr, MmuCommand::FlushPt)?;
         Ok(())
@@ -467,7 +466,7 @@ fn as_end_update(&mut self, as_nr: usize) -> Result {
     /// Flushes the translation table cache for an AS slot.
     ///
     /// Returns an error if the slot is invalid or if the flush command fails.
-    fn as_flush(&mut self, as_nr: usize) -> Result {
+    fn as_flush(&self, as_nr: usize) -> Result {
         self.validate_as_slot(as_nr)?;
         self.as_send_cmd(as_nr, MmuCommand::FlushPt)
     }
diff --git a/drivers/gpu/drm/tyr/reset.rs b/drivers/gpu/drm/tyr/reset.rs
index a0eabf8ac6d0..69c1ea3d6abc 100644
--- a/drivers/gpu/drm/tyr/reset.rs
+++ b/drivers/gpu/drm/tyr/reset.rs
@@ -21,7 +21,7 @@
 
 mod hw_gate;
 
-use hw_gate::HwGate;
+pub(crate) use hw_gate::HwGate;
 
 use kernel::{
     device::{
@@ -41,8 +41,7 @@
             Full,
             Release, //
         },
-        Arc,
-        ArcBorrow, //
+        Arc, //
     },
     time,
     workqueue::{
@@ -83,13 +82,10 @@ unsafe impl AtomicType for ResetState {
 struct Controller<'bound> {
     /// Parent platform device.
     pdev: &'bound platform::Device<Bound>,
-    /// Mapped register space needed for reset operations.
-    iomem: Arc<IoMem<'bound>>,
     /// State shared by reset schedulers and the worker.
     state: Atomic<ResetState>,
-    /// Drains reset-sensitive hardware accesses before a reset.
-    #[pin]
-    hw: HwGate,
+    /// Shared gate that coordinates hardware access with GPU reset.
+    hw: Arc<HwGate<'bound>>,
     /// Work item backing async reset processing.
     #[pin]
     work: Work<Controller<'bound>>,
@@ -109,16 +105,12 @@ fn run(this: Arc<Self>) {
 
 impl<'bound> Controller<'bound> {
     /// Creates an [`Arc<Controller>`] ready for use.
-    fn new(
-        pdev: &'bound platform::Device<Bound>,
-        iomem: ArcBorrow<'_, IoMem<'bound>>,
-    ) -> Result<Arc<Self>> {
+    fn new(pdev: &'bound platform::Device<Bound>, hw: Arc<HwGate<'bound>>) -> Result<Arc<Self>> {
         Arc::pin_init(
             try_pin_init!(Self {
                 pdev,
-                iomem: iomem.into(),
                 state: Atomic::new(ResetState::Idle),
-                hw <- HwGate::new(),
+                hw,
                 work <- kernel::new_work!("tyr::reset"),
             }),
             GFP_KERNEL,
@@ -148,10 +140,7 @@ fn reset_work(self: &Arc<Self>) {
 
         dev_info!(self.pdev, "Starting GPU reset.\n");
 
-        // Wait for current hardware accesses to finish before resetting.
-        let reset_guard = self.hw.close();
-        let reset_result = run_reset(self.pdev.as_ref(), &self.iomem);
-        drop(reset_guard);
+        let reset_result = run_reset(self.pdev.as_ref(), &self.hw);
 
         if let Err(e) = reset_result {
             dev_err!(self.pdev, "GPU reset failed: {:?}\n", e);
@@ -185,10 +174,10 @@ impl<'bound> ResetHandle<'bound> {
     /// running [`Drop`], since it owns work that may borrow from `'bound`.
     pub(crate) unsafe fn new(
         pdev: &'bound platform::Device<Bound>,
-        iomem: ArcBorrow<'_, IoMem<'bound>>,
+        hw: Arc<HwGate<'bound>>,
     ) -> Result<Self> {
         Ok(Self {
-            controller: Controller::new(pdev, iomem)?,
+            controller: Controller::new(pdev, hw)?,
             // SAFETY: The caller guarantees the handle is dropped.
             wq: unsafe { ScopedQueue::new(c"tyr-reset-wq")? },
         })
@@ -253,7 +242,10 @@ fn issue_soft_reset<'bound>(dev: &'bound Device<Bound>, io: &IoMem<'bound>) -> R
 ///   - Trigger a GPU soft reset.
 ///   - Wait for the reset-complete IRQ status.
 ///   - Power L2 back on.
-pub(super) fn run_reset<'bound>(dev: &'bound Device<Bound>, iomem: &IoMem<'bound>) -> Result {
+pub(super) fn run_reset<'bound>(dev: &'bound Device<Bound>, hw: &HwGate<'bound>) -> Result {
+    let hw_guard = hw.close();
+    let iomem = hw_guard.iomem();
+
     issue_soft_reset(dev, iomem)?;
     gpu::l2_power_on(dev, iomem)?;
     Ok(())
diff --git a/drivers/gpu/drm/tyr/reset/hw_gate.rs b/drivers/gpu/drm/tyr/reset/hw_gate.rs
index 54754f9fc05f..e761a0b03661 100644
--- a/drivers/gpu/drm/tyr/reset/hw_gate.rs
+++ b/drivers/gpu/drm/tyr/reset/hw_gate.rs
@@ -18,9 +18,13 @@
     },
 };
 
+use crate::driver::IoMem;
+
 /// Synchronizes GPU hardware access with reset.
 #[pin_data]
-pub(super) struct HwGate {
+pub(crate) struct HwGate<'bound> {
+    /// GPU MMIO register mapping.
+    iomem: IoMem<'bound>,
     /// Admits readers and is held exclusively while the reset worker owns the
     /// hardware.
     #[pin]
@@ -30,30 +34,33 @@ pub(super) struct HwGate {
     srcu: Srcu,
 }
 
-impl HwGate {
+impl<'bound> HwGate<'bound> {
     /// Creates an open hardware-access gate.
-    pub(super) fn new() -> impl PinInit<Self, Error> {
+    pub(crate) fn new(iomem: IoMem<'bound>) -> impl PinInit<Self, Error> {
         try_pin_init!(Self {
+            iomem,
             gate_lock <- new_mutex!(()),
             srcu <- kernel::new_srcu!(),
         })
     }
 
     /// Enters a reset-sensitive hardware-access section.
-    #[expect(dead_code)]
-    fn access(&self) -> HwAccessGuard<'_> {
+    pub(crate) fn access(&self) -> HwAccessGuard<'_, 'bound> {
         let gate_lock = self.gate_lock.lock();
         let srcu = self.srcu.read_lock();
         drop(gate_lock);
 
-        HwAccessGuard { _srcu: srcu }
+        HwAccessGuard {
+            gate: self,
+            _srcu: srcu,
+        }
     }
 
     /// Stops new readers and drains admitted readers for the reset worker.
     ///
     /// Callers must serialize write-side access. The reset controller's state
     /// machine provides that serialization.
-    pub(super) fn close(&self) -> HwClosedGuard<'_> {
+    pub(super) fn close(&self) -> HwClosedGuard<'_, 'bound> {
         let gate_lock = self.gate_lock.lock();
 
         // Holding `gate_lock` prevents new readers from entering SRCU. Readers
@@ -61,6 +68,7 @@ pub(super) fn close(&self) -> HwClosedGuard<'_> {
         self.srcu.synchronize();
 
         HwClosedGuard {
+            gate: self,
             _gate_lock: gate_lock,
         }
     }
@@ -68,13 +76,27 @@ pub(super) fn close(&self) -> HwClosedGuard<'_> {
 
 /// Shared hardware access that blocks reset until dropped.
 #[must_use = "the gate is released when the guard is dropped"]
-struct HwAccessGuard<'a> {
+pub(crate) struct HwAccessGuard<'a, 'bound> {
+    gate: &'a HwGate<'bound>,
     _srcu: srcu::Guard<'a>,
 }
 
+impl<'a, 'bound> HwAccessGuard<'a, 'bound> {
+    pub(crate) fn iomem(&self) -> &IoMem<'bound> {
+        &self.gate.iomem
+    }
+}
+
 /// Exclusive hardware access for the reset worker that blocks new hardware
 /// accesses until dropped.
 #[must_use = "the gate stays closed until the guard is dropped"]
-pub(super) struct HwClosedGuard<'a> {
+pub(super) struct HwClosedGuard<'a, 'bound> {
+    gate: &'a HwGate<'bound>,
     _gate_lock: MutexGuard<'a, ()>,
 }
+
+impl<'a, 'bound> HwClosedGuard<'a, 'bound> {
+    pub(super) fn iomem(&self) -> &IoMem<'bound> {
+        &self.gate.iomem
+    }
+}

-- 
2.51.2

Re: [PATCH v4 0/4] drm/tyr: GPU reset infrastructure

[Onur Özkan]

On Sat, 15 Aug 2026 13:23:56 +0300
Onur Özkan <work@onurozkan.dev> wrote:

> Add support for scheduling GPU resets on a dedicated workqueue. Track
> the reset state to avoid queueing another reset while one is already
> pending or in progress.
> 
> Use an SRCU based gate with mutex-protected reader admission to block
> hardware accesses while reset work runs and wait for current users
> before resetting.
> 
> Stop new reset requests during teardown and drain any queued or running
> reset work before releasing the device resources.
> 
> This is the initial reset infrastructure only. It is not wired to a reset
> source yet as those will follow in separate work.
> 
> Based on 'commit 53441a9cae3c ("drm/tyr: program CSF global interface")'
> from tyr-for-upstream with the following patch series on the ML:
>   - rust: workqueue: add cancel_sync support [1]
>   - rust: add SRCU abstraction [2]
>   - rust: workqueue: add ScopedQueue for lifetime bound items [3]
>   - Creation of workqueues in Rust [4]
> 
> TODOs:
>   - On reset failure, we don't do anything for now. We should unplug
> 	  the GPU (that's what Panthor does) but we don't have the infrastructure
>     for that yet [5].
>   - In schedule(), similar to panthor_device_schedule_reset(), we should
>   	have a PM check but similar to the note above, we don't have the
>     infrastructure for that yet.
> 
> Changes since v4:
>   - Moved iomem behind the HwGate.
>   - Renamed the guard names in hw_gate (after the iomem patch, I realized
>     the old names were confusing).
> 
> Changes since v3:
>   - Dropped Resettable, ActiveHwState, pre/post-reset hooks and typestate.
>   - Removed ResetState::Enqueueing and teardown spinning.
>   - Replaced fail-fast try_access() and epoch tracking with a blocking
>     hardware-access gate.
>   - Used b4 for the prerequisites.
> 
> Changes since v2:
>   - Replaced Work::disable_sync with Work::cancel_sync.
>   - Used type state pattern for reset stages.
>   - Using ScopedQueue with device lifetime instead of a static workqueue.
>   - Removed SRCU patch from this series.
> 
> Changes since v1:
>   - Removed OrderedQueue and using Alice's workqueue implementation [1]
>     instead.
>   - Added Resettable trait with pre_reset and post_reset hooks to be
>     implemented by reset-managed hardwares.
>   - Added SRCU abstraction and used it to synchronize the reset work and
>     hardware access.
> 
> v1: https://lore.kernel.org/rust-for-linux/20260313091646.16938-1-work@onurozkan.dev
> v2: https://lore.kernel.org/rust-for-linux/20260416171728.205141-1-work@onurozkan.dev
> v3: https://lore.kernel.org/all/20260708114358.957305-1-work@onurozkan.dev
> v4: https://lore.kernel.org/all/20260813-tyr-reset-impl-v4-0-b36fcd0805b2@onurozkan.dev
> 
> Link: https://lore.kernel.org/all/20260617131731.145337-1-work@onurozkan.dev [1]
> Link: https://lore.kernel.org/all/20260613065348.96750-1-work@onurozkan.dev [2]
> Link: https://lore.kernel.org/all/20260617144645.253444-1-work@onurozkan.dev [3]
> Link: https://lore.kernel.org/all/20260312-create-workqueue-v4-0-ea39c351c38f@google.com [4]
> Link: https://gitlab.freedesktop.org/panfrost/linux/-/work_items/29#note_3391826 [5]
> Link: https://gitlab.freedesktop.org/panfrost/linux/-/issues/28
> Signed-off-by: Onur Özkan <work@onurozkan.dev>
> ---
> Onur Özkan (4):
>       rust: workqueue: impl Send and Sync for OwnedQueue
>       drm/tyr: clear stale IRQ state before soft reset
>       drm/tyr: add GPU reset infrastructure
>       drm/tyr: put iomem behind the hardware gate
> 
>  drivers/gpu/drm/tyr/driver.rs            |  61 +++-----
>  drivers/gpu/drm/tyr/fw.rs                |  16 +-
>  drivers/gpu/drm/tyr/mmu.rs               |   9 +-
>  drivers/gpu/drm/tyr/mmu/address_space.rs |  49 +++---
>  drivers/gpu/drm/tyr/reset.rs             | 252 +++++++++++++++++++++++++++++++
>  drivers/gpu/drm/tyr/reset/hw_gate.rs     | 102 +++++++++++++
>  drivers/gpu/drm/tyr/tyr.rs               |   1 +
>  rust/kernel/workqueue/mod.rs             |   8 +
>  8 files changed, 421 insertions(+), 77 deletions(-)
> ---
> base-commit: 53441a9cae3c4be552fa8aefa6e61b0f1bceb8a5
> change-id: 20260813-tyr-reset-impl-93e951f996b4
> prerequisite-message-id: <20260312-create-workqueue-v4-0-ea39c351c38f@google.com>
> prerequisite-patch-id: f5e24f7b3717f2ab0445b5395c7f12b554861d78
> prerequisite-patch-id: 0bf6ae4abcef7090d0e48921d6ec627a59dc6a7a
> prerequisite-patch-id: f2bd17b7ba9f4626ddec56fec8e108872ddc6af1
> prerequisite-message-id: <20260617144645.253444-1-work@onurozkan.dev>
> prerequisite-patch-id: 5b966d09cfd455dd09fb0911d174b123efa02a16
> prerequisite-message-id: <20260613065348.96750-1-work@onurozkan.dev>
> prerequisite-patch-id: 9e1efee190d212ba1b01cd0acb5a4357e0b4da42
> prerequisite-patch-id: 26aba035f4d1e212fa6ea7078095febefff5c5ba
> prerequisite-patch-id: ffa25d5aadec4c04589af2bdd59a9c022f0fc9b0
> prerequisite-patch-id: c2e05a4ac9d665d331952b291a622df6be673e41
> prerequisite-patch-id: c14a4bd8a68b045356d61f7fa94690bd037ad08b
> prerequisite-message-id: <20260617131731.145337-1-work@onurozkan.dev>
> prerequisite-patch-id: b40e7a218c4e0467933e83c45b09eb78c7ebace2
> 

The version prefix is wrong on this series. It's not V4; it's V5. I am
not sure if I should re-send the whole series with the correct prefix.

Sorry,
Onur

Re: [PATCH v4 3/4] drm/tyr: add GPU reset infrastructure

[Danilo Krummrich]

On Sat Aug 15, 2026 at 12:23 PM CEST, Onur Özkan wrote:
> +#[pin_data]
> +struct Controller<'bound> {

Please only use the lifetime name 'bound for bus device private data (which
defines the 'bound lifetime). Everything within is shorter lived and should
carry a different name (see also [1]).

I'd suggest 'ctrl or just 'a, once you have self-referencial fields 'ctrl (or
similar) is preferred.

[1] https://lore.kernel.org/all/DKAINVQDNE79.3JRKZDQJCSX9@kernel.org/

> +    fn reset_work(self: &Arc<Self>) {
> +        if !self.try_transition(ResetState::Pending, ResetState::InProgress) {
> +            return;
> +        }
> +
> +        dev_info!(self.pdev, "Starting GPU reset.\n");

Please use dev_dbg!().

> +        // Wait for current hardware accesses to finish before resetting.
> +        let reset_guard = self.hw.close();
> +        let reset_result = run_reset(self.pdev.as_ref(), &self.iomem);
> +        drop(reset_guard);
> +
> +        if let Err(e) = reset_result {
> +            dev_err!(self.pdev, "GPU reset failed: {:?}\n", e);
> +
> +            // TODO: Unplug the GPU.
> +            // There is no API for unplugging the GPU and this is unreachable
> +            // for now since there are no hardware users for reset API.
> +        } else {
> +            dev_info!(self.pdev, "GPU reset completed.\n");

Same here.

> +        }
> +
> +        let _ = self.try_transition(ResetState::InProgress, ResetState::Idle);
> +    }
> +}
> +
> +/// User-facing handle for scheduling resets.
> +///
> +/// Dropping the handle drains any queued or in-flight reset work before the
> +/// [`ScopedQueue`] and the clock and regulator resources are released.
> +pub(crate) struct ResetHandle<'bound> {

Same as above 'reset or just 'a.

> +    controller: Arc<Controller<'bound>>,

This can just be ScopedWork<Controller<'a>>; no extra reference count and
allocation needed, as the constructor gives you an impl PinInit.

It also gets you rid of the open-coded cancel_sync() call in the destructor of
ResetHandle.

Also note that [2] already has Send + Sync for OwnedQueue when OwnedQueue is
introduced, so you can drop patch 1 of this series.

Thanks,
Danilo

[2] https://lore.kernel.org/all/20260807165252.3849875-1-dakr@kernel.org/