Re: [PATCH 3/3] platform: generic: spacemit: k3: wake A100 core 8 for ESOS/RPMI services

From: "Troy Mitchell" <troy.mitchell@linux.spacemit.com>
To: "Valentin Haudiquet" <valentin.haudiquet@canonical.com>
Cc: <opensbi@lists.infradead.org>, <troy.mitchell@linux.spacemit.com>,
	"Xianbin Zhu" <xianbin.zhu@linux.spacemit.com>,
	"Anup Patel" <anup@brainfault.org>, "Bo Gan" <ganboing@gmail.com>,
	"Samuel Holland" <samuel.holland@sifive.com>,
	"Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>
Subject: Re: [PATCH 3/3] platform: generic: spacemit: k3: wake A100 core 8 for ESOS/RPMI services
Date: Tue, 01 Sep 2026 10:25:16 +0800	[thread overview]
Message-ID: <DL3MGIY12GHW.1W3S0MLQIOM5@linux.spacemit.com> (raw)
In-Reply-To: <20260831200832.404000-4-valentin.haudiquet@canonical.com>

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On Mon, Aug 31, 2026 at 10:07 PM +0200, Valentin Haudiquet wrote:
> The K3 SoC has two asymmetric CPU complexes: X100 (harts 0-7) and A100
> (harts 8-15).  ESOS -- the rcpu-side firmware already loaded in SPI NOR --
> runs on A100 core 8 and provides RPMI services (clock, voltage, device
> power, system reset, suspend) that the X100 side depends on during boot.
>
> Without waking core 8, all RPMI mailbox transactions time out and the
> system hangs early during Linux boot (at basic.target or
> cryptsetup.target, depending on which earlier fixes are present).

This does not match the SDK firmware layout. ESOS runs on the two RT24
RCPUs; the FIT contains rt24_os0_rcpu.elf and rt24_os1_rcpu.elf. A100
hart 8 is not the processor executing ESOS.

Please clarify what hardware dependency is satisfied by waking hart 8, and
provide the exact kernel, DTB, FSBL/U-Boot and ESOS versions used for the
test, along with the RPMI request that times out.

> +	/* Restore C2 RVBADDR to the normal warm-boot entry. */
> +	lla	t0, _spacemit_k3_warm_start
> +	li	t1, C2_RVBADDR_LO_ADDR
> +	sw	t0, 0(t1)
> +	li	t1, C2_RVBADDR_HI_ADDR
> +	srli	t0, t0, 32
> +	sw	t0, 0(t1)
> +
> +	/* Enter WFI until the HSM starts this hart. */
> +1:	wfi
> +	j	1b

The vendor OpenSBI path powers hart 8 back down and flushes and disables
its caches and snooping before entering WFI. This code instead leaves
hart 8 running in a private WFI loop. Reprogramming C2_RVBADDR does not
by itself transfer an already-running hart to _spacemit_k3_warm_start,
so a later HSM start is not guaranteed to work.

If this sequence is required by the SDK firmware ABI, it should be a
separate, DT-described compatibility path and must preserve the normal HSM
lifecycle.

                                            - Troy

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