From: "Trevor Gamblin" <tgamblin@baylibre.com>
To: "Wang Yechao" <wang.yechao255@zte.com.cn>,
<daniel.barboza@oss.qualcomm.com>, <richard.henderson@linaro.org>,
<tgamblin@baylibre.com>
Cc: <alistair.francis@wdc.com>, <chao.liu@processmission.com>,
<liwei1518@gmail.com>, <palmer@dabbelt.com>,
<qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>,
<zhiwei_liu@linux.alibaba.com>,
<qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org>
Subject: Re: [PATCH v2 0/2] target: riscv: support TLB page flush for sfence.vma
Date: Mon, 19 Oct 2026 13:14:23 -0400 [thread overview]
Message-ID: <DM8ZFFJKYUUD.1YC6LDKPIOGX5@baylibre.com> (raw)
In-Reply-To: <20261008070029.20239-1-wang.yechao255@zte.com.cn>
On Thu Oct 8, 2026 at 3:00 AM EDT, Wang Yechao wrote:
> Hi all,
>
> Patch 1 decides whether to use tlb_flush_page based on whether rs1
> is 0. This is similar to a patch I submitted last year [1]. Under
> normal circumstances this works fine, but it can leave stale TLB
> entries when the guest kernel uses THP.
>
> The reason is that with THP, the guest's mapping is at the PMD level.
> When flushing the TLB, the guest executes sfence.vma only once for the
> whole huge page, rather than 512 times to flush each individual 4K page.
> Patch 1 does not account for this: it only flushes the single 4K page
> corresponding to the address in rs1, leaving the other 511 pages of the
> huge page with stale entries. As a result, guest memory access faults
> can occur after Patch 1 is merged, unless huge-page TLB support is added
> for the RISC-V TCG case.
>
> Please correct me if I've misunderstood anything.
Hi,
Thanks for letting me know about this. I'm working on a local test setup to be
able to reproduce the problem, and I'll look into a more complete fix if so.
>
> [1] https://lore.kernel.org/qemu-devel/20250930174849833XG1Q1ETbNvg66WU2UVBTV@zte.com.cn/
>
> Yechao,
> Regards
prev parent reply other threads:[~2026-10-19 17:14 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 18:43 [PATCH v2 0/2] target: riscv: support TLB page flush for sfence.vma Trevor Gamblin
2026-09-04 18:43 ` [PATCH v2 1/2] target/riscv: extract check_sfence_vma() from helper_tlb_flush() Trevor Gamblin
2026-09-07 13:05 ` Daniel Henrique Barboza
2026-09-14 0:59 ` Richard Henderson
2026-10-01 5:13 ` Alistair Francis
2026-09-04 18:43 ` [PATCH v2 2/2] target/riscv: add helper_tlb_flush_page(), use for sfence.vma with vaddr operand Trevor Gamblin
2026-09-07 13:05 ` Daniel Henrique Barboza
2026-09-14 1:06 ` Richard Henderson
2026-09-14 1:17 ` Richard Henderson
2026-09-14 1:34 ` Richard Henderson
2026-10-01 5:14 ` Alistair Francis
2026-10-01 17:02 ` Trevor Gamblin
2026-09-07 13:14 ` [PATCH v2 0/2] target: riscv: support TLB page flush for sfence.vma Daniel Henrique Barboza
2026-09-14 1:14 ` Richard Henderson
2026-09-15 20:40 ` Daniel Henrique Barboza
2026-10-08 7:00 ` Wang Yechao
2026-10-19 17:14 ` Trevor Gamblin [this message]
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