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From: "Michael Walle" <mwalle@kernel.org>
To: "Changhuang Liang" <changhuang.liang@starfivetech.com>,
	"Pratyush Yadav" <pratyush@kernel.org>,
	"Takahiro Kuwano" <takahiro.kuwano@infineon.com>,
	"Mark Brown" <broonie@kernel.org>,
	"Miquel Raynal" <miquel.raynal@bootlin.com>,
	"Richard Weinberger" <richard@nod.at>,
	"Vignesh Raghavendra" <vigneshr@ti.com>
Cc: <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-mtd@lists.infradead.org>
Subject: Re: [PATCH v1 4/4] mtd: spi-nor: macronix: Add 1-4-4 DTR read support for MX66L1G45G
Date: Thu, 22 Oct 2026 14:23:26 +0200	[thread overview]
Message-ID: <DMBD4AK6UXKX.23K3797G1OUS0@kernel.org> (raw)
In-Reply-To: <20261022102614.75696-5-changhuang.liang@starfivetech.com>


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On Thu Oct 22, 2026 at 12:26 PM CEST, Changhuang Liang wrote:
> The MX66L1G45G supports the 1-4-4 DTR read mode. This flash uses 6
> dummy cycles by default in 1-4-4 DTR mode, but the kernel's SFDP
> parser does not derive any SNOR_HWCAPS_READ_1_4_4_DTR capability from
> the BFPT table

So why don't you fix that?

> , and 4BAIT only filters already-known capabilities.
> The exact number of dummy cycles is also not directly given in the
> SFDP tables.

What is BFPT 3rd DWORD bits 4:0 then?

Could you please dump the SFDP for this part? See [1].

-michael

[1] https://docs.kernel.org/6.2/driver-api/mtd/spi-nor.html

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______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: "Michael Walle" <mwalle@kernel.org>
To: "Changhuang Liang" <changhuang.liang@starfivetech.com>,
	"Pratyush Yadav" <pratyush@kernel.org>,
	"Takahiro Kuwano" <takahiro.kuwano@infineon.com>,
	"Mark Brown" <broonie@kernel.org>,
	"Miquel Raynal" <miquel.raynal@bootlin.com>,
	"Richard Weinberger" <richard@nod.at>,
	"Vignesh Raghavendra" <vigneshr@ti.com>
Cc: <linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-mtd@lists.infradead.org>
Subject: Re: [PATCH v1 4/4] mtd: spi-nor: macronix: Add 1-4-4 DTR read support for MX66L1G45G
Date: Thu, 22 Oct 2026 14:23:26 +0200	[thread overview]
Message-ID: <DMBD4AK6UXKX.23K3797G1OUS0@kernel.org> (raw)
In-Reply-To: <20261022102614.75696-5-changhuang.liang@starfivetech.com>

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On Thu Oct 22, 2026 at 12:26 PM CEST, Changhuang Liang wrote:
> The MX66L1G45G supports the 1-4-4 DTR read mode. This flash uses 6
> dummy cycles by default in 1-4-4 DTR mode, but the kernel's SFDP
> parser does not derive any SNOR_HWCAPS_READ_1_4_4_DTR capability from
> the BFPT table

So why don't you fix that?

> , and 4BAIT only filters already-known capabilities.
> The exact number of dummy cycles is also not directly given in the
> SFDP tables.

What is BFPT 3rd DWORD bits 4:0 then?

Could you please dump the SFDP for this part? See [1].

-michael

[1] https://docs.kernel.org/6.2/driver-api/mtd/spi-nor.html

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  parent reply	other threads:[~2026-10-22 12:23 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-22 10:26 [PATCH v1 0/4] Add DDR (Dual Data-Rate) support for DW SPI controller Changhuang Liang
2026-10-22 10:26 ` Changhuang Liang
2026-10-22 10:26 ` [PATCH v1 1/4] spi: dw: Add DDR (Dual Data-Rate) support for enhanced SPI mode Changhuang Liang
2026-10-22 10:26   ` Changhuang Liang
2026-10-22 10:41   ` Miquel Raynal
2026-10-22 10:41     ` Miquel Raynal
2026-10-23  9:42     ` Changhuang Liang
2026-10-23  9:42       ` Changhuang Liang
2026-10-23  9:52       ` Miquel Raynal
2026-10-23  9:52         ` Miquel Raynal
2026-10-23  9:54         ` Changhuang Liang
2026-10-23  9:54           ` Changhuang Liang
2026-10-22 10:48   ` sashiko-bot
2026-10-22 10:26 ` [PATCH v1 2/4] mtd: spi-nor: Support mixed 1S-xD-xD DTR protocols in spi_nor_spimem_setup_op() Changhuang Liang
2026-10-22 10:26   ` Changhuang Liang
2026-10-22 10:45   ` Miquel Raynal
2026-10-22 10:45     ` Miquel Raynal
2026-10-22 12:19     ` Michael Walle
2026-10-22 12:19       ` Michael Walle
2026-10-22 13:27       ` Miquel Raynal
2026-10-22 13:27         ` Miquel Raynal
2026-10-22 10:26 ` [PATCH v1 3/4] mtd: spi-nor: debugfs: Correct DTR protocol names for 1S-xD-xD modes Changhuang Liang
2026-10-22 10:26   ` Changhuang Liang
2026-10-22 10:46   ` Miquel Raynal
2026-10-22 10:46     ` Miquel Raynal
2026-10-22 10:26 ` [PATCH v1 4/4] mtd: spi-nor: macronix: Add 1-4-4 DTR read support for MX66L1G45G Changhuang Liang
2026-10-22 10:26   ` Changhuang Liang
2026-10-22 10:47   ` Miquel Raynal
2026-10-22 10:47     ` Miquel Raynal
2026-10-22 12:23   ` Michael Walle [this message]
2026-10-22 12:23     ` Michael Walle
2026-10-23 10:42     ` Changhuang Liang
2026-10-23 10:42       ` Changhuang Liang

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