From: "Troy Mitchell" <troy.mitchell@linux.dev>
To: "Thomas Gleixner" <tglx@kernel.org>,
"Troy Mitchell" <troy.mitchell@linux.dev>,
"Anup Patel" <anup@brainfault.org>,
"Radu Rendec" <radu@rendec.net>, "Paul Walmsley" <pjw@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Björn Töpel" <bjorn@rivosinc.com>
Cc: "Anup Patel" <apatel@ventanamicro.com>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/2] irqchip/riscv-aplic: Use handle_edge_irq() for edge-triggered MSI sources
Date: Wed, 11 Nov 2026 01:11:36 +0000 [thread overview]
Message-ID: <DMRZCSZ0W7NS.K8CUKB6WCX01@linux.dev> (raw)
In-Reply-To: <87ik24telo.ffs@fw13>
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Hi Thomas,
On Wed Nov 11, 2026 at 12:07 AM GMT, Thomas Gleixner wrote:
> On Tue, Nov 10 2026 at 12:06, Troy Mitchell wrote:
>> In MSI mode, all APLIC interrupts are handled by handle_fasteoi_irq().
>> For an edge-triggered source the APLIC forwards each edge as an MSI and
>> keeps no state after that, so an edge which the CPU side drops is lost.
>> After an affinity change, the next MSI can arrive on the new CPU while
>> the previous one is still being handled on the old CPU, and
>> handle_fasteoi_irq() then drops it.
>>
>> The fasteoi flow also never calls irq_ack(), which is where IMSIC applies
>> an affinity change that was deferred while a previous vector move was in
>> flight. Such a change stays pending, and later affinity changes of the
>> interrupt only update the pending mask.
>>
>> Use handle_edge_irq() for edge-triggered sources. It acknowledges the
>> interrupt before invoking the handler. If the interrupt is still in
>> progress on the previous target CPU, it either waits for it to complete
>> or marks it pending so that the handler runs again.
>>
>> Fixes: ca8df97fe679 ("irqchip/riscv-aplic: Add support for MSI-mode")
>> Signed-off-by: Troy Mitchell <troy.mitchell@linux.dev>
>
> Not that I care at all about showing up in some made up git-tag metrics,
> but in general it's a matter of courtesy to point out that the solution
> to the problem was suggested by someone else, no?
I'm so orry about that. Will add your Suggested-by in v3.
>
>> + /*
>> + * Edge-triggered sources are fire and forget, so they must be
>> + * acknowledged before the handler runs. The edge flow handler also
>> + * replays an interrupt which arrives while the previous one is
>> + * still being handled on another CPU after an affinity change.
>> + */
>> + if (type & IRQ_TYPE_EDGE_BOTH)
>> + irq_set_chip_handler_name_locked(d, irq_data_get_irq_chip(d),
>> + handle_edge_irq, "edge");
>> + else
>> + irq_set_chip_handler_name_locked(d, irq_data_get_irq_chip(d),
>> + handle_fasteoi_irq, "fasteoi");
>> +
>
> https://docs.kernel.org/process/maintainer-tip.html#bracket-rules
Will add the braces in v3. Thanks for your review!
--
Troy Mitchell
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WARNING: multiple messages have this Message-ID (diff)
From: "Troy Mitchell" <troy.mitchell@linux.dev>
To: "Thomas Gleixner" <tglx@kernel.org>,
"Troy Mitchell" <troy.mitchell@linux.dev>,
"Anup Patel" <anup@brainfault.org>,
"Radu Rendec" <radu@rendec.net>, "Paul Walmsley" <pjw@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Björn Töpel" <bjorn@rivosinc.com>
Cc: "Anup Patel" <apatel@ventanamicro.com>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/2] irqchip/riscv-aplic: Use handle_edge_irq() for edge-triggered MSI sources
Date: Wed, 11 Nov 2026 01:11:36 +0000 [thread overview]
Message-ID: <DMRZCSZ0W7NS.K8CUKB6WCX01@linux.dev> (raw)
In-Reply-To: <87ik24telo.ffs@fw13>
[-- Attachment #1.1: Type: text/plain, Size: 2235 bytes --]
Hi Thomas,
On Wed Nov 11, 2026 at 12:07 AM GMT, Thomas Gleixner wrote:
> On Tue, Nov 10 2026 at 12:06, Troy Mitchell wrote:
>> In MSI mode, all APLIC interrupts are handled by handle_fasteoi_irq().
>> For an edge-triggered source the APLIC forwards each edge as an MSI and
>> keeps no state after that, so an edge which the CPU side drops is lost.
>> After an affinity change, the next MSI can arrive on the new CPU while
>> the previous one is still being handled on the old CPU, and
>> handle_fasteoi_irq() then drops it.
>>
>> The fasteoi flow also never calls irq_ack(), which is where IMSIC applies
>> an affinity change that was deferred while a previous vector move was in
>> flight. Such a change stays pending, and later affinity changes of the
>> interrupt only update the pending mask.
>>
>> Use handle_edge_irq() for edge-triggered sources. It acknowledges the
>> interrupt before invoking the handler. If the interrupt is still in
>> progress on the previous target CPU, it either waits for it to complete
>> or marks it pending so that the handler runs again.
>>
>> Fixes: ca8df97fe679 ("irqchip/riscv-aplic: Add support for MSI-mode")
>> Signed-off-by: Troy Mitchell <troy.mitchell@linux.dev>
>
> Not that I care at all about showing up in some made up git-tag metrics,
> but in general it's a matter of courtesy to point out that the solution
> to the problem was suggested by someone else, no?
I'm so orry about that. Will add your Suggested-by in v3.
>
>> + /*
>> + * Edge-triggered sources are fire and forget, so they must be
>> + * acknowledged before the handler runs. The edge flow handler also
>> + * replays an interrupt which arrives while the previous one is
>> + * still being handled on another CPU after an affinity change.
>> + */
>> + if (type & IRQ_TYPE_EDGE_BOTH)
>> + irq_set_chip_handler_name_locked(d, irq_data_get_irq_chip(d),
>> + handle_edge_irq, "edge");
>> + else
>> + irq_set_chip_handler_name_locked(d, irq_data_get_irq_chip(d),
>> + handle_fasteoi_irq, "fasteoi");
>> +
>
> https://docs.kernel.org/process/maintainer-tip.html#bracket-rules
Will add the braces in v3. Thanks for your review!
--
Troy Mitchell
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next prev parent reply other threads:[~2026-11-11 1:11 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 12:06 [PATCH v2 0/2] irqchip/riscv-aplic: Use trigger specific flow handlers in MSI mode Troy Mitchell
2026-11-10 12:06 ` Troy Mitchell
2026-11-10 12:06 ` [PATCH v2 1/2] irqchip/riscv-aplic: Use handle_edge_irq() for edge-triggered MSI sources Troy Mitchell
2026-11-10 12:06 ` Troy Mitchell
2026-11-11 0:07 ` Thomas Gleixner
2026-11-11 0:07 ` Thomas Gleixner
2026-11-11 1:11 ` Troy Mitchell [this message]
2026-11-11 1:11 ` Troy Mitchell
2026-11-10 12:06 ` [PATCH v2 2/2] irqchip/riscv-aplic: Apply pending affinity changes for level " Troy Mitchell
2026-11-10 12:06 ` Troy Mitchell
2026-11-11 0:09 ` Thomas Gleixner
2026-11-11 0:09 ` Thomas Gleixner
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