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From: "Troy Mitchell" <troy.mitchell@linux.spacemit.com>
To: "Vlad Banea" <montrealtango@gmail.com>, "Yixun Lan" <dlan@kernel.org>
Cc: <troy.mitchell@linux.spacemit.com>, <wangruikang@iscas.ac.cn>,
	<guodong.xu@oss.qualcomm.com>, <jyc0019@gmail.com>,
	<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<pjw@kernel.org>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<alex@ghiti.fr>, <devicetree@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <spacemit@lists.linux.dev>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] riscv: dts: spacemit: k1: give each PCIe port its own DMA window
Date: Fri, 13 Nov 2026 08:40:53 +0000	[thread overview]
Message-ID: <DMTY5W1EG9R9.2OG78EAK5J7UG@linux.spacemit.com> (raw)
In-Reply-To: <20261113023158.2872492-1-montrealtango@gmail.com>

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On Fri Nov 13, 2026 at 2:31 AM GMT, Vlad Banea wrote:
> On K1 a PCIe master only sees DDR: bus addresses 0-2 GB map to CPU
> 0-2 GB and bus 2-16 GB to CPU 4-18 GB. A root port does not forward
> upstream an inbound access that falls inside its own memory window, so
> dma-ranges must skip each port's own outbound window; the other ports'
> windows reach memory.
>
> The shared pcie-bus skips all three windows, bus 0x8000_0000-0xb7ff_ffff,
> which leaves CPU addresses 0x1_0000_0000-0x1_37ff_ffff unreachable from
> every port. Give each port its own bus that skips only its own window.
> On boards with more than 2 GB of RAM, each port can then reach another
> 512-640 MB without SWIOTLB bouncing.
>
> Signed-off-by: Vlad Banea <montrealtango@gmail.com>
Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>


-- 
Troy Mitchell


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WARNING: multiple messages have this Message-ID (diff)
From: "Troy Mitchell" <troy.mitchell@linux.spacemit.com>
To: "Vlad Banea" <montrealtango@gmail.com>, "Yixun Lan" <dlan@kernel.org>
Cc: <troy.mitchell@linux.spacemit.com>, <wangruikang@iscas.ac.cn>,
	<guodong.xu@oss.qualcomm.com>, <jyc0019@gmail.com>,
	<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<pjw@kernel.org>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<alex@ghiti.fr>, <devicetree@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <spacemit@lists.linux.dev>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] riscv: dts: spacemit: k1: give each PCIe port its own DMA window
Date: Fri, 13 Nov 2026 08:40:53 +0000	[thread overview]
Message-ID: <DMTY5W1EG9R9.2OG78EAK5J7UG@linux.spacemit.com> (raw)
In-Reply-To: <20261113023158.2872492-1-montrealtango@gmail.com>


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On Fri Nov 13, 2026 at 2:31 AM GMT, Vlad Banea wrote:
> On K1 a PCIe master only sees DDR: bus addresses 0-2 GB map to CPU
> 0-2 GB and bus 2-16 GB to CPU 4-18 GB. A root port does not forward
> upstream an inbound access that falls inside its own memory window, so
> dma-ranges must skip each port's own outbound window; the other ports'
> windows reach memory.
>
> The shared pcie-bus skips all three windows, bus 0x8000_0000-0xb7ff_ffff,
> which leaves CPU addresses 0x1_0000_0000-0x1_37ff_ffff unreachable from
> every port. Give each port its own bus that skips only its own window.
> On boards with more than 2 GB of RAM, each port can then reach another
> 512-640 MB without SWIOTLB bouncing.
>
> Signed-off-by: Vlad Banea <montrealtango@gmail.com>
Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>


-- 
Troy Mitchell


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  reply	other threads:[~2026-11-13  8:41 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-13  2:31 [PATCH v2] riscv: dts: spacemit: k1: give each PCIe port its own DMA window Vlad Banea
2026-11-13  2:31 ` Vlad Banea
2026-11-13  8:40 ` Troy Mitchell [this message]
2026-11-13  8:40   ` Troy Mitchell

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