* [Qemu-devel] [PATCH 3/3] Replace some register operations by direct usage of cpu_R[i] TCG variables.
@ 2009-06-29 17:49 Filip Navara
0 siblings, 0 replies; only message in thread
From: Filip Navara @ 2009-06-29 17:49 UTC (permalink / raw)
To: qemu-devel
Various operations could be optimized by removing the temporary TCG variables that were used and using cpu_R[i] TCG variables directly. Care must be taken not to use cpu_R[15] directly since it's the program counter register and it's not updated during the translation.
---
target-arm/translate.c | 70 +++++++++++++++---------------------------------
1 files changed, 22 insertions(+), 48 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 2b8b770..d0ec568 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -1506,9 +1506,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
return 1;
if (insn & ARM_CP_RW_BIT) {
if ((insn >> 28) == 0xf) { /* WLDRW wCx */
- tmp = gen_ld32(cpu_T[1], IS_USER(s));
- tcg_gen_mov_i32(cpu_T[0], tmp);
- dead_tmp(tmp);
+ tcg_gen_qemu_ld32u(cpu_T[0], cpu_T[1], IS_USER(s));
gen_op_iwmmxt_movl_wCx_T0(wrd);
} else {
i = 1;
@@ -3867,18 +3865,11 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
}
}
if (rm != 15) {
- TCGv base;
-
- base = load_reg(s, rn);
if (rm == 13) {
- tcg_gen_addi_i32(base, base, stride);
+ tcg_gen_addi_i32(cpu_R[rn], cpu_R[rn], stride);
} else {
- TCGv index;
- index = load_reg(s, rm);
- tcg_gen_add_i32(base, base, index);
- dead_tmp(index);
+ tcg_gen_add_i32(cpu_R[rn], cpu_R[rn], cpu_R[rm]);
}
- store_reg(s, rn, base);
}
return 0;
}
@@ -5780,8 +5771,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
}
if (offset)
tcg_gen_addi_i32(addr, addr, offset);
- tmp = load_reg(s, 14);
- gen_st32(tmp, addr, 0);
+ tcg_gen_qemu_st32(cpu_R[14], addr, 0);
tmp = new_tmp();
gen_helper_cpsr_read(tmp);
tcg_gen_addi_i32(addr, addr, 4);
@@ -7470,21 +7460,18 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
tcg_gen_mul_i32(tmp, tmp, tmp2);
dead_tmp(tmp2);
if (rs != 15) {
- tmp2 = load_reg(s, rs);
- if (op)
- tcg_gen_sub_i32(tmp, tmp2, tmp);
- else
- tcg_gen_add_i32(tmp, tmp, tmp2);
- dead_tmp(tmp2);
+ if (op) {
+ tcg_gen_sub_i32(tmp, cpu_R[rs], tmp);
+ } else {
+ tcg_gen_add_i32(tmp, tmp, cpu_R[rs]);
+ }
}
break;
case 1: /* 16 x 16 -> 32 */
gen_mulxy(tmp, tmp2, op & 2, op & 1);
dead_tmp(tmp2);
if (rs != 15) {
- tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, tmp, tmp2);
- dead_tmp(tmp2);
+ gen_helper_add_setq(tmp, tmp, cpu_R[rs]);
}
break;
case 2: /* Dual multiply add. */
@@ -7499,12 +7486,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
tcg_gen_add_i32(tmp, tmp, tmp2);
}
dead_tmp(tmp2);
- if (rs != 15)
- {
- tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, tmp, tmp2);
- dead_tmp(tmp2);
- }
+ if (rs != 15) {
+ gen_helper_add_setq(tmp, tmp, cpu_R[rs]);
+ }
break;
case 3: /* 32 * 16 -> 32msb */
if (op)
@@ -7515,12 +7499,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
tcg_gen_shri_i64(tmp64, tmp64, 16);
tmp = new_tmp();
tcg_gen_trunc_i64_i32(tmp, tmp64);
- if (rs != 15)
- {
- tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, tmp, tmp2);
- dead_tmp(tmp2);
- }
+ if (rs != 15) {
+ gen_helper_add_setq(tmp, tmp, cpu_R[rs]);
+ }
break;
case 5: case 6: /* 32 * 32 -> 32msb */
gen_imull(tmp, tmp2);
@@ -7532,22 +7513,18 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
tmp = tmp2;
}
if (rs != 15) {
- tmp2 = load_reg(s, rs);
if (insn & (1 << 21)) {
- tcg_gen_add_i32(tmp, tmp, tmp2);
+ tcg_gen_add_i32(tmp, tmp, cpu_R[rs]);
} else {
- tcg_gen_sub_i32(tmp, tmp2, tmp);
+ tcg_gen_sub_i32(tmp, cpu_R[rs], tmp);
}
- dead_tmp(tmp2);
}
break;
case 7: /* Unsigned sum of absolute differences. */
gen_helper_usad8(tmp, tmp, tmp2);
dead_tmp(tmp2);
if (rs != 15) {
- tmp2 = load_reg(s, rs);
- tcg_gen_add_i32(tmp, tmp, tmp2);
- dead_tmp(tmp2);
+ tcg_gen_add_i32(tmp, tmp, cpu_R[rs]);
}
break;
}
@@ -8498,12 +8475,10 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s)
if (insn & (1 << i)) {
if (insn & (1 << 11)) {
/* pop */
- tmp = gen_ld32(addr, IS_USER(s));
- store_reg(s, i, tmp);
+ tcg_gen_qemu_ld32u(cpu_R[i], addr, IS_USER(s));
} else {
/* push */
- tmp = load_reg(s, i);
- gen_st32(tmp, addr, IS_USER(s));
+ tcg_gen_qemu_st32(cpu_R[i], addr, IS_USER(s));
}
/* advance to the next address. */
tcg_gen_addi_i32(addr, addr, 4);
@@ -8518,8 +8493,7 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s)
has completed */
} else {
/* push lr */
- tmp = load_reg(s, 14);
- gen_st32(tmp, addr, IS_USER(s));
+ tcg_gen_qemu_st32(cpu_R[14], addr, IS_USER(s));
}
tcg_gen_addi_i32(addr, addr, 4);
}
--
1.6.3.msysgit.0
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2009-06-29 17:49 [Qemu-devel] [PATCH 3/3] Replace some register operations by direct usage of cpu_R[i] TCG variables Filip Navara
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