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From: Cameron Nemo <cnemo@tutanota.com>
To: Devicetree <devicetree@vger.kernel.org>,
	Linux Arm Kernel <linux-arm-kernel@lists.infradead.org>,
	Linux Rockchip <linux-rockchip@lists.infradead.org>,
	Linux Kernel <linux-kernel@vger.kernel.org>,
	Linux Usb <linux-usb@vger.kernel.org>
Cc: Balbi <balbi@kernel.org>, Robh+dt <robh+dt@kernel.org>,
	Heiko <heiko@sntech.de>, Gregkh <gregkh@linuxfoundation.org>
Subject: [PATCH 2/3] arm64: dts: rockchip: rk3328 usb3 controller node
Date: Sun, 16 Aug 2020 19:18:13 +0200 (CEST)	[thread overview]
Message-ID: <MEsGppx--3-2@tutanota.com> (raw)
In-Reply-To: <MEsGWB_--3-2@tutanota.com>

RK3328 SoCs have one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB 3.0/2.0 OTG basing
on ID of USB3.0 PHY.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Cameron Nemo <cnemo@tutanota.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index bbdb19a3e85d..27e86bf06d3e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -983,6 +983,33 @@ usb_host0_ohci: usb@ff5d0000 {
status = "disabled";
};

+	usbdrd3: usb@ff600000 {
+		compatible = "rockchip,rk3328-dwc3";
+		clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
+			 <&cru ACLK_USB3OTG>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		usbdrd_dwc3: dwc3@ff600000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xff600000 0x0 0x100000>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "otg";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			status = "disabled";
+		};
+	};
+
gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.28.0



_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

WARNING: multiple messages have this Message-ID (diff)
From: Cameron Nemo <cnemo@tutanota.com>
To: Devicetree <devicetree@vger.kernel.org>,
	Linux Arm Kernel <linux-arm-kernel@lists.infradead.org>,
	Linux Rockchip <linux-rockchip@lists.infradead.org>,
	Linux Kernel <linux-kernel@vger.kernel.org>,
	Linux Usb <linux-usb@vger.kernel.org>
Cc: Robh+dt <robh+dt@kernel.org>, Heiko <heiko@sntech.de>,
	Balbi <balbi@kernel.org>, Gregkh <gregkh@linuxfoundation.org>
Subject: [PATCH 2/3] arm64: dts: rockchip: rk3328 usb3 controller node
Date: Sun, 16 Aug 2020 19:18:13 +0200 (CEST)	[thread overview]
Message-ID: <MEsGppx--3-2@tutanota.com> (raw)
In-Reply-To: <MEsGWB_--3-2@tutanota.com>

RK3328 SoCs have one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB 3.0/2.0 OTG basing
on ID of USB3.0 PHY.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Cameron Nemo <cnemo@tutanota.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index bbdb19a3e85d..27e86bf06d3e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -983,6 +983,33 @@ usb_host0_ohci: usb@ff5d0000 {
status = "disabled";
};

+	usbdrd3: usb@ff600000 {
+		compatible = "rockchip,rk3328-dwc3";
+		clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
+			 <&cru ACLK_USB3OTG>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		usbdrd_dwc3: dwc3@ff600000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xff600000 0x0 0x100000>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "otg";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			status = "disabled";
+		};
+	};
+
gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.28.0



WARNING: multiple messages have this Message-ID (diff)
From: Cameron Nemo <cnemo@tutanota.com>
To: Devicetree <devicetree@vger.kernel.org>,
	Linux Arm Kernel <linux-arm-kernel@lists.infradead.org>,
	Linux Rockchip <linux-rockchip@lists.infradead.org>,
	Linux Kernel <linux-kernel@vger.kernel.org>,
	Linux Usb <linux-usb@vger.kernel.org>
Cc: Balbi <balbi@kernel.org>, Robh+dt <robh+dt@kernel.org>,
	Heiko <heiko@sntech.de>, Gregkh <gregkh@linuxfoundation.org>
Subject: [PATCH 2/3] arm64: dts: rockchip: rk3328 usb3 controller node
Date: Sun, 16 Aug 2020 19:18:13 +0200 (CEST)	[thread overview]
Message-ID: <MEsGppx--3-2@tutanota.com> (raw)
In-Reply-To: <MEsGWB_--3-2@tutanota.com>

RK3328 SoCs have one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB 3.0/2.0 OTG basing
on ID of USB3.0 PHY.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Cameron Nemo <cnemo@tutanota.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index bbdb19a3e85d..27e86bf06d3e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -983,6 +983,33 @@ usb_host0_ohci: usb@ff5d0000 {
status = "disabled";
};

+	usbdrd3: usb@ff600000 {
+		compatible = "rockchip,rk3328-dwc3";
+		clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
+			 <&cru ACLK_USB3OTG>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		usbdrd_dwc3: dwc3@ff600000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xff600000 0x0 0x100000>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "otg";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			status = "disabled";
+		};
+	};
+
gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.28.0



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2020-08-16 17:18 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-16 17:16 [PATCH 1/3] usb: dwc3: of-simple: Add compatible for rk3328 Cameron Nemo
2020-08-16 17:16 ` Cameron Nemo
2020-08-16 17:16 ` Cameron Nemo
2020-08-16 17:18 ` Cameron Nemo [this message]
2020-08-16 17:18   ` [PATCH 2/3] arm64: dts: rockchip: rk3328 usb3 controller node Cameron Nemo
2020-08-16 17:18   ` Cameron Nemo
2020-08-16 17:19   ` [PATCH 3/3] arm64: dts: rockchip: enable rk3328-rock64 usb3 nodes Cameron Nemo
2020-08-16 17:19     ` Cameron Nemo
2020-08-16 17:19     ` Cameron Nemo
2020-08-16 17:27     ` Cameron Nemo
2020-08-16 17:27       ` Cameron Nemo
2020-08-16 17:27       ` Cameron Nemo
2020-08-16 19:23 ` [PATCH 1/3] usb: dwc3: of-simple: Add compatible for rk3328 Johan Jonker
2020-08-16 19:23   ` Johan Jonker
2020-08-16 19:23   ` Johan Jonker

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