* [PATCH 2/5] drm/amdgpu: Delete unimplemented IH soft_reset() code
2026-09-04 18:34 [PATCH 1/5] drm/amdgpu: Delete SI/CIK/VI IH soft_reset() code Timur Kristóf
@ 2026-09-04 18:34 ` Timur Kristóf
2026-09-04 18:34 ` [PATCH 3/5] drm/amdgpu: Delete GMC v6-v7 " Timur Kristóf
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Timur Kristóf @ 2026-09-04 18:34 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
Cc: Timur Kristóf
The soft_reset() function for IH (interrupt handler) blocks
of Vega and newer have never been implemented, and there are
no plans to implement them.
Let's delete these functions, they don't do anything and
also aren't called from anywhere.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 7 -------
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 7 -------
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 7 -------
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 7 -------
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 8 --------
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 8 --------
6 files changed, 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
index d6554add485c..8dee48649650 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
@@ -693,12 +693,6 @@ static int ih_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
return -ETIMEDOUT;
}
-static int ih_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- /* todo */
- return 0;
-}
-
static void ih_v6_0_update_clockgating_state(struct amdgpu_device *adev,
bool enable)
{
@@ -815,7 +809,6 @@ static const struct amd_ip_funcs ih_v6_0_ip_funcs = {
.suspend = ih_v6_0_suspend,
.resume = ih_v6_0_resume,
.wait_for_idle = ih_v6_0_wait_for_idle,
- .soft_reset = ih_v6_0_soft_reset,
.set_clockgating_state = ih_v6_0_set_clockgating_state,
.set_powergating_state = ih_v6_0_set_powergating_state,
.get_clockgating_state = ih_v6_0_get_clockgating_state,
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
index 0fc348010ac7..ad370b326e88 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -643,12 +643,6 @@ static int ih_v6_1_wait_for_idle(struct amdgpu_ip_block *ip_block)
return -ETIMEDOUT;
}
-static int ih_v6_1_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- /* todo */
- return 0;
-}
-
static void ih_v6_1_update_clockgating_state(struct amdgpu_device *adev,
bool enable)
{
@@ -769,7 +763,6 @@ static const struct amd_ip_funcs ih_v6_1_ip_funcs = {
.suspend = ih_v6_1_suspend,
.resume = ih_v6_1_resume,
.wait_for_idle = ih_v6_1_wait_for_idle,
- .soft_reset = ih_v6_1_soft_reset,
.set_clockgating_state = ih_v6_1_set_clockgating_state,
.set_powergating_state = ih_v6_1_set_powergating_state,
.get_clockgating_state = ih_v6_1_get_clockgating_state,
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
index 3745439b86b3..e5f8742553eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
@@ -700,12 +700,6 @@ static int ih_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
return -ETIMEDOUT;
}
-static int ih_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- /* todo */
- return 0;
-}
-
static void ih_v7_0_update_clockgating_state(struct amdgpu_device *adev,
bool enable)
{
@@ -863,7 +857,6 @@ static const struct amd_ip_funcs ih_v7_0_ip_funcs = {
.suspend = ih_v7_0_suspend,
.resume = ih_v7_0_resume,
.wait_for_idle = ih_v7_0_wait_for_idle,
- .soft_reset = ih_v7_0_soft_reset,
.set_clockgating_state = ih_v7_0_set_clockgating_state,
.set_powergating_state = ih_v7_0_set_powergating_state,
.get_clockgating_state = ih_v7_0_get_clockgating_state,
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 1dae7df9ee17..df2245fa35b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -635,12 +635,6 @@ static int navi10_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
return -ETIMEDOUT;
}
-static int navi10_ih_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- /* todo */
- return 0;
-}
-
static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev,
bool enable)
{
@@ -698,7 +692,6 @@ static const struct amd_ip_funcs navi10_ih_ip_funcs = {
.suspend = navi10_ih_suspend,
.resume = navi10_ih_resume,
.wait_for_idle = navi10_ih_wait_for_idle,
- .soft_reset = navi10_ih_soft_reset,
.set_clockgating_state = navi10_ih_set_clockgating_state,
.set_powergating_state = navi10_ih_set_powergating_state,
.get_clockgating_state = navi10_ih_get_clockgating_state,
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 4509e6130bc2..c9dca49fc2b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -561,13 +561,6 @@ static int vega10_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
return -ETIMEDOUT;
}
-static int vega10_ih_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- /* todo */
-
- return 0;
-}
-
static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev,
bool enable)
{
@@ -625,7 +618,6 @@ const struct amd_ip_funcs vega10_ih_ip_funcs = {
.suspend = vega10_ih_suspend,
.resume = vega10_ih_resume,
.wait_for_idle = vega10_ih_wait_for_idle,
- .soft_reset = vega10_ih_soft_reset,
.set_clockgating_state = vega10_ih_set_clockgating_state,
.set_powergating_state = vega10_ih_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
index 460f4bf195e8..0bda48558d4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
@@ -661,13 +661,6 @@ static int vega20_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
return -ETIMEDOUT;
}
-static int vega20_ih_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- /* todo */
-
- return 0;
-}
-
static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
bool enable)
{
@@ -722,7 +715,6 @@ const struct amd_ip_funcs vega20_ih_ip_funcs = {
.suspend = vega20_ih_suspend,
.resume = vega20_ih_resume,
.wait_for_idle = vega20_ih_wait_for_idle,
- .soft_reset = vega20_ih_soft_reset,
.set_clockgating_state = vega20_ih_set_clockgating_state,
.set_powergating_state = vega20_ih_set_powergating_state,
};
--
2.55.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/5] drm/amdgpu: Delete GMC v6-v7 soft_reset() code
2026-09-04 18:34 [PATCH 1/5] drm/amdgpu: Delete SI/CIK/VI IH soft_reset() code Timur Kristóf
2026-09-04 18:34 ` [PATCH 2/5] drm/amdgpu: Delete unimplemented " Timur Kristóf
@ 2026-09-04 18:34 ` Timur Kristóf
2026-09-04 18:34 ` [PATCH 4/5] drm/amdgpu: Delete unimplemented GMC v9 " Timur Kristóf
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Timur Kristóf @ 2026-09-04 18:34 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
Cc: Timur Kristóf
Note that the soft reset code for GMC v6-v7 was never
called from anywhere, so there is no loss of functionality
from this commit. The implementation looks plausible but
it was never enabled or tested, and unlikely to be useful.
We should only reset the memory controller during ASIC reset
and otherwise leave it alone. Resetting the memory controller
can break everything and risks losing the contents of VRAM
(it's unclear if VRAM is lost or not, but it's likely).
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 85 ---------------------------
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 83 --------------------------
2 files changed, 168 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index cdd11587b12a..71409eb718d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -61,45 +61,6 @@ MODULE_FIRMWARE("amdgpu/si58_mc.bin");
#define MC_SEQ_MISC0__MT__HBM 0x60000000
#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
-static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
-{
- u32 blackout;
- struct amdgpu_ip_block *ip_block;
-
- ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC);
- if (!ip_block)
- return;
-
- gmc_v6_0_wait_for_idle(ip_block);
-
- blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
- if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
- /* Block CPU access */
- WREG32(mmBIF_FB_EN, 0);
- /* blackout the MC */
- blackout = REG_SET_FIELD(blackout,
- MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
- WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
- }
- /* wait for the MC to settle */
- udelay(100);
-
-}
-
-static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
-{
- u32 tmp;
-
- /* unblackout the MC */
- tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
- tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
- WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
- /* allow CPU access */
- tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
- tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
- WREG32(mmBIF_FB_EN, tmp);
-}
-
static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
{
const char *chip_name;
@@ -981,51 +942,6 @@ static int gmc_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
}
-static int gmc_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- struct amdgpu_device *adev = ip_block->adev;
-
- u32 srbm_soft_reset = 0;
- u32 tmp = RREG32(mmSRBM_STATUS);
-
- if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
- srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
- SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
-
- if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
- SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
- if (!(adev->flags & AMD_IS_APU))
- srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
- SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
- }
-
- if (srbm_soft_reset) {
- gmc_v6_0_mc_stop(adev);
-
- if (gmc_v6_0_wait_for_idle(ip_block))
- dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
-
- tmp = RREG32(mmSRBM_SOFT_RESET);
- tmp |= srbm_soft_reset;
- dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
- WREG32(mmSRBM_SOFT_RESET, tmp);
- tmp = RREG32(mmSRBM_SOFT_RESET);
-
- udelay(50);
-
- tmp &= ~srbm_soft_reset;
- WREG32(mmSRBM_SOFT_RESET, tmp);
- tmp = RREG32(mmSRBM_SOFT_RESET);
-
- udelay(50);
-
- gmc_v6_0_mc_resume(adev);
- udelay(50);
- }
-
- return 0;
-}
-
static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src,
unsigned int type,
@@ -1139,7 +1055,6 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
.suspend = gmc_v6_0_suspend,
.resume = gmc_v6_0_resume,
.wait_for_idle = gmc_v6_0_wait_for_idle,
- .soft_reset = gmc_v6_0_soft_reset,
.set_clockgating_state = gmc_v6_0_set_clockgating_state,
.set_powergating_state = gmc_v6_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index c9cc55e18893..c95e097241bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -85,44 +85,6 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
}
}
-static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
-{
- struct amdgpu_ip_block *ip_block;
- u32 blackout;
-
- ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC);
- if (!ip_block)
- return;
-
- gmc_v7_0_wait_for_idle(ip_block);
-
- blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
- if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
- /* Block CPU access */
- WREG32(mmBIF_FB_EN, 0);
- /* blackout the MC */
- blackout = REG_SET_FIELD(blackout,
- MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
- WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
- }
- /* wait for the MC to settle */
- udelay(100);
-}
-
-static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
-{
- u32 tmp;
-
- /* unblackout the MC */
- tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
- tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
- WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
- /* allow CPU access */
- tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
- tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
- WREG32(mmBIF_FB_EN, tmp);
-}
-
/**
* gmc_v7_0_init_microcode - load ucode images from disk
*
@@ -1168,50 +1130,6 @@ static int gmc_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
}
-static int gmc_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- struct amdgpu_device *adev = ip_block->adev;
- u32 srbm_soft_reset = 0;
- u32 tmp = RREG32(mmSRBM_STATUS);
-
- if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
- srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
- SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
-
- if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
- SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
- if (!(adev->flags & AMD_IS_APU))
- srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
- SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
- }
-
- if (srbm_soft_reset) {
- gmc_v7_0_mc_stop(adev);
- if (gmc_v7_0_wait_for_idle(ip_block))
- dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
-
- tmp = RREG32(mmSRBM_SOFT_RESET);
- tmp |= srbm_soft_reset;
- dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
- WREG32(mmSRBM_SOFT_RESET, tmp);
- tmp = RREG32(mmSRBM_SOFT_RESET);
-
- udelay(50);
-
- tmp &= ~srbm_soft_reset;
- WREG32(mmSRBM_SOFT_RESET, tmp);
- tmp = RREG32(mmSRBM_SOFT_RESET);
-
- /* Wait a little for things to settle down */
- udelay(50);
-
- gmc_v7_0_mc_resume(adev);
- udelay(50);
- }
-
- return 0;
-}
-
static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *src,
unsigned int type,
@@ -1353,7 +1271,6 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
.suspend = gmc_v7_0_suspend,
.resume = gmc_v7_0_resume,
.wait_for_idle = gmc_v7_0_wait_for_idle,
- .soft_reset = gmc_v7_0_soft_reset,
.set_clockgating_state = gmc_v7_0_set_clockgating_state,
.set_powergating_state = gmc_v7_0_set_powergating_state,
};
--
2.55.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 4/5] drm/amdgpu: Delete unimplemented GMC v9 soft_reset() code
2026-09-04 18:34 [PATCH 1/5] drm/amdgpu: Delete SI/CIK/VI IH soft_reset() code Timur Kristóf
2026-09-04 18:34 ` [PATCH 2/5] drm/amdgpu: Delete unimplemented " Timur Kristóf
2026-09-04 18:34 ` [PATCH 3/5] drm/amdgpu: Delete GMC v6-v7 " Timur Kristóf
@ 2026-09-04 18:34 ` Timur Kristóf
2026-09-04 18:34 ` [PATCH 5/5] drm/amdgpu: Delete unimplemented DM " Timur Kristóf
2026-09-07 7:43 ` [PATCH 1/5] drm/amdgpu: Delete SI/CIK/VI IH " Christian König
4 siblings, 0 replies; 8+ messages in thread
From: Timur Kristóf @ 2026-09-04 18:34 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
Cc: Timur Kristóf
The soft_reset() function for GMC (memory controller) block
of Vega has never been implemented, and there are no
plans to implement it.
Let's delete this function, it doesn't do anything and
also isn't called from anywhere.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 633772fa71fd..999c4d9a6deb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -2312,12 +2312,6 @@ static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- /* XXX for emulation.*/
- return 0;
-}
-
static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
@@ -2356,7 +2350,6 @@ const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
.suspend = gmc_v9_0_suspend,
.resume = gmc_v9_0_resume,
.wait_for_idle = gmc_v9_0_wait_for_idle,
- .soft_reset = gmc_v9_0_soft_reset,
.set_clockgating_state = gmc_v9_0_set_clockgating_state,
.set_powergating_state = gmc_v9_0_set_powergating_state,
.get_clockgating_state = gmc_v9_0_get_clockgating_state,
--
2.55.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 5/5] drm/amdgpu: Delete unimplemented DM soft_reset() code
2026-09-04 18:34 [PATCH 1/5] drm/amdgpu: Delete SI/CIK/VI IH soft_reset() code Timur Kristóf
` (2 preceding siblings ...)
2026-09-04 18:34 ` [PATCH 4/5] drm/amdgpu: Delete unimplemented GMC v9 " Timur Kristóf
@ 2026-09-04 18:34 ` Timur Kristóf
2026-09-07 7:43 ` [PATCH 1/5] drm/amdgpu: Delete SI/CIK/VI IH " Christian König
4 siblings, 0 replies; 8+ messages in thread
From: Timur Kristóf @ 2026-09-04 18:34 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
Cc: Timur Kristóf
The soft_reset() function for the DCE / DCN blocks
has never been implemented, and there are no
plans to implement it.
Let's delete this function, it doesn't do anything and
also isn't called from anywhere.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 --------
.../drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c | 10 ----------
2 files changed, 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f49cc198fb0d..4cf81b8dc030 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -231,13 +231,6 @@ STATIC_IFN_KUNIT int dm_wait_for_idle(struct amdgpu_ip_block *ip_block)
}
EXPORT_IF_KUNIT(dm_wait_for_idle);
-STATIC_IFN_KUNIT int dm_soft_reset(struct amdgpu_ip_block *ip_block)
-{
- /* XXX todo */
- return 0;
-}
-EXPORT_IF_KUNIT(dm_soft_reset);
-
/*
* DC will program planes with their z-order determined by their ordering
* in the dc_surface_updates array. This comparator is used to sort them
@@ -2109,7 +2102,6 @@ static const struct amd_ip_funcs amdgpu_dm_funcs = {
.suspend = dm_suspend,
.resume = dm_resume,
.wait_for_idle = dm_wait_for_idle,
- .soft_reset = dm_soft_reset,
.set_clockgating_state = dm_set_clockgating_state,
.set_powergating_state = dm_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
index a67774e6db36..a3ccb2522a6a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_test.c
@@ -49,15 +49,6 @@ static void dm_test_wait_for_idle(struct kunit *test)
KUNIT_EXPECT_EQ(test, dm_wait_for_idle(NULL), 0);
}
-/**
- * dm_test_soft_reset - Test placeholder soft-reset callback returns success
- * @test: The KUnit test context
- */
-static void dm_test_soft_reset(struct kunit *test)
-{
- KUNIT_EXPECT_EQ(test, dm_soft_reset(NULL), 0);
-}
-
/**
* dm_test_set_clockgating_state - Test placeholder clockgating callback returns success
* @test: The KUnit test context
@@ -4541,7 +4532,6 @@ static void dm_test_initialize_plane_overlay(struct kunit *test)
static struct kunit_case amdgpu_dm_tests[] = {
/* Simple DM callbacks */
KUNIT_CASE(dm_test_wait_for_idle),
- KUNIT_CASE(dm_test_soft_reset),
KUNIT_CASE(dm_test_set_clockgating_state),
KUNIT_CASE(dm_test_set_powergating_state),
KUNIT_CASE(dm_test_bandwidth_update),
--
2.55.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 1/5] drm/amdgpu: Delete SI/CIK/VI IH soft_reset() code
2026-09-04 18:34 [PATCH 1/5] drm/amdgpu: Delete SI/CIK/VI IH soft_reset() code Timur Kristóf
` (3 preceding siblings ...)
2026-09-04 18:34 ` [PATCH 5/5] drm/amdgpu: Delete unimplemented DM " Timur Kristóf
@ 2026-09-07 7:43 ` Christian König
2026-09-21 10:37 ` Timur Kristóf
4 siblings, 1 reply; 8+ messages in thread
From: Christian König @ 2026-09-07 7:43 UTC (permalink / raw)
To: Timur Kristóf, amd-gfx, Alexander.Deucher, Natalie Vock,
Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
On 9/4/26 20:34, Timur Kristóf wrote:
> The code for SI/CIK/VI IH (interrupt handler) IP blocks
> has a soft_reset() function for each block.
> These functions are not called from anywhere and are
> dead code. It's unclear what the original intention
> was or why the IH block would ever need to be reset.
>
> All SI/CIK/VI GPUs have been working well for
> 10+ years without ever resetting the IH block
> so it's time to just delete the dead code.
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Christian König <christian.koenig@amd.com> for the entire series.
@Alex do you pick them up or should I?
Thanks,
Christian.
> ---
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 31 ------------------------
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 31 ------------------------
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 31 ------------------------
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 30 -----------------------
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 32 -------------------------
> 5 files changed, 155 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index 314d8f1d64cc..73ec61bc69de 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -373,36 +373,6 @@ static int cik_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return -ETIMEDOUT;
> }
>
> -static int cik_ih_soft_reset(struct amdgpu_ip_block *ip_block)
> -{
> - struct amdgpu_device *adev = ip_block->adev;
> -
> - u32 srbm_soft_reset = 0;
> - u32 tmp = RREG32(mmSRBM_STATUS);
> -
> - if (tmp & SRBM_STATUS__IH_BUSY_MASK)
> - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
> -
> - if (srbm_soft_reset) {
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> - tmp |= srbm_soft_reset;
> - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
> - WREG32(mmSRBM_SOFT_RESET, tmp);
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> -
> - udelay(50);
> -
> - tmp &= ~srbm_soft_reset;
> - WREG32(mmSRBM_SOFT_RESET, tmp);
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> -
> - /* Wait a little for things to settle down */
> - udelay(50);
> - }
> -
> - return 0;
> -}
> -
> static int cik_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> @@ -425,7 +395,6 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = {
> .suspend = cik_ih_suspend,
> .resume = cik_ih_resume,
> .wait_for_idle = cik_ih_wait_for_idle,
> - .soft_reset = cik_ih_soft_reset,
> .set_clockgating_state = cik_ih_set_clockgating_state,
> .set_powergating_state = cik_ih_set_powergating_state,
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index 8d02602f8433..82bff26abd5e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -367,36 +367,6 @@ static int cz_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return -ETIMEDOUT;
> }
>
> -static int cz_ih_soft_reset(struct amdgpu_ip_block *ip_block)
> -{
> - u32 srbm_soft_reset = 0;
> - struct amdgpu_device *adev = ip_block->adev;
> - u32 tmp = RREG32(mmSRBM_STATUS);
> -
> - if (tmp & SRBM_STATUS__IH_BUSY_MASK)
> - srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
> - SOFT_RESET_IH, 1);
> -
> - if (srbm_soft_reset) {
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> - tmp |= srbm_soft_reset;
> - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
> - WREG32(mmSRBM_SOFT_RESET, tmp);
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> -
> - udelay(50);
> -
> - tmp &= ~srbm_soft_reset;
> - WREG32(mmSRBM_SOFT_RESET, tmp);
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> -
> - /* Wait a little for things to settle down */
> - udelay(50);
> - }
> -
> - return 0;
> -}
> -
> static int cz_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> @@ -421,7 +391,6 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = {
> .suspend = cz_ih_suspend,
> .resume = cz_ih_resume,
> .wait_for_idle = cz_ih_wait_for_idle,
> - .soft_reset = cz_ih_soft_reset,
> .set_clockgating_state = cz_ih_set_clockgating_state,
> .set_powergating_state = cz_ih_set_powergating_state,
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index 49002c80dc71..29faaa726644 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -361,36 +361,6 @@ static int iceland_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return -ETIMEDOUT;
> }
>
> -static int iceland_ih_soft_reset(struct amdgpu_ip_block *ip_block)
> -{
> - u32 srbm_soft_reset = 0;
> - struct amdgpu_device *adev = ip_block->adev;
> - u32 tmp = RREG32(mmSRBM_STATUS);
> -
> - if (tmp & SRBM_STATUS__IH_BUSY_MASK)
> - srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
> - SOFT_RESET_IH, 1);
> -
> - if (srbm_soft_reset) {
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> - tmp |= srbm_soft_reset;
> - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
> - WREG32(mmSRBM_SOFT_RESET, tmp);
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> -
> - udelay(50);
> -
> - tmp &= ~srbm_soft_reset;
> - WREG32(mmSRBM_SOFT_RESET, tmp);
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> -
> - /* Wait a little for things to settle down */
> - udelay(50);
> - }
> -
> - return 0;
> -}
> -
> static int iceland_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> @@ -413,7 +383,6 @@ static const struct amd_ip_funcs iceland_ih_ip_funcs = {
> .suspend = iceland_ih_suspend,
> .resume = iceland_ih_resume,
> .wait_for_idle = iceland_ih_wait_for_idle,
> - .soft_reset = iceland_ih_soft_reset,
> .set_clockgating_state = iceland_ih_set_clockgating_state,
> .set_powergating_state = iceland_ih_set_powergating_state,
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index 52118765dccf..2c5ac398b582 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -247,35 +247,6 @@ static int si_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return -ETIMEDOUT;
> }
>
> -static int si_ih_soft_reset(struct amdgpu_ip_block *ip_block)
> -{
> - struct amdgpu_device *adev = ip_block->adev;
> -
> - u32 srbm_soft_reset = 0;
> - u32 tmp = RREG32(mmSRBM_STATUS);
> -
> - if (tmp & SRBM_STATUS__IH_BUSY_MASK)
> - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
> -
> - if (srbm_soft_reset) {
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> - tmp |= srbm_soft_reset;
> - dev_info(adev->dev, "mmSRBM_SOFT_RESET=0x%08X\n", tmp);
> - WREG32(mmSRBM_SOFT_RESET, tmp);
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> -
> - udelay(50);
> -
> - tmp &= ~srbm_soft_reset;
> - WREG32(mmSRBM_SOFT_RESET, tmp);
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> -
> - udelay(50);
> - }
> -
> - return 0;
> -}
> -
> static int si_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> @@ -298,7 +269,6 @@ static const struct amd_ip_funcs si_ih_ip_funcs = {
> .suspend = si_ih_suspend,
> .resume = si_ih_resume,
> .wait_for_idle = si_ih_wait_for_idle,
> - .soft_reset = si_ih_soft_reset,
> .set_clockgating_state = si_ih_set_clockgating_state,
> .set_powergating_state = si_ih_set_powergating_state,
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index d84c08698dff..194487a71fd4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -379,37 +379,6 @@ static int tonga_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return -ETIMEDOUT;
> }
>
> -static int tonga_ih_soft_reset(struct amdgpu_ip_block *ip_block)
> -{
> - struct amdgpu_device *adev = ip_block->adev;
> - u32 srbm_soft_reset;
> -
> - if (!adev->irq.srbm_soft_reset)
> - return 0;
> - srbm_soft_reset = adev->irq.srbm_soft_reset;
> -
> - if (srbm_soft_reset) {
> - u32 tmp;
> -
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> - tmp |= srbm_soft_reset;
> - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
> - WREG32(mmSRBM_SOFT_RESET, tmp);
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> -
> - udelay(50);
> -
> - tmp &= ~srbm_soft_reset;
> - WREG32(mmSRBM_SOFT_RESET, tmp);
> - tmp = RREG32(mmSRBM_SOFT_RESET);
> -
> - /* Wait a little for things to settle down */
> - udelay(50);
> - }
> -
> - return 0;
> -}
> -
> static int tonga_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> @@ -432,7 +401,6 @@ static const struct amd_ip_funcs tonga_ih_ip_funcs = {
> .suspend = tonga_ih_suspend,
> .resume = tonga_ih_resume,
> .wait_for_idle = tonga_ih_wait_for_idle,
> - .soft_reset = tonga_ih_soft_reset,
> .set_clockgating_state = tonga_ih_set_clockgating_state,
> .set_powergating_state = tonga_ih_set_powergating_state,
> };
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/5] drm/amdgpu: Delete SI/CIK/VI IH soft_reset() code
2026-09-07 7:43 ` [PATCH 1/5] drm/amdgpu: Delete SI/CIK/VI IH " Christian König
@ 2026-09-21 10:37 ` Timur Kristóf
2026-09-21 20:52 ` Alex Deucher
0 siblings, 1 reply; 8+ messages in thread
From: Timur Kristóf @ 2026-09-21 10:37 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Natalie Vock, Tvrtko Ursulin,
Felix Kuehling, Lijo Lazar, Christian König
On Monday, September 7, 2026 9:43:55 AM Central European Summer Time Christian
König wrote:
> On 9/4/26 20:34, Timur Kristóf wrote:
> > The code for SI/CIK/VI IH (interrupt handler) IP blocks
> > has a soft_reset() function for each block.
> > These functions are not called from anywhere and are
> > dead code. It's unclear what the original intention
> > was or why the IH block would ever need to be reset.
> >
> > All SI/CIK/VI GPUs have been working well for
> > 10+ years without ever resetting the IH block
> > so it's time to just delete the dead code.
> >
> > Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
>
> Acked-by: Christian König <christian.koenig@amd.com> for the entire series.
>
> @Alex do you pick them up or should I?
>
> Thanks,
> Christian.
Hi Alex & Christian,
Ping. Is there anything I need to do to move forward with this series?
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/5] drm/amdgpu: Delete SI/CIK/VI IH soft_reset() code
2026-09-21 10:37 ` Timur Kristóf
@ 2026-09-21 20:52 ` Alex Deucher
0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2026-09-21 20:52 UTC (permalink / raw)
To: Timur Kristóf
Cc: amd-gfx, Alexander.Deucher, Natalie Vock, Tvrtko Ursulin,
Felix Kuehling, Lijo Lazar, Christian König
Applied. Thanks!
Alex
On Mon, Sep 21, 2026 at 7:16 AM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> On Monday, September 7, 2026 9:43:55 AM Central European Summer Time Christian
> König wrote:
> > On 9/4/26 20:34, Timur Kristóf wrote:
> > > The code for SI/CIK/VI IH (interrupt handler) IP blocks
> > > has a soft_reset() function for each block.
> > > These functions are not called from anywhere and are
> > > dead code. It's unclear what the original intention
> > > was or why the IH block would ever need to be reset.
> > >
> > > All SI/CIK/VI GPUs have been working well for
> > > 10+ years without ever resetting the IH block
> > > so it's time to just delete the dead code.
> > >
> > > Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> >
> > Acked-by: Christian König <christian.koenig@amd.com> for the entire series.
> >
> > @Alex do you pick them up or should I?
> >
> > Thanks,
> > Christian.
>
> Hi Alex & Christian,
>
> Ping. Is there anything I need to do to move forward with this series?
>
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread