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From: Conor Dooley <conor.dooley@microchip.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Conor Dooley <conor@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Atish Patra <atishp@atishpatra.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<devicetree@vger.kernel.org>
Subject: Re: [PATCH v2 6/9] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC
Date: Mon, 20 Feb 2023 10:32:57 +0000	[thread overview]
Message-ID: <Y/NMWZAW4KAqKXEs@wendy> (raw)
In-Reply-To: <CAK9=C2UPa5SATTG1pJdckqaoJxh-8EBz8xsENirZQ-vbaHTgjg@mail.gmail.com>


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Hey Anup,

On Mon, Feb 20, 2023 at 10:06:49AM +0530, Anup Patel wrote:
> On Thu, Jan 5, 2023 at 3:47 AM Conor Dooley <conor@kernel.org> wrote:
> > On Tue, Jan 03, 2023 at 07:44:06PM +0530, Anup Patel wrote:
> > > We add DT bindings document for RISC-V advanced platform level
> > > interrupt controller (APLIC) defined by the RISC-V advanced
> > > interrupt architecture (AIA) specification.
> > >
> > > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > > ---
> > >  .../interrupt-controller/riscv,aplic.yaml     | 159 ++++++++++++++++++
> > >  1 file changed, 159 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml

> > I'm sorry Anup, but this child versus delegate thing is still not clear
> > to me binding wise. See below.
> 
> There are two different information in-context of APLIC domain:
> 
> 1) HW child domain numbering: If an APLIC domain has N children
>     then HW will have a fixed child index for each of the N children
>     in the range 0 to N-1. This HW child index is required at the time
>     of setting up interrupt delegation in sourcecfgX registers. The
>     "riscv,children" DT property helps firmware (or bootloader) find
>     the total number of child APLIC domains and corresponding
>     HW child index number.
> 
> 2) IRQ delegation to child domains: An APLIC domain can delegate
>    any IRQ range(s) to a particular APLIC child domain. The
>    "riscv,delegate" DT property is simply a table where we have
>    one row for each IRQ range which is delegated to some child
>    APLIC domain. This property is more of a system setting fixed
>    by the RISC-V platform vendor.

Thanks for the explanations. It's been a while since my brain swapped
this stuff out, but I think delegate/child makes sense to me now.
Just don't ask me to write the dt entry as proof...

Thanks,
Conor.

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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Conor Dooley <conor@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Atish Patra <atishp@atishpatra.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<devicetree@vger.kernel.org>
Subject: Re: [PATCH v2 6/9] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC
Date: Mon, 20 Feb 2023 10:32:57 +0000	[thread overview]
Message-ID: <Y/NMWZAW4KAqKXEs@wendy> (raw)
In-Reply-To: <CAK9=C2UPa5SATTG1pJdckqaoJxh-8EBz8xsENirZQ-vbaHTgjg@mail.gmail.com>

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Hey Anup,

On Mon, Feb 20, 2023 at 10:06:49AM +0530, Anup Patel wrote:
> On Thu, Jan 5, 2023 at 3:47 AM Conor Dooley <conor@kernel.org> wrote:
> > On Tue, Jan 03, 2023 at 07:44:06PM +0530, Anup Patel wrote:
> > > We add DT bindings document for RISC-V advanced platform level
> > > interrupt controller (APLIC) defined by the RISC-V advanced
> > > interrupt architecture (AIA) specification.
> > >
> > > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > > ---
> > >  .../interrupt-controller/riscv,aplic.yaml     | 159 ++++++++++++++++++
> > >  1 file changed, 159 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml

> > I'm sorry Anup, but this child versus delegate thing is still not clear
> > to me binding wise. See below.
> 
> There are two different information in-context of APLIC domain:
> 
> 1) HW child domain numbering: If an APLIC domain has N children
>     then HW will have a fixed child index for each of the N children
>     in the range 0 to N-1. This HW child index is required at the time
>     of setting up interrupt delegation in sourcecfgX registers. The
>     "riscv,children" DT property helps firmware (or bootloader) find
>     the total number of child APLIC domains and corresponding
>     HW child index number.
> 
> 2) IRQ delegation to child domains: An APLIC domain can delegate
>    any IRQ range(s) to a particular APLIC child domain. The
>    "riscv,delegate" DT property is simply a table where we have
>    one row for each IRQ range which is delegated to some child
>    APLIC domain. This property is more of a system setting fixed
>    by the RISC-V platform vendor.

Thanks for the explanations. It's been a while since my brain swapped
this stuff out, but I think delegate/child makes sense to me now.
Just don't ask me to write the dt entry as proof...

Thanks,
Conor.

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  reply	other threads:[~2023-02-20 10:33 UTC|newest]

Thread overview: 72+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-03 14:14 [PATCH v2 0/9] Linux RISC-V AIA Support Anup Patel
2023-01-03 14:14 ` Anup Patel
2023-01-03 14:14 ` [PATCH v2 1/9] RISC-V: Add AIA related CSR defines Anup Patel
2023-01-03 14:14   ` Anup Patel
2023-01-04 23:07   ` Conor Dooley
2023-01-04 23:07     ` Conor Dooley
2023-01-09  5:09     ` Anup Patel
2023-01-09  5:09       ` Anup Patel
2023-01-17 20:42       ` Conor Dooley
2023-01-17 20:42         ` Conor Dooley
2023-01-27 11:58         ` Anup Patel
2023-01-27 11:58           ` Anup Patel
2023-01-27 14:20           ` Conor Dooley
2023-01-27 14:20             ` Conor Dooley
2023-01-03 14:14 ` [PATCH v2 2/9] RISC-V: Detect AIA CSRs from ISA string Anup Patel
2023-01-03 14:14   ` Anup Patel
2023-01-03 14:14 ` [PATCH v2 3/9] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-01-03 14:14   ` Anup Patel
2023-01-13  9:39   ` Marc Zyngier
2023-01-13  9:39     ` Marc Zyngier
2023-01-03 14:14 ` [PATCH v2 4/9] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-01-03 14:14   ` Anup Patel
2023-01-04 23:21   ` Conor Dooley
2023-01-04 23:21     ` Conor Dooley
2023-02-20  3:15     ` Anup Patel
2023-02-20  3:15       ` Anup Patel
2023-01-12 20:49   ` Rob Herring
2023-01-12 20:49     ` Rob Herring
2023-02-20  3:20     ` Anup Patel
2023-02-20  3:20       ` Anup Patel
2023-02-19 11:17   ` Vivian Wang
2023-02-19 11:17     ` Vivian Wang
2023-02-20  3:31     ` Anup Patel
2023-02-20  3:31       ` Anup Patel
2023-01-03 14:14 ` [PATCH v2 5/9] irqchip: Add RISC-V incoming MSI controller driver Anup Patel
2023-01-03 14:14   ` Anup Patel
2023-01-13 10:10   ` Marc Zyngier
2023-01-13 10:10     ` Marc Zyngier
2023-05-01  8:28     ` Anup Patel
2023-05-01  8:28       ` Anup Patel
2023-05-01  8:44       ` Marc Zyngier
2023-05-01  8:44         ` Marc Zyngier
     [not found]   ` <CAPqJEFqhd-=-RYepKqnco7HySoxk7AhEctL+vzNozMSWe0mv7A@mail.gmail.com>
     [not found]     ` <CABvJ_xhcuC92A_oo1mWQoRvtRzE8XXx9bbXKs7N7wKm0=Z3_Cw@mail.gmail.com>
2023-01-18  3:49       ` Fwd: " Vincent Chen
2023-01-18  3:49         ` Vincent Chen
2023-01-18  4:20         ` Anup Patel
2023-01-18  4:20           ` Anup Patel
2023-01-03 14:14 ` [PATCH v2 6/9] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-01-03 14:14   ` Anup Patel
2023-01-04 22:16   ` Conor Dooley
2023-01-04 22:16     ` Conor Dooley
2023-02-20  4:36     ` Anup Patel
2023-02-20  4:36       ` Anup Patel
2023-02-20 10:32       ` Conor Dooley [this message]
2023-02-20 10:32         ` Conor Dooley
2023-02-20 10:56         ` Conor Dooley
2023-02-20 10:56           ` Conor Dooley
2023-01-12 21:02   ` Rob Herring
2023-01-12 21:02     ` Rob Herring
2023-02-19 11:48   ` Vivian Wang
2023-02-19 11:48     ` Vivian Wang
2023-02-20  5:09     ` Anup Patel
2023-02-20  5:09       ` Anup Patel
2023-01-03 14:14 ` [PATCH v2 7/9] irqchip: Add RISC-V advanced PLIC driver Anup Patel
2023-01-03 14:14   ` Anup Patel
     [not found]   ` <CAPqJEFpmAvWiOdackxYwSPBfjo4DnTHXrXVSCC4snMn8tnZXPw@mail.gmail.com>
     [not found]     ` <CABvJ_xhjMa8xTsO-Qa23TOqxPpYxyBYSfV6TmKney-Gp3oi8cA@mail.gmail.com>
2023-01-17  7:09       ` Fwd: " Vincent Chen
2023-01-17  7:09         ` Vincent Chen
2023-01-18  4:37         ` Anup Patel
2023-01-18  4:37           ` Anup Patel
2023-01-03 14:14 ` [PATCH v2 8/9] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-01-03 14:14   ` Anup Patel
2023-01-03 14:14 ` [PATCH v2 9/9] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2023-01-03 14:14   ` Anup Patel

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