* [Intel-gfx] [PATCH 0/5] drm/i915: Error/underrun interrupt fixes
@ 2023-01-25 18:52 Ville Syrjala
2023-01-25 18:52 ` [Intel-gfx] [PATCH 1/5] drm/i915: Mark FIFO underrun disabled earlier Ville Syrjala
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Ville Syrjala @ 2023-01-25 18:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fix up some error interrupt/underrun reporting issues
on old platforms.
Ville Syrjälä (5):
drm/i915: Mark FIFO underrun disabled earlier
drm/i915: Undo rmw damage to gen3 error interrupt handler
drm/i915: Dump PGTBL_ER on gen2/3/4 error interrupt
drm/i915: Extract {i9xx,i965)_error_mask()
drm/i915: Mask page table errors on gen2/3 with FBC
drivers/gpu/drm/i915/display/intel_crtc.c | 3 +
.../drm/i915/display/intel_fifo_underrun.c | 20 +++++
.../drm/i915/display/intel_fifo_underrun.h | 3 +
.../drm/i915/display/intel_modeset_setup.c | 24 ++----
drivers/gpu/drm/i915/i915_irq.c | 80 +++++++++++++------
5 files changed, 86 insertions(+), 44 deletions(-)
--
2.39.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 1/5] drm/i915: Mark FIFO underrun disabled earlier
2023-01-25 18:52 [Intel-gfx] [PATCH 0/5] drm/i915: Error/underrun interrupt fixes Ville Syrjala
@ 2023-01-25 18:52 ` Ville Syrjala
2023-02-23 9:17 ` Govindapillai, Vinod
2023-01-25 18:52 ` [Intel-gfx] [PATCH 2/5] drm/i915: Undo rmw damage to gen3 error interrupt handler Ville Syrjala
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjala @ 2023-01-25 18:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
At least on some platforms (tested on ctg) the way
vgacon does screen blanking seems to flag constant
FIFO underruns, which means we have to be prepared
for them while the driver is loading. Currently
there is a time window between drm_crtc_init() and
intel_sanitize_fifo_underrun_reporting() during
which FIFO underrun reporting is in fact marked as
enabled. Thus we may end up mistakenly detecting
these bogus underruns during driver init.
Close the race by marking FIFO underrun reporting
as disabled prior to even registering the crtc.
intel_sanitize_fifo_underrun_reporting()/etc. will
re-enable it later if needed.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 3 +++
.../drm/i915/display/intel_fifo_underrun.c | 20 ++++++++++++++++
.../drm/i915/display/intel_fifo_underrun.h | 3 +++
.../drm/i915/display/intel_modeset_setup.c | 24 +++++--------------
4 files changed, 32 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 82be0fbe9934..b79a8834559f 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -25,6 +25,7 @@
#include "intel_display_types.h"
#include "intel_drrs.h"
#include "intel_dsi.h"
+#include "intel_fifo_underrun.h"
#include "intel_pipe_crc.h"
#include "intel_psr.h"
#include "intel_sprite.h"
@@ -314,6 +315,8 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
}
crtc->plane_ids_mask |= BIT(primary->id);
+ intel_init_fifo_underrun_reporting(dev_priv, crtc, false);
+
for_each_sprite(dev_priv, pipe, sprite) {
struct intel_plane *plane;
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index d636d21fa9ce..b708a62e509a 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -31,6 +31,7 @@
#include "intel_display_types.h"
#include "intel_fbc.h"
#include "intel_fifo_underrun.h"
+#include "intel_pch_display.h"
/**
* DOC: fifo underrun handling
@@ -509,3 +510,22 @@ void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
+
+void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915,
+ struct intel_crtc *crtc,
+ bool enable)
+{
+ crtc->cpu_fifo_underrun_disabled = !enable;
+
+ /*
+ * We track the PCH trancoder underrun reporting state
+ * within the crtc. With crtc for pipe A housing the underrun
+ * reporting state for PCH transcoder A, crtc for pipe B housing
+ * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
+ * and marking underrun reporting as disabled for the non-existing
+ * PCH transcoders B and C would prevent enabling the south
+ * error interrupt (see cpt_can_enable_serr_int()).
+ */
+ if (intel_has_pch_trancoder(i915, crtc->pipe))
+ crtc->pch_fifo_underrun_disabled = !enable;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
index 2e47d7d3c101..b00d8abebcf9 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
@@ -9,8 +9,11 @@
#include <linux/types.h>
struct drm_i915_private;
+struct intel_crtc;
enum pipe;
+void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915,
+ struct intel_crtc *crtc, bool enable);
bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
enum pipe pipe, bool enable);
bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 52cdbd4fc2fa..be095327a9ba 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -21,6 +21,7 @@
#include "intel_display.h"
#include "intel_display_power.h"
#include "intel_display_types.h"
+#include "intel_fifo_underrun.h"
#include "intel_modeset_setup.h"
#include "intel_pch_display.h"
#include "intel_pm.h"
@@ -234,12 +235,9 @@ static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- if (!crtc_state->hw.active && !HAS_GMCH(i915))
- return;
-
/*
- * We start out with underrun reporting disabled to avoid races.
- * For correct bookkeeping mark this on active crtcs.
+ * We start out with underrun reporting disabled on active
+ * pipes to avoid races.
*
* Also on gmch platforms we dont have any hardware bits to
* disable the underrun reporting. Which means we need to start
@@ -250,19 +248,9 @@ static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state
* No protection against concurrent access is required - at
* worst a fifo underrun happens which also sets this to false.
*/
- crtc->cpu_fifo_underrun_disabled = true;
-
- /*
- * We track the PCH trancoder underrun reporting state
- * within the crtc. With crtc for pipe A housing the underrun
- * reporting state for PCH transcoder A, crtc for pipe B housing
- * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
- * and marking underrun reporting as disabled for the non-existing
- * PCH transcoders B and C would prevent enabling the south
- * error interrupt (see cpt_can_enable_serr_int()).
- */
- if (intel_has_pch_trancoder(i915, crtc->pipe))
- crtc->pch_fifo_underrun_disabled = true;
+ intel_init_fifo_underrun_reporting(i915, crtc,
+ !crtc_state->hw.active &&
+ !HAS_GMCH(i915));
}
static void intel_sanitize_crtc(struct intel_crtc *crtc,
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 2/5] drm/i915: Undo rmw damage to gen3 error interrupt handler
2023-01-25 18:52 [Intel-gfx] [PATCH 0/5] drm/i915: Error/underrun interrupt fixes Ville Syrjala
2023-01-25 18:52 ` [Intel-gfx] [PATCH 1/5] drm/i915: Mark FIFO underrun disabled earlier Ville Syrjala
@ 2023-01-25 18:52 ` Ville Syrjala
2023-02-23 12:21 ` Govindapillai, Vinod
2023-01-25 18:52 ` [Intel-gfx] [PATCH 3/5] drm/i915: Dump PGTBL_ER on gen2/3/4 error interrupt Ville Syrjala
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjala @ 2023-01-25 18:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The gen2/gen3 irq code is supposed to be identical apart
from the 32bit vs. 16bit access width. The recent change
to intel_de_rmw() ruined that symmetry. Restore it to avoid
needless mental gymnastics when comparing the two codepaths.
And while at it remove the extra eir!=0 check that somehow
ended up in the gen2 codepath only.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 240d5e198904..b45d426a5bd5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3510,9 +3510,7 @@ static void i8xx_error_irq_ack(struct drm_i915_private *i915,
u16 emr;
*eir = intel_uncore_read16(uncore, EIR);
-
- if (*eir)
- intel_uncore_write16(uncore, EIR, *eir);
+ intel_uncore_write16(uncore, EIR, *eir);
*eir_stuck = intel_uncore_read16(uncore, EIR);
if (*eir_stuck == 0)
@@ -3548,7 +3546,8 @@ static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
{
u32 emr;
- *eir = intel_uncore_rmw(&dev_priv->uncore, EIR, 0, 0);
+ *eir = intel_uncore_read(&dev_priv->uncore, EIR);
+ intel_uncore_write(&dev_priv->uncore, EIR, *eir);
*eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);
if (*eir_stuck == 0)
@@ -3564,7 +3563,8 @@ static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
* (or by a GPU reset) so we mask any bit that
* remains set.
*/
- emr = intel_uncore_rmw(&dev_priv->uncore, EMR, ~0, 0xffffffff);
+ emr = intel_uncore_read(&dev_priv->uncore, EMR);
+ intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff);
intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck);
}
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 3/5] drm/i915: Dump PGTBL_ER on gen2/3/4 error interrupt
2023-01-25 18:52 [Intel-gfx] [PATCH 0/5] drm/i915: Error/underrun interrupt fixes Ville Syrjala
2023-01-25 18:52 ` [Intel-gfx] [PATCH 1/5] drm/i915: Mark FIFO underrun disabled earlier Ville Syrjala
2023-01-25 18:52 ` [Intel-gfx] [PATCH 2/5] drm/i915: Undo rmw damage to gen3 error interrupt handler Ville Syrjala
@ 2023-01-25 18:52 ` Ville Syrjala
2023-02-23 12:23 ` Govindapillai, Vinod
2023-01-25 18:52 ` [Intel-gfx] [PATCH 4/5] drm/i915: Extract {i9xx, i965)_error_mask() Ville Syrjala
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjala @ 2023-01-25 18:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
PGTBL_ER contains the individual reasons for the page table
error interrupt. Dump it out.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b45d426a5bd5..0e90c348175e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3539,6 +3539,9 @@ static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
if (eir_stuck)
drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
eir_stuck);
+
+ drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n",
+ intel_uncore_read(&dev_priv->uncore, PGTBL_ER));
}
static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
@@ -3576,6 +3579,9 @@ static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
if (eir_stuck)
drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
eir_stuck);
+
+ drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n",
+ intel_uncore_read(&dev_priv->uncore, PGTBL_ER));
}
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 4/5] drm/i915: Extract {i9xx, i965)_error_mask()
2023-01-25 18:52 [Intel-gfx] [PATCH 0/5] drm/i915: Error/underrun interrupt fixes Ville Syrjala
` (2 preceding siblings ...)
2023-01-25 18:52 ` [Intel-gfx] [PATCH 3/5] drm/i915: Dump PGTBL_ER on gen2/3/4 error interrupt Ville Syrjala
@ 2023-01-25 18:52 ` Ville Syrjala
2023-02-23 12:34 ` Govindapillai, Vinod
2023-01-25 18:52 ` [Intel-gfx] [PATCH 5/5] drm/i915: Mask page table errors on gen2/3 with FBC Ville Syrjala
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjala @ 2023-01-25 18:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pull the EMR calculation into small helpers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 46 ++++++++++++++++++---------------
1 file changed, 25 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0e90c348175e..081b79d00521 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3471,15 +3471,18 @@ static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
dev_priv->irq_mask = ~0u;
}
+static u32 i9xx_error_mask(struct drm_i915_private *i915)
+{
+ return ~(I915_ERROR_PAGE_TABLE |
+ I915_ERROR_MEMORY_REFRESH);
+}
+
static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
u16 enable_mask;
- intel_uncore_write16(uncore,
- EMR,
- ~(I915_ERROR_PAGE_TABLE |
- I915_ERROR_MEMORY_REFRESH));
+ intel_uncore_write16(uncore, EMR, i9xx_error_mask(dev_priv));
/* Unmask the interrupts that we always want on. */
dev_priv->irq_mask =
@@ -3651,8 +3654,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
struct intel_uncore *uncore = &dev_priv->uncore;
u32 enable_mask;
- intel_uncore_write(uncore, EMR, ~(I915_ERROR_PAGE_TABLE |
- I915_ERROR_MEMORY_REFRESH));
+ intel_uncore_write(uncore, EMR, i9xx_error_mask(dev_priv));
/* Unmask the interrupts that we always want on. */
dev_priv->irq_mask =
@@ -3755,26 +3757,28 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
dev_priv->irq_mask = ~0u;
}
-static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
+static u32 i965_error_mask(struct drm_i915_private *i915)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
- u32 enable_mask;
- u32 error_mask;
-
/*
* Enable some error detection, note the instruction error mask
* bit is reserved, so we leave it masked.
*/
- if (IS_G4X(dev_priv)) {
- error_mask = ~(GM45_ERROR_PAGE_TABLE |
- GM45_ERROR_MEM_PRIV |
- GM45_ERROR_CP_PRIV |
- I915_ERROR_MEMORY_REFRESH);
- } else {
- error_mask = ~(I915_ERROR_PAGE_TABLE |
- I915_ERROR_MEMORY_REFRESH);
- }
- intel_uncore_write(uncore, EMR, error_mask);
+ if (IS_G4X(i915))
+ return ~(GM45_ERROR_PAGE_TABLE |
+ GM45_ERROR_MEM_PRIV |
+ GM45_ERROR_CP_PRIV |
+ I915_ERROR_MEMORY_REFRESH);
+ else
+ return ~(I915_ERROR_PAGE_TABLE |
+ I915_ERROR_MEMORY_REFRESH);
+}
+
+static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ u32 enable_mask;
+
+ intel_uncore_write(uncore, EMR, i965_error_mask(dev_priv));
/* Unmask the interrupts that we always want on. */
dev_priv->irq_mask =
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 5/5] drm/i915: Mask page table errors on gen2/3 with FBC
2023-01-25 18:52 [Intel-gfx] [PATCH 0/5] drm/i915: Error/underrun interrupt fixes Ville Syrjala
` (3 preceding siblings ...)
2023-01-25 18:52 ` [Intel-gfx] [PATCH 4/5] drm/i915: Extract {i9xx, i965)_error_mask() Ville Syrjala
@ 2023-01-25 18:52 ` Ville Syrjala
2023-02-23 12:46 ` Govindapillai, Vinod
2023-01-26 2:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Error/underrun interrupt fixes Patchwork
2023-01-26 12:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
6 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjala @ 2023-01-25 18:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
FBC on gen2/3 seems to trigger page table errors. No visual
artifacts are visible, and essentially the same FBC
code works on gen4 so these seem entirely spurious. There
are also hints in gen3 bspec indicating that certain bits
in PGTBL_ER are just not wired up correctly in the
hardware.
Ideally we'd want to mask out only the bogus bits, but
sadly there is no mask for PGTBL_ER, and instead we are
forced to mask out all page table errors via EMR :(
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 081b79d00521..496f76bf42f3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3473,8 +3473,23 @@ static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
static u32 i9xx_error_mask(struct drm_i915_private *i915)
{
- return ~(I915_ERROR_PAGE_TABLE |
- I915_ERROR_MEMORY_REFRESH);
+ /*
+ * On gen2/3 FBC generates (seemingly spurious)
+ * display INVALID_GTT/INVALID_GTT_PTE table errors.
+ *
+ * Also gen3 bspec has this to say:
+ * "DISPA_INVALID_GTT_PTE
+ " [DevNapa] : Reserved. This bit does not reflect the page
+ " table error for the display plane A."
+ *
+ * Unfortunately we can't mask off individual PGTBL_ER bits,
+ * so we just have to mask off all page table errors via EMR.
+ */
+ if (HAS_FBC(i915))
+ return ~I915_ERROR_MEMORY_REFRESH;
+ else
+ return ~(I915_ERROR_PAGE_TABLE |
+ I915_ERROR_MEMORY_REFRESH);
}
static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3762,6 +3777,9 @@ static u32 i965_error_mask(struct drm_i915_private *i915)
/*
* Enable some error detection, note the instruction error mask
* bit is reserved, so we leave it masked.
+ *
+ * i965 FBC no longer generates spurious GTT errors,
+ * so we can always enable the page table errors.
*/
if (IS_G4X(i915))
return ~(GM45_ERROR_PAGE_TABLE |
--
2.39.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Error/underrun interrupt fixes
2023-01-25 18:52 [Intel-gfx] [PATCH 0/5] drm/i915: Error/underrun interrupt fixes Ville Syrjala
` (4 preceding siblings ...)
2023-01-25 18:52 ` [Intel-gfx] [PATCH 5/5] drm/i915: Mask page table errors on gen2/3 with FBC Ville Syrjala
@ 2023-01-26 2:27 ` Patchwork
2023-01-26 12:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2023-01-26 2:27 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4537 bytes --]
== Series Details ==
Series: drm/i915: Error/underrun interrupt fixes
URL : https://patchwork.freedesktop.org/series/113353/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12640 -> Patchwork_113353v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/index.html
Participating hosts (37 -> 36)
------------------------------
Missing (1): fi-rkl-11600
Known issues
------------
Here are the changes found in Patchwork_113353v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- fi-bsw-nick: NOTRUN -> [SKIP][1] ([fdo#109271]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/fi-bsw-nick/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- fi-hsw-4770: NOTRUN -> [SKIP][2] ([fdo#109271])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-crc.html
#### Possible fixes ####
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [FAIL][3] ([i915#7229]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlp-9}: [DMESG-WARN][5] -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/bat-adlp-9/igt@gem_exec_suspend@basic-s0@smem.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/bat-adlp-9/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [INCOMPLETE][7] ([i915#7911]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@migrate:
- {bat-dg2-11}: [DMESG-WARN][9] ([i915#7699]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/bat-dg2-11/igt@i915_selftest@live@migrate.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/bat-dg2-11/igt@i915_selftest@live@migrate.html
* igt@kms_cursor_legacy@basic-flip-after-cursor@atomic-transitions-varying-size:
- fi-bsw-n3050: [FAIL][11] ([i915#2346]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/fi-bsw-n3050/igt@kms_cursor_legacy@basic-flip-after-cursor@atomic-transitions-varying-size.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/fi-bsw-n3050/igt@kms_cursor_legacy@basic-flip-after-cursor@atomic-transitions-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
Build changes
-------------
* Linux: CI_DRM_12640 -> Patchwork_113353v1
CI-20190529: 20190529
CI_DRM_12640: cc7783f223ac644092bb8788f0750fc5c68aa00e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7136: 31b6af91747ad8c705399c9006cdb81cb1864146 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113353v1: cc7783f223ac644092bb8788f0750fc5c68aa00e @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
2f1752ce21e5 drm/i915: Mask page table errors on gen2/3 with FBC
9cc4667e1b16 drm/i915: Extract {i9xx, i965)_error_mask()
7c1aade88d3e drm/i915: Dump PGTBL_ER on gen2/3/4 error interrupt
3667dec44110 drm/i915: Undo rmw damage to gen3 error interrupt handler
c74466c4b5e7 drm/i915: Mark FIFO underrun disabled earlier
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/index.html
[-- Attachment #2: Type: text/html, Size: 5212 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Error/underrun interrupt fixes
2023-01-25 18:52 [Intel-gfx] [PATCH 0/5] drm/i915: Error/underrun interrupt fixes Ville Syrjala
` (5 preceding siblings ...)
2023-01-26 2:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Error/underrun interrupt fixes Patchwork
@ 2023-01-26 12:55 ` Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2023-01-26 12:55 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 17066 bytes --]
== Series Details ==
Series: drm/i915: Error/underrun interrupt fixes
URL : https://patchwork.freedesktop.org/series/113353/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12640_full -> Patchwork_113353v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/index.html
Participating hosts (12 -> 10)
------------------------------
Missing (2): pig-skl-6260u pig-kbl-iris
Known issues
------------
Here are the changes found in Patchwork_113353v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-glk4/igt@gem_exec_fair@basic-pace@vecs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-glk6/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2346])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
#### Possible fixes ####
* igt@fbdev@nullptr:
- {shard-rkl}: [SKIP][5] ([i915#2582]) -> [PASS][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-1/igt@fbdev@nullptr.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-6/igt@fbdev@nullptr.html
* igt@gem_eio@suspend:
- {shard-rkl}: [FAIL][7] ([i915#7052]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-3/igt@gem_eio@suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-5/igt@gem_eio@suspend.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][9] ([i915#2846]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-glk9/igt@gem_exec_fair@basic-deadline.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [FAIL][11] ([i915#2842]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-glk3/igt@gem_exec_fair@basic-none-share@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-glk9/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_reloc@basic-gtt-read-noreloc:
- {shard-rkl}: [SKIP][13] ([i915#3281]) -> [PASS][14] +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-3/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
* igt@gem_partial_pwrite_pread@writes-after-reads-display:
- {shard-rkl}: [SKIP][15] ([i915#3282]) -> [PASS][16] +4 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-3/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-display.html
* igt@gen9_exec_parse@valid-registers:
- {shard-rkl}: [SKIP][17] ([i915#2527]) -> [PASS][18] +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-3/igt@gen9_exec_parse@valid-registers.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-5/igt@gen9_exec_parse@valid-registers.html
* igt@i915_hangman@gt-engine-error@bcs0:
- {shard-rkl}: [SKIP][19] ([i915#6258]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-5/igt@i915_hangman@gt-engine-error@bcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-4/igt@i915_hangman@gt-engine-error@bcs0.html
* igt@i915_pm_sseu@full-enable:
- {shard-rkl}: [SKIP][21] ([i915#4387]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@i915_pm_sseu@full-enable.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-5/igt@i915_pm_sseu@full-enable.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- {shard-rkl}: [SKIP][23] ([i915#1849] / [i915#4098]) -> [PASS][24] +9 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_properties@plane-properties-atomic:
- {shard-rkl}: [SKIP][25] ([i915#1849]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-5/igt@kms_properties@plane-properties-atomic.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-6/igt@kms_properties@plane-properties-atomic.html
* igt@kms_psr@suspend:
- {shard-rkl}: [SKIP][27] ([i915#1072]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-5/igt@kms_psr@suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-6/igt@kms_psr@suspend.html
* igt@kms_vblank@pipe-b-query-idle:
- {shard-rkl}: [SKIP][29] ([i915#1845] / [i915#4098]) -> [PASS][30] +16 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-1/igt@kms_vblank@pipe-b-query-idle.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-6/igt@kms_vblank@pipe-b-query-idle.html
* igt@perf@polling-small-buf:
- {shard-rkl}: [FAIL][31] ([i915#1722]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-2/igt@perf@polling-small-buf.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-5/igt@perf@polling-small-buf.html
* igt@perf_pmu@idle@rcs0:
- {shard-rkl}: [FAIL][33] ([i915#4349]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12640/shard-rkl-6/igt@perf_pmu@idle@rcs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/shard-rkl-5/igt@perf_pmu@idle@rcs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
Build changes
-------------
* Linux: CI_DRM_12640 -> Patchwork_113353v1
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12640: cc7783f223ac644092bb8788f0750fc5c68aa00e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7136: 31b6af91747ad8c705399c9006cdb81cb1864146 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113353v1: cc7783f223ac644092bb8788f0750fc5c68aa00e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113353v1/index.html
[-- Attachment #2: Type: text/html, Size: 9813 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 1/5] drm/i915: Mark FIFO underrun disabled earlier
2023-01-25 18:52 ` [Intel-gfx] [PATCH 1/5] drm/i915: Mark FIFO underrun disabled earlier Ville Syrjala
@ 2023-02-23 9:17 ` Govindapillai, Vinod
0 siblings, 0 replies; 14+ messages in thread
From: Govindapillai, Vinod @ 2023-02-23 9:17 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Thanks
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
BR
Vinod
On Wed, 2023-01-25 at 20:52 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> At least on some platforms (tested on ctg) the way
> vgacon does screen blanking seems to flag constant
> FIFO underruns, which means we have to be prepared
> for them while the driver is loading. Currently
> there is a time window between drm_crtc_init() and
> intel_sanitize_fifo_underrun_reporting() during
> which FIFO underrun reporting is in fact marked as
> enabled. Thus we may end up mistakenly detecting
> these bogus underruns during driver init.
>
> Close the race by marking FIFO underrun reporting
> as disabled prior to even registering the crtc.
> intel_sanitize_fifo_underrun_reporting()/etc. will
> re-enable it later if needed.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 3 +++
> .../drm/i915/display/intel_fifo_underrun.c | 20 ++++++++++++++++
> .../drm/i915/display/intel_fifo_underrun.h | 3 +++
> .../drm/i915/display/intel_modeset_setup.c | 24 +++++--------------
> 4 files changed, 32 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 82be0fbe9934..b79a8834559f 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -25,6 +25,7 @@
> #include "intel_display_types.h"
> #include "intel_drrs.h"
> #include "intel_dsi.h"
> +#include "intel_fifo_underrun.h"
> #include "intel_pipe_crc.h"
> #include "intel_psr.h"
> #include "intel_sprite.h"
> @@ -314,6 +315,8 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
> }
> crtc->plane_ids_mask |= BIT(primary->id);
>
> + intel_init_fifo_underrun_reporting(dev_priv, crtc, false);
> +
> for_each_sprite(dev_priv, pipe, sprite) {
> struct intel_plane *plane;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index d636d21fa9ce..b708a62e509a 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -31,6 +31,7 @@
> #include "intel_display_types.h"
> #include "intel_fbc.h"
> #include "intel_fifo_underrun.h"
> +#include "intel_pch_display.h"
>
> /**
> * DOC: fifo underrun handling
> @@ -509,3 +510,22 @@ void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
>
> spin_unlock_irq(&dev_priv->irq_lock);
> }
> +
> +void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915,
> + struct intel_crtc *crtc,
> + bool enable)
> +{
> + crtc->cpu_fifo_underrun_disabled = !enable;
> +
> + /*
> + * We track the PCH trancoder underrun reporting state
> + * within the crtc. With crtc for pipe A housing the underrun
> + * reporting state for PCH transcoder A, crtc for pipe B housing
> + * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
> + * and marking underrun reporting as disabled for the non-existing
> + * PCH transcoders B and C would prevent enabling the south
> + * error interrupt (see cpt_can_enable_serr_int()).
> + */
> + if (intel_has_pch_trancoder(i915, crtc->pipe))
> + crtc->pch_fifo_underrun_disabled = !enable;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
> b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
> index 2e47d7d3c101..b00d8abebcf9 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h
> @@ -9,8 +9,11 @@
> #include <linux/types.h>
>
> struct drm_i915_private;
> +struct intel_crtc;
> enum pipe;
>
> +void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915,
> + struct intel_crtc *crtc, bool enable);
> bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
> enum pipe pipe, bool enable);
> bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 52cdbd4fc2fa..be095327a9ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -21,6 +21,7 @@
> #include "intel_display.h"
> #include "intel_display_power.h"
> #include "intel_display_types.h"
> +#include "intel_fifo_underrun.h"
> #include "intel_modeset_setup.h"
> #include "intel_pch_display.h"
> #include "intel_pm.h"
> @@ -234,12 +235,9 @@ static void intel_sanitize_fifo_underrun_reporting(const struct
> intel_crtc_state
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>
> - if (!crtc_state->hw.active && !HAS_GMCH(i915))
> - return;
> -
> /*
> - * We start out with underrun reporting disabled to avoid races.
> - * For correct bookkeeping mark this on active crtcs.
> + * We start out with underrun reporting disabled on active
> + * pipes to avoid races.
> *
> * Also on gmch platforms we dont have any hardware bits to
> * disable the underrun reporting. Which means we need to start
> @@ -250,19 +248,9 @@ static void intel_sanitize_fifo_underrun_reporting(const struct
> intel_crtc_state
> * No protection against concurrent access is required - at
> * worst a fifo underrun happens which also sets this to false.
> */
> - crtc->cpu_fifo_underrun_disabled = true;
> -
> - /*
> - * We track the PCH trancoder underrun reporting state
> - * within the crtc. With crtc for pipe A housing the underrun
> - * reporting state for PCH transcoder A, crtc for pipe B housing
> - * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
> - * and marking underrun reporting as disabled for the non-existing
> - * PCH transcoders B and C would prevent enabling the south
> - * error interrupt (see cpt_can_enable_serr_int()).
> - */
> - if (intel_has_pch_trancoder(i915, crtc->pipe))
> - crtc->pch_fifo_underrun_disabled = true;
> + intel_init_fifo_underrun_reporting(i915, crtc,
> + !crtc_state->hw.active &&
> + !HAS_GMCH(i915));
> }
>
> static void intel_sanitize_crtc(struct intel_crtc *crtc,
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 2/5] drm/i915: Undo rmw damage to gen3 error interrupt handler
2023-01-25 18:52 ` [Intel-gfx] [PATCH 2/5] drm/i915: Undo rmw damage to gen3 error interrupt handler Ville Syrjala
@ 2023-02-23 12:21 ` Govindapillai, Vinod
0 siblings, 0 replies; 14+ messages in thread
From: Govindapillai, Vinod @ 2023-02-23 12:21 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Hello
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
BR
Vinod
On Wed, 2023-01-25 at 20:52 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The gen2/gen3 irq code is supposed to be identical apart
> from the 32bit vs. 16bit access width. The recent change
> to intel_de_rmw() ruined that symmetry. Restore it to avoid
> needless mental gymnastics when comparing the two codepaths.
>
> And while at it remove the extra eir!=0 check that somehow
> ended up in the gen2 codepath only.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 240d5e198904..b45d426a5bd5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3510,9 +3510,7 @@ static void i8xx_error_irq_ack(struct drm_i915_private *i915,
> u16 emr;
>
> *eir = intel_uncore_read16(uncore, EIR);
> -
> - if (*eir)
> - intel_uncore_write16(uncore, EIR, *eir);
> + intel_uncore_write16(uncore, EIR, *eir);
>
> *eir_stuck = intel_uncore_read16(uncore, EIR);
> if (*eir_stuck == 0)
> @@ -3548,7 +3546,8 @@ static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
> {
> u32 emr;
>
> - *eir = intel_uncore_rmw(&dev_priv->uncore, EIR, 0, 0);
> + *eir = intel_uncore_read(&dev_priv->uncore, EIR);
> + intel_uncore_write(&dev_priv->uncore, EIR, *eir);
>
> *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);
> if (*eir_stuck == 0)
> @@ -3564,7 +3563,8 @@ static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
> * (or by a GPU reset) so we mask any bit that
> * remains set.
> */
> - emr = intel_uncore_rmw(&dev_priv->uncore, EMR, ~0, 0xffffffff);
> + emr = intel_uncore_read(&dev_priv->uncore, EMR);
> + intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff);
> intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck);
> }
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 3/5] drm/i915: Dump PGTBL_ER on gen2/3/4 error interrupt
2023-01-25 18:52 ` [Intel-gfx] [PATCH 3/5] drm/i915: Dump PGTBL_ER on gen2/3/4 error interrupt Ville Syrjala
@ 2023-02-23 12:23 ` Govindapillai, Vinod
0 siblings, 0 replies; 14+ messages in thread
From: Govindapillai, Vinod @ 2023-02-23 12:23 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Hi
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
BR
Vinod
On Wed, 2023-01-25 at 20:52 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> PGTBL_ER contains the individual reasons for the page table
> error interrupt. Dump it out.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b45d426a5bd5..0e90c348175e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3539,6 +3539,9 @@ static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
> if (eir_stuck)
> drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
> eir_stuck);
> +
> + drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n",
> + intel_uncore_read(&dev_priv->uncore, PGTBL_ER));
> }
>
> static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
> @@ -3576,6 +3579,9 @@ static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
> if (eir_stuck)
> drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
> eir_stuck);
> +
> + drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n",
> + intel_uncore_read(&dev_priv->uncore, PGTBL_ER));
> }
>
> static irqreturn_t i8xx_irq_handler(int irq, void *arg)
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 4/5] drm/i915: Extract {i9xx, i965)_error_mask()
2023-01-25 18:52 ` [Intel-gfx] [PATCH 4/5] drm/i915: Extract {i9xx, i965)_error_mask() Ville Syrjala
@ 2023-02-23 12:34 ` Govindapillai, Vinod
0 siblings, 0 replies; 14+ messages in thread
From: Govindapillai, Vinod @ 2023-02-23 12:34 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Hi,
On Wed, 2023-01-25 at 20:52 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the EMR calculation into small helpers.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 46 ++++++++++++++++++---------------
> 1 file changed, 25 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 0e90c348175e..081b79d00521 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3471,15 +3471,18 @@ static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
> dev_priv->irq_mask = ~0u;
> }
>
> +static u32 i9xx_error_mask(struct drm_i915_private *i915)
> +{
> + return ~(I915_ERROR_PAGE_TABLE |
> + I915_ERROR_MEMORY_REFRESH);
> +}
> +
> static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> u16 enable_mask;
>
> - intel_uncore_write16(uncore,
> - EMR,
> - ~(I915_ERROR_PAGE_TABLE |
> - I915_ERROR_MEMORY_REFRESH));
> + intel_uncore_write16(uncore, EMR, i9xx_error_mask(dev_priv));
>
> /* Unmask the interrupts that we always want on. */
> dev_priv->irq_mask =
> @@ -3651,8 +3654,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
> struct intel_uncore *uncore = &dev_priv->uncore;
> u32 enable_mask;
>
> - intel_uncore_write(uncore, EMR, ~(I915_ERROR_PAGE_TABLE |
> - I915_ERROR_MEMORY_REFRESH));
> + intel_uncore_write(uncore, EMR, i9xx_error_mask(dev_priv));
>
> /* Unmask the interrupts that we always want on. */
> dev_priv->irq_mask =
> @@ -3755,26 +3757,28 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
> dev_priv->irq_mask = ~0u;
> }
>
> -static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
> +static u32 i965_error_mask(struct drm_i915_private *i915)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - u32 enable_mask;
> - u32 error_mask;
> -
> /*
> * Enable some error detection, note the instruction error mask
> * bit is reserved, so we leave it masked.
> */
> - if (IS_G4X(dev_priv)) {
> - error_mask = ~(GM45_ERROR_PAGE_TABLE |
> - GM45_ERROR_MEM_PRIV |
> - GM45_ERROR_CP_PRIV |
> - I915_ERROR_MEMORY_REFRESH);
> - } else {
> - error_mask = ~(I915_ERROR_PAGE_TABLE |
> - I915_ERROR_MEMORY_REFRESH);
> - }
> - intel_uncore_write(uncore, EMR, error_mask);
> + if (IS_G4X(i915))
> + return ~(GM45_ERROR_PAGE_TABLE |
> + GM45_ERROR_MEM_PRIV |
> + GM45_ERROR_CP_PRIV |
> + I915_ERROR_MEMORY_REFRESH);
> + else
> + return ~(I915_ERROR_PAGE_TABLE |
> + I915_ERROR_MEMORY_REFRESH);
May be this could be optimized to -> return i9xx_error_mask(i915) too?
In any case,
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> +}
> +
> +static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> + u32 enable_mask;
> +
> + intel_uncore_write(uncore, EMR, i965_error_mask(dev_priv));
>
> /* Unmask the interrupts that we always want on. */
> dev_priv->irq_mask =
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 5/5] drm/i915: Mask page table errors on gen2/3 with FBC
2023-01-25 18:52 ` [Intel-gfx] [PATCH 5/5] drm/i915: Mask page table errors on gen2/3 with FBC Ville Syrjala
@ 2023-02-23 12:46 ` Govindapillai, Vinod
2023-02-23 14:01 ` Ville Syrjälä
0 siblings, 1 reply; 14+ messages in thread
From: Govindapillai, Vinod @ 2023-02-23 12:46 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Hi
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
BR
vinod
PS: With this patch seems my comment for the prev patch in this series might not be relevant.
On Wed, 2023-01-25 at 20:52 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> FBC on gen2/3 seems to trigger page table errors. No visual
> artifacts are visible, and essentially the same FBC
> code works on gen4 so these seem entirely spurious. There
> are also hints in gen3 bspec indicating that certain bits
> in PGTBL_ER are just not wired up correctly in the
> hardware.
>
> Ideally we'd want to mask out only the bogus bits, but
> sadly there is no mask for PGTBL_ER, and instead we are
> forced to mask out all page table errors via EMR :(
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 22 ++++++++++++++++++++--
> 1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 081b79d00521..496f76bf42f3 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3473,8 +3473,23 @@ static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
>
> static u32 i9xx_error_mask(struct drm_i915_private *i915)
> {
> - return ~(I915_ERROR_PAGE_TABLE |
> - I915_ERROR_MEMORY_REFRESH);
> + /*
> + * On gen2/3 FBC generates (seemingly spurious)
> + * display INVALID_GTT/INVALID_GTT_PTE table errors.
> + *
> + * Also gen3 bspec has this to say:
> + * "DISPA_INVALID_GTT_PTE
> + " [DevNapa] : Reserved. This bit does not reflect the page
> + " table error for the display plane A."
> + *
> + * Unfortunately we can't mask off individual PGTBL_ER bits,
> + * so we just have to mask off all page table errors via EMR.
> + */
> + if (HAS_FBC(i915))
> + return ~I915_ERROR_MEMORY_REFRESH;
> + else
> + return ~(I915_ERROR_PAGE_TABLE |
> + I915_ERROR_MEMORY_REFRESH);
> }
>
> static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
> @@ -3762,6 +3777,9 @@ static u32 i965_error_mask(struct drm_i915_private *i915)
> /*
> * Enable some error detection, note the instruction error mask
> * bit is reserved, so we leave it masked.
> + *
> + * i965 FBC no longer generates spurious GTT errors,
> + * so we can always enable the page table errors.
> */
> if (IS_G4X(i915))
> return ~(GM45_ERROR_PAGE_TABLE |
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH 5/5] drm/i915: Mask page table errors on gen2/3 with FBC
2023-02-23 12:46 ` Govindapillai, Vinod
@ 2023-02-23 14:01 ` Ville Syrjälä
0 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2023-02-23 14:01 UTC (permalink / raw)
To: Govindapillai, Vinod; +Cc: intel-gfx@lists.freedesktop.org
On Thu, Feb 23, 2023 at 12:46:21PM +0000, Govindapillai, Vinod wrote:
> Hi
>
> Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>
> BR
> vinod
>
> PS: With this patch seems my comment for the prev patch in this series might not be relevant.
Aye.
On a related note, sometimes I do muse about unifying all
the (non-vlv/chv) gmch platform irq code into just one
copy, but in this case that wouldn't really change
anything anyway since we need different values for
different platforms.
Thaks for the review.
>
> On Wed, 2023-01-25 at 20:52 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > FBC on gen2/3 seems to trigger page table errors. No visual
> > artifacts are visible, and essentially the same FBC
> > code works on gen4 so these seem entirely spurious. There
> > are also hints in gen3 bspec indicating that certain bits
> > in PGTBL_ER are just not wired up correctly in the
> > hardware.
> >
> > Ideally we'd want to mask out only the bogus bits, but
> > sadly there is no mask for PGTBL_ER, and instead we are
> > forced to mask out all page table errors via EMR :(
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 22 ++++++++++++++++++++--
> > 1 file changed, 20 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 081b79d00521..496f76bf42f3 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3473,8 +3473,23 @@ static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
> >
> > static u32 i9xx_error_mask(struct drm_i915_private *i915)
> > {
> > - return ~(I915_ERROR_PAGE_TABLE |
> > - I915_ERROR_MEMORY_REFRESH);
> > + /*
> > + * On gen2/3 FBC generates (seemingly spurious)
> > + * display INVALID_GTT/INVALID_GTT_PTE table errors.
> > + *
> > + * Also gen3 bspec has this to say:
> > + * "DISPA_INVALID_GTT_PTE
> > + " [DevNapa] : Reserved. This bit does not reflect the page
> > + " table error for the display plane A."
> > + *
> > + * Unfortunately we can't mask off individual PGTBL_ER bits,
> > + * so we just have to mask off all page table errors via EMR.
> > + */
> > + if (HAS_FBC(i915))
> > + return ~I915_ERROR_MEMORY_REFRESH;
> > + else
> > + return ~(I915_ERROR_PAGE_TABLE |
> > + I915_ERROR_MEMORY_REFRESH);
> > }
> >
> > static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
> > @@ -3762,6 +3777,9 @@ static u32 i965_error_mask(struct drm_i915_private *i915)
> > /*
> > * Enable some error detection, note the instruction error mask
> > * bit is reserved, so we leave it masked.
> > + *
> > + * i965 FBC no longer generates spurious GTT errors,
> > + * so we can always enable the page table errors.
> > */
> > if (IS_G4X(i915))
> > return ~(GM45_ERROR_PAGE_TABLE |
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2023-02-23 14:02 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-01-25 18:52 [Intel-gfx] [PATCH 0/5] drm/i915: Error/underrun interrupt fixes Ville Syrjala
2023-01-25 18:52 ` [Intel-gfx] [PATCH 1/5] drm/i915: Mark FIFO underrun disabled earlier Ville Syrjala
2023-02-23 9:17 ` Govindapillai, Vinod
2023-01-25 18:52 ` [Intel-gfx] [PATCH 2/5] drm/i915: Undo rmw damage to gen3 error interrupt handler Ville Syrjala
2023-02-23 12:21 ` Govindapillai, Vinod
2023-01-25 18:52 ` [Intel-gfx] [PATCH 3/5] drm/i915: Dump PGTBL_ER on gen2/3/4 error interrupt Ville Syrjala
2023-02-23 12:23 ` Govindapillai, Vinod
2023-01-25 18:52 ` [Intel-gfx] [PATCH 4/5] drm/i915: Extract {i9xx, i965)_error_mask() Ville Syrjala
2023-02-23 12:34 ` Govindapillai, Vinod
2023-01-25 18:52 ` [Intel-gfx] [PATCH 5/5] drm/i915: Mask page table errors on gen2/3 with FBC Ville Syrjala
2023-02-23 12:46 ` Govindapillai, Vinod
2023-02-23 14:01 ` Ville Syrjälä
2023-01-26 2:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Error/underrun interrupt fixes Patchwork
2023-01-26 12:55 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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